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AgeCommit message (Expand)AuthorFilesLines
2022-03-26openocd: include config.h in every file .cAntonio Borneo1-0/+4
2022-03-26arm_tpiu_swo: fix autodetection of SWO pin frequencyAntonio Borneo1-4/+13
2022-03-26semihosting: fix mode flags for local host open()Antonio Borneo1-3/+18
2022-03-19breakpoints: fix build on -fno-inlineAntonio Borneo1-2/+2
2022-03-19target: Rework 'set' variable of break-/watchpointsMarc Schink21-242/+258
2022-03-19semihosting: permit redirection of semihosting I/O to TCPTarek BOCHKATI2-17/+332
2022-03-19server: change prototype of add_service()Antonio Borneo2-11/+21
2022-03-12target: Deprecate 'array2mem' and 'mem2array''Marc Schink2-50/+30
2022-03-12target/tcl: Add 'read_memory' and 'write_memory'Marc Schink1-0/+321
2022-03-12cortex_m: use LOG_TARGET_XXXTarek BOCHKATI1-106/+104
2022-03-05target/arm_tpiu: Fix usage of 'tpiu create'Marc Schink1-1/+1
2022-03-05target/arm_tpiu: Fix 'tpiu create' parameter checkMarc Schink1-1/+1
2022-03-05target/arm_tpiu: Make error message easier to understandMarc Schink1-1/+2
2022-03-05target/tcl: Add get_reg functionMarc Schink1-0/+101
2022-03-05target/tcl: Add set_reg functionMarc Schink1-0/+65
2022-02-25target/cortex_m: add Cortex-M part number getterTomas Vanek1-0/+18
2022-02-25target/armv7m,cortex_m: introduce checked arch_info cast routinesTomas Vanek2-9/+69
2022-02-25target/cortex_m: fix target_to_cm() helperTomas Vanek1-1/+1
2022-02-14Fix small memory leak.Tim Newsome1-3/+5
2022-02-14target/riscv: revive 'riscv resume_order'Tim Newsome2-3/+9
2022-02-14target/smp: use a struct list_head to hold the smp targetsAntonio Borneo13-156/+121
2022-02-05semihosting: User defined operation, Tcl command exec on hostZoltán Dudás6-4/+135
2022-01-29semihosting: use open mode flags from GDB, not from sys/stat.hPavel Kirienko1-12/+28
2022-01-29aarch64: support for aarch32 ARM_MODE_UNDJulien Massot2-0/+7
2022-01-22target: use target_event_name()Antonio Borneo1-5/+5
2022-01-22aarch64: dump a message when CTI is missingAntonio Borneo1-1/+3
2021-12-24target/riscv: calloc() memory per register.Tim Newsome2-8/+5
2021-12-24semihosting: use macro COMMAND_HANDLERAntonio Borneo1-4/+4
2021-12-18target/cortex_m: minor refactoring in cortex_m_store_core_reg_u32()Tomas Vanek1-3/+1
2021-12-11target/arm_jtag.h: fix wrong comparison in arm_jtag_set_instrBohdan Tymkiv1-1/+2
2021-12-11target/target: Check checksum_memory before callYasushi SHOJI1-0/+4
2021-12-11adi_v5_swd: add jtag-to-swd through dormantAntonio Borneo2-2/+18
2021-12-11cortex_m: remove last references to debugport_init()Antonio Borneo1-1/+0
2021-12-03target,flash: allow target_free_working_area on NULL area pointerTomas Vanek3-12/+13
2021-11-25target/hla_target: set cortex_m->common_magicTomas Vanek3-1/+16
2021-11-23openocd: use unique name for struct command_registrationAntonio Borneo2-5/+5
2021-11-23openocd: use single line for register_commands*()Antonio Borneo1-2/+1
2021-11-20target/arm_dap: check SWD DAP configurationTomas Vanek1-0/+52
2021-11-20target/adi_v5_swd: add support for SWD multidropTomas Vanek2-35/+228
2021-11-20target/arm_adi_v5,arm_dap: introduce multidrop_targetsel and its configurationTomas Vanek2-1/+65
2021-11-20target/arm_dap: clean up dap_configure codeTomas Vanek1-18/+22
2021-11-20target/adi_v5_swd: introduce swd_queue_dp_read/write_inner()Tomas Vanek1-74/+92
2021-11-20target/arm_dap: fix memory leak in error path of dap_create()Tomas Vanek1-1/+4
2021-11-20target: Use target_addr_t for algorithm addresses.Tim Newsome2-6/+6
2021-11-20riscv: Clear type 6 triggers on connecting.Tim Newsome1-0/+4
2021-11-20riscv: Regenerated debug_defines.h and encoding.hJan Matyas2-165/+1705
2021-11-20adi_v5_swd: add comment to describe debug flag 'do_sync'Antonio Borneo1-0/+1
2021-11-20arm_adi_v5: add missing enum DORMANT_TO_JTAGAntonio Borneo1-0/+1
2021-11-18cortex_m: Restore fast register reads if no polling is neededAndreas Fritiofson1-0/+10
2021-11-18target/cortex_m: faster reading of all CPU registersTomas Vanek4-11/+179
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