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2024-06-04Revert "Initialize all registers in examine"Evgeniy Naydanov1-2/+0
2024-06-04Merge pull request #1056 from aap-sc/aap-sc/no_hit_bit_statusAnatoly Parshintsev2-15/+90
2024-05-31riscv-013: Remove unused typedef slot_tremove-slot_t-from-riscv-013Jan Matyas1-6/+0
2024-05-28target/riscv: do not emit warnings when a non-existent CSR is hiddenParshintsev Anatoly1-1/+1
2024-05-28target/riscv: fix halt reason for targets that do not support hit bit on trig...Parshintsev Anatoly2-15/+90
2024-05-28Merge pull request #1033 from en-sc/en-sc/err-read-abs-argEvgeniy Naydanov3-80/+218
2024-05-23target/riscv: read abstract args using batchEvgeniy Naydanov3-80/+218
2024-05-18Merge pull request #1061 from en-sc/en-sc/dm-resetEvgeniy Naydanov1-41/+81
2024-05-17Merge pull request #1029 from MrAlexei/add_decode_wp_rvcEvgeniy Naydanov1-30/+467
2024-05-15target/riscv: only `dmactive` can be written if `dmactive` is lowEvgeniy Naydanov1-41/+81
2024-05-07Merge pull request #1064 from en-sc/en-sc/from_upstreamEvgeniy Naydanov1-2/+2
2024-05-02Merge pull request #1028 from en-sc/en-sc/busy-reset-batchEvgeniy Naydanov5-29/+45
2024-04-30Add functions to decode RVC load and store instructionsAleksey Lotosh1-30/+467
2024-04-27Merge pull request #1031 from aap-sc/aap-sc/hart_status_info_fixupEvgeniy Naydanov1-8/+31
2024-04-27Merge pull request #1055 from aap-sc/aap-sc/bp_unitializedEvgeniy Naydanov1-3/+7
2024-04-27Merge up to 04154af5d6cd5fe76a2583778379bdacb5aa6fb0 from upstreamEvgeniy Naydanov1-2/+2
2024-04-26target/riscv: reset delays during batch scansEvgeniy Naydanov5-29/+45
2024-04-26Merge pull request #1025 from en-sc/en-sc/dump-fieldEvgeniy Naydanov5-76/+49
2024-04-26Merge pull request #1046 from en-sc/en-sc/reg-rv011-segfault-propperEvgeniy Naydanov1-4/+4
2024-04-24fix confusing status messages during resumeParshintsev Anatoly1-8/+31
2024-04-24target/riscv: use breakpoint_hw_set/watchpoint_set to properly initialize bp/...Parshintsev Anatoly1-3/+7
2024-04-23target/riscv/riscv-011: pc and dpc should be cached at the same locationEvgeniy Naydanov1-2/+2
2024-04-20target/riscv/riscv-011.c: fix access to non-existent registerEvgeniy Naydanov1-4/+4
2024-04-19target/riscv: decode DMI scans in batch accessEvgeniy Naydanov5-76/+49
2024-04-14Merge pull request #1040 from rivos-eblot/dev/ebl/read_mem_dmibaseEvgeniy Naydanov1-1/+5
2024-04-14Merge pull request #1023 from en-sc/en-sc/check-ac-busyEvgeniy Naydanov1-80/+239
2024-04-14Merge pull request #1039 from en-sc/en-sc/running-cacheEvgeniy Naydanov1-1/+2
2024-04-11target/riscv: check `abstractcs.busy`Evgeniy Naydanov1-6/+73
2024-04-11target/riscv: introduce `examine_dm()` functionEvgeniy Naydanov1-73/+131
2024-04-10target/riscv: cache `abstractcs.busy` in `dm013_info_t`Evgeniy Naydanov1-2/+36
2024-04-07target/mips32: fix clang sbuild check failWalter Ji1-2/+2
2024-04-05target/riscv: read registers are not valid on a running targetEvgeniy Naydanov1-1/+2
2024-04-04target/riscv: Add missing DM base offset to read_memory_bus_v1()Emmanuel Blot1-1/+5
2024-03-28Merge up to a35e254c5383008cdacf7838a777f7f17af5eeb1 from upstreamEvgeniy Naydanov11-61/+748
2024-03-24target/adi_v5_swd: move setting of do_reconnect one level upTomas Vanek1-12/+10
2024-03-24helper/list: include the correct header fileAntonio Borneo1-0/+1
2024-03-21[NFC] target/riscv: refactor `init_registers()`Evgeniy Naydanov3-379/+529
2024-03-16target/mips32: add fpu access supportWalter Ji4-12/+245
2024-03-16target: aarch64: add support for 32 bit MON modeAntonio Borneo1-0/+3
2024-03-16target/adi_v5_swd: fix DP registers bankingTomas Vanek1-6/+9
2024-03-16target/arm_adi_v5: introduce adiv5_jim_configure_ext()Tomas Vanek4-26/+29
2024-03-09target/mips32: add dsp access supportWalter Ji2-1/+447
2024-03-09mem_ap: fix GDB connectionsAntonio Borneo1-4/+4
2024-03-07Merge up to 07141132a7d787005c0829618a60b4a842be7847 from upstreamEvgeniy Naydanov4-71/+74
2024-03-02target/esp_xtensa_smp: don't use coreid as an SMP indexErhan Kurubas1-2/+5
2024-02-27Merge pull request #977 from kr-sc/kr-sc/improve-riscv-controlsEvgeniy Naydanov2-80/+68
2024-02-24src/target/riscv: Help older compilersSevan Janiyan1-1/+1
2024-02-24Merge pull request #1018 from en-sc/en-sc/from_upstreamEvgeniy Naydanov1-36/+12
2024-02-21Merge pull request #1014 from riscv-collab/riscv-batch-cleanupEvgeniy Naydanov5-82/+93
2024-02-16Merge pull request #1016 from tom-van/free-dm-target_listEvgeniy Naydanov1-0/+25
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