riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-16	Merge pull request #799 from riscv/icount	Tim Newsome	1	-15/+126
2023-02-15	target/riscv: hide_csrs configuration option (#787)	Anatoly Parshintsev	2	-0/+48
2023-02-15	Add command "exec_progbuf" (#795)	Jan Matyas	3	-9/+65
2023-02-15	Add `riscv icount` command.	Tim Newsome	1	-15/+126
2023-02-14	Merge pull request #794 from riscv/fix-fence-instruction	Tim Newsome	4	-7/+8
2023-02-10	Merge pull request #797 from riscv/Zve32	Tim Newsome	3	-39/+65
2023-02-10	Don't reuse a single riscv_program.	Tim Newsome	1	-5/+7
2023-02-10	If XLEN=64 and vsew=64 fails, fall back to vsew=32.	Tim Newsome	3	-27/+51
2023-02-10	CSR_MCOUNTEREN should not exist if U-mode is not supported	Parshintsev Anatoly	1	-0/+3
2023-02-08	Print out debug value after the assignment is made.	Tim Newsome	1	-1/+1
2023-02-08	Move yes_no_maybe_t into riscv.h.	Tim Newsome	2	-6/+6
2023-02-01	Fix opcode for the "fence" instruction	Jan Matyas	4	-7/+8
2023-01-10	target/riscv: added support for missing VCSR register	Parshintsev Anatoly	3	-0/+3
2023-01-04	Merge pull request #777 from riscv/itrigger	Tim Newsome	2	-22/+289
2023-01-03	target/riscv: Remove `riscv test_sba_config_reg` command. (#780)	Tim Newsome	3	-404/+0
2023-01-03	target/riscv: Use unsigned int for trigger indexes.	Tim Newsome	1	-7/+12
2023-01-03	target/riscv: Read back tdata2 in set_trigger()	Tim Newsome	1	-4/+14
2023-01-02	target/riscv: Add `riscv etrigger` command.	Tim Newsome	2	-0/+118
2023-01-02	target/riscv: Add `riscv itrigger` command.	Tim Newsome	2	-7/+141
2022-12-27	target/riscv: Use macros for trigger types.	Tim Newsome	1	-6/+6
2022-12-02	riscv/run_algorithm : Add support for memory parameters (#773)	Dolu1990	1	-5/+27
2022-11-29	target/riscv: Set target->state in riscv013_halt_go()	Tim Newsome	1	-2/+14
2022-11-23	target/riscv: Fix small riscv013_halt_go() bug	Tim Newsome	1	-1/+1
2022-11-23	target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK	Tim Newsome	3	-4/+4
2022-11-23	target/riscv: Set correct target->state in riscv013_halt_go()	Tim Newsome	1	-3/+26
2022-11-22	target/riscv: Don't resume unavailable harts.	Tim Newsome	2	-7/+19
2022-11-22	target/riscv: Share single-target and SMP resume code.	Tim Newsome	1	-30/+33
2022-11-22	target/riscv: Make poll() use TARGET_UNAVAILABLE.	Tim Newsome	2	-60/+152
2022-11-21	target/riscv: Refactor riscv_openocd_poll()	Tim Newsome	1	-101/+74
2022-11-21	target/riscv: Error when hart becomes unavailable during resume	Tim Newsome	1	-0/+2
2022-11-21	Merge pull request #769 from riscv/0.11	Tim Newsome	2	-27/+22
2022-11-17	target/riscv: 0.11, call handle_halt() after step	Tim Newsome	1	-1/+3
2022-11-17	target/riscv: Ignore maskmax when reading back tdata1	Tim Newsome	1	-15/+18
2022-11-17	target/riscv: Don't always read on DMI batch write (#768)	Tim Newsome	3	-13/+19
2022-11-17	target/riscv: Ignore debug_execution in 0.11 resume	Tim Newsome	1	-11/+1
2022-11-16	Fix breackpoint_add for rtos swbp (#734)	Evgeniy Naydanov	1	-13/+4
2022-11-15	Workaround for fp register access in case fp unit is disabled (#766)	Evgeniy Naydanov	1	-11/+11
2022-11-10	target/riscv: Use vlenb to check whether vector registers exist (#762)	Tim Newsome	3	-24/+13
2022-11-10	riscv/target: Replace is_halted() with get_hart_state() (#756)	Tim Newsome	3	-61/+84
2022-11-09	Use match field for trigger (#725)	Xiang W	3	-193/+305
2022-11-09	target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)	Tim Newsome	1	-5/+16
2022-11-01	Fix dm->current_hartid corruption on hartsellen discovery (#754)	Dolu1990	1	-1/+9
2022-10-27	target: Add TARGET_UNAVAILABLE state. (#752)	Tim Newsome	2	-0/+4
2022-10-21	target/riscv: Correctly set target->state in deassert_reset (#750)	Tim Newsome	1	-2/+7
2022-10-14	[riscv] step operation handler should respect handle_breakpoints parameter (#...	Anatoly Parshintsev	1	-3/+22
2022-10-12	Properly track selecting multiple harts at once. (#743)	Tim Newsome	1	-59/+64
2022-10-11	target/riscv: Clean up halt_go for multiple harts.	Tim Newsome	1	-6/+11
2022-10-07	Fix incorrect braces caused by #732	Dmitry Ryzhov	1	-2/+2
2022-10-05	riscv: Minor formatting cleanup.	Tim Newsome	1	-9/+7
2022-09-30	Remove riscv_info_t.current_hartid	Tim Newsome	4	-121/+79