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AgeCommit message (Expand)AuthorFilesLines
2020-11-07target/image: Use proper data typesMarc Schink5-42/+32
2020-11-07semihosting: print the semihosting operation idAdrian Negreanu2-2/+2
2020-11-07armv7m: add a TCP channel to stream captured traceTarek BOCHKATI2-19/+120
2020-11-07server: permit the add_service function to return the created serviceTarek BOCHKATI1-1/+2
2020-11-04target/adi_v5_jtag: remove unused global variableAntonio Borneo1-1/+1
2020-11-04cortex_m: declare local functions as staticAntonio Borneo2-6/+3
2020-11-04target: declare local symbols as staticAntonio Borneo19-51/+48
2020-11-04target: handle command 'target current' when no target is presentAntonio Borneo1-1/+3
2020-11-04gdb_server: allow multiple GDB connections to selected targetsAntonio Borneo2-3/+27
2020-11-04target/arm_cti: use adiv5_jim_mem_ap_spot_configure()Antonio Borneo2-101/+47
2020-11-04target/arm_adi_v5: add helper to get mem_ap spot in configure/cgetAntonio Borneo2-85/+135
2020-10-30target: restore last run state after profilingChristopher Head1-1/+13
2020-10-30target/cortex_m: reduce duplication in profilingChristopher Head3-47/+24
2020-10-30target: allow profiling from runningChristopher Head2-4/+6
2020-10-24target/arc: introduce watchpoints supportEvgeniy Didin1-3/+165
2020-10-22cortex_m: support control.FPCASylvain Chouleur3-7/+7
2020-10-21Add before/after timestamps to memory sampling. (#550)Tim Newsome3-12/+18
2020-10-16Merge pull request #549 from riscv/from_upstream_histogramTim Newsome95-2270/+1913
2020-10-16Allow riscv_semihosting without 16 bit access to memory with instructions (#544)Samuel Obuch3-13/+19
2020-10-15Make it build again.Tim Newsome3-228/+1
2020-10-15Merge branch 'master' into from_upstream_histogramTim Newsome95-2269/+2139
2020-10-14riscv: fix compile errorAntonio Borneo1-2/+2
2020-10-14Upstream tons of RISC-V changes.Tim Newsome14-2659/+7226
2020-10-12Do not throw error if RISC-V tselect unimplemented (#542)Tobias Kaiser1-2/+8
2020-10-11target/aarch64: fix use of 'target->private_config'Antonio Borneo1-0/+5
2020-10-11target/aarch64: Use apnum settingKevin Yang1-10/+14
2020-10-07Add memory sample feature (#541)Tim Newsome5-77/+505
2020-10-03target/cortex_m.c: vector_catch command checks if a target is examinedDaniel Trnka1-0/+5
2020-10-03target/aarch64: a64 disassemblerMete Balci4-1/+218
2020-10-01Improve support for GD32VF103 MCU (#538)Tom Hebb1-14/+15
2020-10-01Improve riscv expose_[csrs|custom] commands (#536)Samuel Obuch2-110/+204
2020-09-28riscv: remove unused riscv_error_t type (#539)Tom Hebb2-12/+0
2020-09-28riscv: remove outdated documentation in riscv.c (#540)Tom Hebb1-42/+0
2020-09-28Minor cleanups. (#537)Tim Newsome3-6/+6
2020-09-27Use capstone for ARM disassemblerMarc Schink4-1615/+112
2020-09-20cortex_m: add detection of Cortex M35P and M55Tarek BOCHKATI2-3/+9
2020-09-20cortex_m: read and display core security stateTarek BOCHKATI3-1/+25
2020-09-20armv8-m: add SecureFault exceptionTarek BOCHKATI3-1/+12
2020-09-17Allocate RISC-V arch_info during target creation (#531)Jan Matyas4-10/+25
2020-09-15{read_from,write_to}_buf -> buf_[sg]et_u{32,64} (#529)Tim Newsome1-114/+18
2020-09-15Make a couple variables static. (#528)Tim Newsome2-4/+2
2020-09-14Allow to put breakpoints in memories without 16 bit access (#525)Samuel Obuch1-7/+126
2020-09-10Selection of memory access methods, aampostincrement detection (#508)Samuel Obuch3-100/+445
2020-09-10Add empty usage strings back in. (#526)Tim Newsome1-0/+4
2020-09-05target: avoid checking for non NULL pointer to free itAntonio Borneo11-87/+43
2020-09-05openrisc: Fix segv jsp due to free of unallocated dataStafford Horne1-6/+0
2020-09-05openocd: fix command's usage stringAntonio Borneo2-5/+5
2020-09-05target/arc: fix command's usage stringAntonio Borneo1-10/+10
2020-09-05target: use proper format with uint32_tAntonio Borneo30-121/+121
2020-09-05adi_v5: use macro DP_APSEL_MAX to allocate struct adiv5_apAntonio Borneo1-1/+1
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