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2019-06-14Reversed hart loop order in riscv_resume_go_all_hartsreverse-resume-ordercgsfv1-1/+1
2019-06-10Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)Paul George3-82/+150
* Inverted Frame to Pseudo Tap for Simpler Hardware to Decode Given the variable supported message length , a prefix decoding approach is significantly simpler for a pseudo tap architecture with a shift reg of len = max len of packet. This prefix coding packet also makes the message len field redundant , as that is implict in ir_len and the ir selected. * style patch * non-conflict with original * style patch * style patch * requested changes * style-patch
2019-05-21Don't write sbcs while sbbusy is set. (#375)Tim Newsome1-9/+24
* Fix small SBA bug. We were not compliant with the spec, but I'm not sure if this was causing problems for anybody. Change-Id: Ia31ee400fd75ad907349c4dd995b1e03bd2116c7 * Don't write sbcs while sbbusy is set. Probably not hurting anything, but the spec says we shouldn't. Also propagate more errors, and fully decode sbcs in debug output. Change-Id: I1a36646772fe794c8780702565103a309bbcc5e9
2019-05-20RISC-V: Make compliance tests more verbose (#366)Philipp Wagner1-2/+10
Currently the RISC-V compliance test suite doesn't output the test is currently runs before it succeeds. It also uses the same message for many tests. This makes it very hard to find out which test fails. This commit makes things slightly easier by printing the test that's being executed before it actually runs, and by adding the source code line where the test is located, making it easier to look up the test in the source code. New output looks like this: Info : Executing test 149 (riscv-013.c:3800): Regular calls must return ERROR_OK Info : PASSED
2019-05-20RISC-V compliance test: target must be examined (#367)Philipp Wagner1-0/+6
The test assumes that the target has been examined. If that fails (for whatever reason) the test will segfault: Program received signal SIGSEGV, Segmentation fault. register_cache_invalidate (cache=0x0) at ../src/target/register.c:109 109 struct reg *reg = cache->reg_list; (gdb) bt 0 register_cache_invalidate (cache=0x0) at ../src/target/register.c:109 1 0x0000000000520735 in riscv_invalidate_register_cache (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2160 2 0x000000000052224f in riscv_halt_all_harts (target=target@entry=0x779b50) at ../src/target/riscv/riscv.c:2022 3 0x0000000000574e82 in riscv013_test_compliance (target=0x779b50) at ../src/target/riscv/riscv-013.c:3600
2019-05-16More helpful debug output. (#374)Tim Newsome1-1/+1
I often want to see what OpenOCD is telling gdb, and it's annoying to have to recompile. Change-Id: Icce07606f253d67e2523cf2732dbe5042c6e483e
2019-05-09Simultaneous halt (#372)Tim Newsome3-170/+221
* WIP Change-Id: I4f50dced77e9ded4a58ab152824a841a73bc0dc1 * riscv_halt() only halt harts that are running. Progress towards simultaneous halt. Change-Id: I749b6d9ba5e77aa7aca4342c7af841312b78be0e * -rtos riscv passes. But dual gdb is failing again. Change-Id: I1747ba42ce3f3062f6e8c28a75ac40e17f80e980 * Dual gdb works again. -rtos riscv still works. Change-Id: Idddddda79e5918b26e181384def1a305ecceced2 * -rtos hwthread almost completely works. Change-Id: I845feb0bd93484e28ca8620f4760c234d4ce5310 * Maybe better? Change-Id: I669c67e83acf1b749bfb534d3b3c0915c129d686 * All three methods work. Change-Id: If77074fa43f6420d1ec9b594fe366415f5a41f2c * Fix hitting hardware triggers with `-rtos riscv`. Change-Id: I8d4600e1c66fa0e3b9d986b96a5973d09f40735c * Fix halting dual core E31. Change-Id: Ic2d885e027312b68e2f3c6854957fbfee09f814b * Not addressing this TODO right now. Change-Id: Ic7c0d32424068ae1de04d37d15a411c1957207c4 * Remove duplicate line. Change-Id: I14fe8d422f23c97afdaa20a02c0e3ab568219467
2019-04-23Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel ↵Greg Savin3-2/+221
(#370) Including adjustments in response to review comments.
2019-04-09Propagate some errors in execute_abstract_command().Tim Newsome1-3/+4
Change-Id: Ia3ec457dd5d65378a6c922802713e36d6828bcea
2019-04-03Merge branch 'master' into from_upstreamTim Newsome42-540/+605
Conflicts: src/flash/nor/at91sam4.c src/flash/nor/at91sam4l.c src/flash/nor/at91samd.c src/flash/nor/ath79.c src/flash/nor/atsame5.c src/flash/nor/cfi.c src/flash/nor/core.c src/flash/nor/fespi.c src/flash/nor/kinetis.c src/flash/nor/kinetis_ke.c src/flash/nor/lpc2000.c src/flash/nor/niietcm4.c src/flash/nor/nrf5.c src/flash/nor/numicro.c src/flash/nor/pic32mx.c src/flash/nor/stm32h7x.c src/flash/nor/stm32lx.c src/flash/nor/stmsmi.c src/flash/nor/tcl.c src/flash/nor/tms470.c src/flash/nor/virtual.c src/flash/nor/xmc4xxx.c src/rtos/hwthread.c src/rtos/rtos.c src/server/gdb_server.c src/target/riscv/riscv-011.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
2019-04-03Support simultaneous resume using hasel (#364)Tim Newsome4-190/+299
* Remove unnecessary 0.11 code. Don't need need_strict_step anymore now that we have riscv_hit_watchpoint(). Don't need 32-bit warning in riscv011_resume() now that address is a target_address_t. Change-Id: I375c023a7ec9f62d80b037ddb64d14526ba0a3dc * WIP little refactor working towards hasel support. Change-Id: Ie0b8dfd9e5ae2e36613fa00e14c3cd32749141bf * More refactoring. Change-Id: I083387c2ecff78ddfea3ed5078444732d77b909b * More refactoring. Change-Id: Icea1308499492da51354f89e1529353e8385f3a1 * Starting to work towards actual hasel changes. Change-Id: If0df05ffa66cc58400b4855f9630a8b1bae3030e * Implement simultaneous resume using hasel. Change-Id: I97971d7564fdb159d2052393c8b82a2ffaa8833f * Add support back for targets that don't have hasel. Change-Id: I6d5439f0615d5d5333127d280e4f2642649a119a * Make hasel work with >32 harts. Change-Id: I3c55009d48bfc5dd62e3341df4e4bd21df2fe44f
2019-04-03armv7a_mmu: Remove warning on va = paFlorian Fainelli1-2/+0
Depending on how the MMU is configured it is possible to have a 1:1 mapping between virtual and physical addresses, thus making this warning bogus. We already check that the MMU is enabled in the caller: cortex_a_virt2phys(). Change-Id: I09f4c53ef933c8d1e268da5215a769449be014bc Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-on: http://openocd.zylin.com/5007 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-03target/cortex_m: remove target halted check when removing a breakpointTomas Vanek1-9/+3
Remove the target halted check from cortex_m_remove_breakpoint() as there is no such check in cortex_m_set_breakpoint() and bp can be safely removed from the running target. While on it return the error code from cortex_m_unset_breakpoint() to higher level. Change-Id: I2b358c3661feed84297913e9f589bdf1e4de7e64 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4887 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2019-04-01target/cortex_m: remove fp_code_available countingTomas Vanek2-18/+1
fp_code_available looses sync with the real number of free comparators as soon as cortex_m_set_breakpoint() returns an error. Remove the counter and always go through the fp_comparator_list to find a free one. Change-Id: I9f6e06c36d8a57ad11df5155e8a1a3aff6d833a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4870 Tested-by: jenkins Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-04-01target/cortex_m: simplify cortex_m_unset_breakpoint()Tomas Vanek1-10/+4
Cortex-M uses only 2 byte breakpoint instruction. cortex_m_unset_breakpoint() does not need to check breakpoint->length, use the length as the size argument in target_write_memory() Change-Id: I20bb869f6abce2fc61f0469e34a638bc4dc6f7ce Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4889 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Jānis Skujenieks <janis.skujenieks@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2019-03-27smp: move sub-command "smp_gdb" in file smp.cAntonio Borneo3-56/+28
The code for this command is currently replicated in cortex_a and in mips_m4k and is going to be added again for cortex_m. Plus, it is going to be obsoleted by the HW thread pseudo RTOS. Consolidate in smp.c a single instance of the command. This will simplify both obsoleting it and adding it to cortex_m, whatever change comes first. Change-Id: I03cd857e21fa3f7202fdcee36bcbd5aae30a609d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4991 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27smp: replace commands smp_on/smp_off with "smp [on|off]"Antonio Borneo5-154/+96
Seams over-engineered having two separate commands to turn SMP on/off. Plus it is missing the possibility to dump the current status of SMP and would be weird adding an additional command for it. Moreover, such commands are replicated in few targets so it would make sense centralizing them. - Deprecate the commands "smp_on" and "smp_off". - Add a new command "smp" that accepts optional parameters "[on|off]" and prints the SMP status when run without parameters. This replaces the two commands above. - Put the deprecated and the new command handlers in smp.c - Update the documentation, except for mips_m4k, since it is not available yet. - Promote the macro foreach_smp_target to global context and use it where possible. Change-Id: Ia72841c1a3bd6edd4db4cc809046322f498617e6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4615 Tested-by: jenkins Reviewed-by: Graham Sanderson <graham.sanderson@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-27Lots of RISC-V improvements.Tim Newsome7-379/+1764
This represents months of continuing RISC-V work, with too many changes to list individually. Some improvements: * Fixed memory leaks. * Better handling of dbus timeouts. * Add `riscv expose_custom` command. * Somewhat deal with cache coherency. * Deal with more timeouts during block memory accesses. * Basic debug compliance test. * Tell gdb which watchpoint hit. * SMP support for use with -rtos hwthread * Add `riscv set_ir` Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4922 Tested-by: jenkins Reviewed-by: Philipp Guehring <pg@futureware.at> Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-03-23mips32: pracc: Fix indentMarek Vasut1-3/+3
Fix indent of the macros in header file, no functional change. Change-Id: I4d1dba5725155200148d1543c45bad919f6cd37e Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4995 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2019-03-23mips32: pracc: Fix UPPER/LOWER macrosMarek Vasut1-2/+2
These macros are missing parenthesis around the argument, which can lead to side effects, add them. Replace the argument name to avoid conflict with uint32_t data type, since the macro can be applied to other data types as well. Change-Id: I32d2ffec6c062795d7c8bb23d1dfa3378bfc3a58 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4994 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2019-03-14target/mips: Use 'bool' data typeMarc Schink2-15/+15
Change-Id: Ifb114bfc062ed7c0ff6e4f37a1a6d546f5415344 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4970 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-14target/xscale: Use 'bool' data typeMarc Schink1-15/+15
Change-Id: I4e117f4e6c8c0850f565587f68f41d88da0d6b0b Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4968 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-14target/dsp563xx: Use 'bool' data typeMarc Schink1-23/+23
Change-Id: Ie7ee82bf04c76ef899ae8b19105158e71b69ae2c Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4962 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-14target/adi_v5_swd: improve error check while updating DP_SELECTAntonio Borneo1-13/+42
Write to register DP_SELECT can fail, but both functions swd_queue_dp_bankselect() and swd_queue_ap_bankselect() return void and do not propagate the error. Change the return type of the two functions to int and check the returned value. Invalidate the cached value of DP_SELECT if the write fails. Change-Id: Iba6ef8b0c2332e7f7efb66337d558fb7a4a0d39c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4980 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-03-14target/adi_v5_swd: update cached value on write to DP_SELECTAntonio Borneo1-1/+4
When the register DP_SELECT is written directly, e.g. with command <dap> dpreg 8 <value> the cached value in OpenOCD is not completely updated with the new value, thus creating issues in the following AP and DP read/write that rely on the cached value. Update the cached value while writing to DP_SELECT. Change-Id: I8221b10cd6fc1fbe73e6b834b68820b43480e1a2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4979 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-03-12target/breakpoints: make internal functions staticTomas Vanek1-4/+6
While on it add two missing new lines. Change-Id: I0d54740479bc462b734f91686f0931824796b598 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4888 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
2019-03-08gdb_server, target: Add target_address_bits()Tim Newsome4-1/+39
Targets can use this to expose how many address bits there are. gdb_server uses this to send gdb the appropriate upper limit in the memory-map. (Before this change the upper limit would only be correct for 32-bit targets.) Change-Id: Idb0933255ed53951fcfb05e040674bcdf19441e1 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4947 Tested-by: jenkins Reviewed-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-03-06target/openrisc/x86_32_common: Use 'bool' data typeMarc Schink1-12/+12
Change-Id: I395a36ddd7ac7e85bc54f6bb073a93b0c6f24db0 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4972 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/openrisc/or1k: Use 'bool' data typeMarc Schink1-8/+8
Change-Id: I6393bb8503d64947a1f2349e1d14c1552cabf927 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4971 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/lakemont: Use 'bool' data typeMarc Schink1-12/+12
Change-Id: I9baaf617c2bfabd07ac3ca195e486893d7950398 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4969 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/feroceon: Use 'bool' data typeMarc Schink1-6/+6
Change-Id: I30b8d07ee198e8f67cd98f83c4bec15bcfe8be08 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4967 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/etb: Use 'bool' data typeMarc Schink1-4/+4
Change-Id: I536036b15af10bb1879dbbec84576134fd3dce35 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4966 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/arm_semihosting: Use 'bool' data typeMarc Schink1-6/+6
Change-Id: I05245b7dc9c37ea8e0e40672070fb3e87cb7683f Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4965 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/embeddedice: Use 'bool' data typeMarc Schink1-4/+4
Change-Id: I0f237e0769786aa560d1a472a71499d3856ab25c Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4964 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/cortex_a: Use 'bool' data typeMarc Schink1-6/+6
Change-Id: I055767f1c20af539159ee59e35de8dd20b399fa4 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4963 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/avr32_ap7k: Use 'bool' data typeMarc Schink1-8/+8
Change-Id: I49f1a6c6ee6d175935eb40b49abf8ebdf56a0b6e Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4961 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/arm926ejs: Use 'bool' data typeMarc Schink1-3/+3
Change-Id: I3016a8ba37942d674017c09e4540d9813c832872 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4960 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/arm920t: Use 'bool' data typeMarc Schink1-7/+7
Change-Id: I5f2c95d9a4bdb14cc31d72eb026f58710fb07db5 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4959 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/arm720t: Use 'bool' data typeMarc Schink1-3/+3
Change-Id: I9838d0d0ba472f029169ab37597ef367a6084fbf Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4958 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/aarch64: Use 'bool' data typeMarc Schink1-2/+2
Change-Id: Ibfe4413b88ed0759a556a8777dac40f0c2c64922 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4957 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/armv8: Use 'bool' data typeMarc Schink1-8/+8
Change-Id: I65def33f24187ab336db5732ce35200ca5cd8f5f Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4956 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/armv7m: Use 'bool' data typeMarc Schink1-16/+16
Change-Id: I9cfbba9d81601cc72e2b54ec410e21c7edc4f1c4 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4955 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/arm11: Use 'bool' data typeMarc Schink1-2/+2
Change-Id: Ia09adeab88eaf66c009f94be25ab82b0b8f88f61 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4954 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/armv7_9_common: Use 'bool' data typeMarc Schink1-34/+34
Change-Id: I5af27247f39cf47c925260784e21292f34665471 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4953 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/armv4_5: Use 'bool' data typeMarc Schink1-13/+13
Change-Id: I82e3963ea662844bb96943aee849dab35ea96bb3 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4952 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/register: Use 'bool' data typeMarc Schink1-4/+4
Change-Id: I3633ced9cb2bfe6afb0ef49aa42fd1b54f155a66 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4951 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/cortex_m: Use 'bool' instead of 'int'Marc Schink2-9/+9
Change-Id: I273d24997e2c844015e144a15981f8f0af522261 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4950 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target: Remove unused variable 'has_percent'Marc Schink1-1/+0
Change-Id: Ib080fc33e8a0305990ee334019547e7643c446ac Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4949 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-03-05Set up halt groups for SMP groups. (#353)Tim Newsome3-164/+616
If the hardware supports it, when one hart in an SMP group halts all the other harts in that same SMP group will automatically, quickly, halt as well. Change-Id: Ida81f1309c180674e8c9d8060e3d2a4bbb910a6f
2019-03-04armv8: allow halt on exceptionMatthias Welwarsky5-2/+80
add command 'catch_exc' to halt a core on entering any of Secure EL1 or EL3 or Non-Secure EL1 or EL2. Change-Id: I0c68e247af68dd96616855a9bc1063c277d222e5 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4479 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
generated by cgit v1.1 at 2024-09-10 13:39:47 +0000