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AgeCommit message (Expand)AuthorFilesLines
2019-06-14Reversed hart loop order in riscv_resume_go_all_hartsreverse-resume-ordercgsfv1-1/+1
2019-06-10Inverted Frame to Pseudo Tap for Simpler Hardware to Decode DR (#373)Paul George3-82/+150
2019-05-21Don't write sbcs while sbbusy is set. (#375)Tim Newsome1-9/+24
2019-05-20RISC-V: Make compliance tests more verbose (#366)Philipp Wagner1-2/+10
2019-05-20RISC-V compliance test: target must be examined (#367)Philipp Wagner1-0/+6
2019-05-16More helpful debug output. (#374)Tim Newsome1-1/+1
2019-05-09Simultaneous halt (#372)Tim Newsome3-170/+221
2019-04-23Support for driving RISC-V DM via Arty's own JTAG chain using BSCAN tunnel (#...Greg Savin3-2/+221
2019-04-09Propagate some errors in execute_abstract_command().Tim Newsome1-3/+4
2019-04-03Merge branch 'master' into from_upstreamTim Newsome42-540/+605
2019-04-03Support simultaneous resume using hasel (#364)Tim Newsome4-190/+299
2019-04-03armv7a_mmu: Remove warning on va = paFlorian Fainelli1-2/+0
2019-04-03target/cortex_m: remove target halted check when removing a breakpointTomas Vanek1-9/+3
2019-04-01target/cortex_m: remove fp_code_available countingTomas Vanek2-18/+1
2019-04-01target/cortex_m: simplify cortex_m_unset_breakpoint()Tomas Vanek1-10/+4
2019-03-27smp: move sub-command "smp_gdb" in file smp.cAntonio Borneo3-56/+28
2019-03-27smp: replace commands smp_on/smp_off with "smp [on|off]"Antonio Borneo5-154/+96
2019-03-27Lots of RISC-V improvements.Tim Newsome7-379/+1764
2019-03-23mips32: pracc: Fix indentMarek Vasut1-3/+3
2019-03-23mips32: pracc: Fix UPPER/LOWER macrosMarek Vasut1-2/+2
2019-03-14target/mips: Use 'bool' data typeMarc Schink2-15/+15
2019-03-14target/xscale: Use 'bool' data typeMarc Schink1-15/+15
2019-03-14target/dsp563xx: Use 'bool' data typeMarc Schink1-23/+23
2019-03-14target/adi_v5_swd: improve error check while updating DP_SELECTAntonio Borneo1-13/+42
2019-03-14target/adi_v5_swd: update cached value on write to DP_SELECTAntonio Borneo1-1/+4
2019-03-12target/breakpoints: make internal functions staticTomas Vanek1-4/+6
2019-03-08gdb_server, target: Add target_address_bits()Tim Newsome4-1/+39
2019-03-06target/openrisc/x86_32_common: Use 'bool' data typeMarc Schink1-12/+12
2019-03-06target/openrisc/or1k: Use 'bool' data typeMarc Schink1-8/+8
2019-03-06target/lakemont: Use 'bool' data typeMarc Schink1-12/+12
2019-03-06target/feroceon: Use 'bool' data typeMarc Schink1-6/+6
2019-03-06target/etb: Use 'bool' data typeMarc Schink1-4/+4
2019-03-06target/arm_semihosting: Use 'bool' data typeMarc Schink1-6/+6
2019-03-06target/embeddedice: Use 'bool' data typeMarc Schink1-4/+4
2019-03-06target/cortex_a: Use 'bool' data typeMarc Schink1-6/+6
2019-03-06target/avr32_ap7k: Use 'bool' data typeMarc Schink1-8/+8
2019-03-06target/arm926ejs: Use 'bool' data typeMarc Schink1-3/+3
2019-03-06target/arm920t: Use 'bool' data typeMarc Schink1-7/+7
2019-03-06target/arm720t: Use 'bool' data typeMarc Schink1-3/+3
2019-03-06target/aarch64: Use 'bool' data typeMarc Schink1-2/+2
2019-03-06target/armv8: Use 'bool' data typeMarc Schink1-8/+8
2019-03-06target/armv7m: Use 'bool' data typeMarc Schink1-16/+16
2019-03-06target/arm11: Use 'bool' data typeMarc Schink1-2/+2
2019-03-06target/armv7_9_common: Use 'bool' data typeMarc Schink1-34/+34
2019-03-06target/armv4_5: Use 'bool' data typeMarc Schink1-13/+13
2019-03-06target/register: Use 'bool' data typeMarc Schink1-4/+4
2019-03-06target/cortex_m: Use 'bool' instead of 'int'Marc Schink2-9/+9
2019-03-06target: Remove unused variable 'has_percent'Marc Schink1-1/+0
2019-03-05Set up halt groups for SMP groups. (#353)Tim Newsome3-164/+616
2019-03-04armv8: allow halt on exceptionMatthias Welwarsky5-2/+80
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