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2024-04-07target/mips32: fix clang sbuild check failWalter Ji1-2/+2
Initialized `value` variables that could only be set in a branch. Change-Id: Iec7413ade9d053c93352a58ff954ad49a6545923 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8179 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-03-16target/mips32: add fpu access supportWalter Ji1-11/+84
Add access to fpr and cp1 registers. GDB can now check the FPRs with `info reg f` and change them. Checkpatch-ignore: MACRO_ARG_REUSE Change-Id: I63896ab6f6737054d8108db105a13a58e1446fbc Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7866 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-03-09target/mips32: add dsp access supportWalter Ji1-0/+428
Add access to dsp registers and a command for dsp related operations. Checkpatch-ignore: MACRO_ARG_REUSE Change-Id: I30aec0b9e4984896965edb1663f74216ad41101e Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7867 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-01-13target/mips32: fix false positive from clangAntonio Borneo1-8/+9
clang build triggers an error for an uninitialized value of the variable 'instr'. This is a false positive, as the macro #define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT) guarantees the switch/case already covers all the possible values with cases 0, 1, 2 and 3. Silent clang by adding a useless default case to the switch. While there, fix the indentation of the switch/case accordingly to OpenOCD coding style. Change-Id: I0ae316754ce7d091dd8366bf314b8e6ee780e313 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 7de4b1202d50 ("target/mips32: add cpu info detection") Reviewed-on: https://review.openocd.org/c/openocd/+/8065 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2024-01-06target/mips32: optimize pracc accessWalter Ji1-0/+38
Update mips32 instructions, add barrier and sync related insts. Add SYNC and barrier instruction blocks for memory access safety. These instructions are not supported on Lexra and/or MIPSr1 CPUs, detections were added and they will be executed conditionally. Rework mips32_pracc_read/write_regs function. Checkpatch-ignore: MACRO_ARG_REUSE Change-Id: Ib14112f37ff1f060b1633df73d671a6b09bb2178 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7865 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-01-06target/mips32: add mips ejtag commandWalter Ji1-0/+70
Add mips32 ejtag_reg command for inspecting ejtag status. Add description for mips32 ejtag_reg command. Change-Id: Icd173d3397d568b0c004a8cc3f45518d7b48ce43 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7906 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-01-06target/mips32: update coprocessor 0 commandWalter Ji1-38/+273
Update mips32 cp0 command, it accepts cp0 reg names now. Updated mips32 cp0 description. Change-Id: Ib23dd13519def77a657c9c5bb039276746207b9b Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7905 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins
2024-01-06target/mips32: add cpu info detectionWalter Ji1-13/+320
Add detection for mips cpu types by using prid. Add cpuinfo command for inspecting more verbose info. Add MIPS Architecture specs in openocd docs. Change-Id: I28573b7c51783628db986bad0e226dcc399b4fa6 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7912 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2023-11-11target/mips32: update mips32 config register parsingWalter Ji1-7/+103
Enhance `mips32_read_config_regs` to better detect MIPS32 ISA, DSP, and FPU features, allowing user to get more detailed target information. Most of these information will be used in MIPS m/iAptiv support. Change-Id: I23571a626ec64fa019acac91bdbfcb434373bfc1 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7911 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2023-10-25target/mips32: check read regs result in save contextWalter Ji1-1/+5
Add result check for mips32_pracc_read_regs in mips32_save_context. Change-Id: Ie796d2b05a9feb11e246c2d0771b52cad4fb70db Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7932 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-10-25target/mips32: rework mips core register related functionsWalter Ji1-114/+164
Update mips core definitions. Reworked mips core register structure and read/write function. Add coprocessor0 register definitions for target configuration. Change-Id: I59c1f4cc4020db8a78e8d79f7421b87382fa1709 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7864 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-08-26mips32: add per-cpu quirks featureArtur Rojek1-0/+58
Introduce the ability to detect CPUs based on CP0 PRId register and apply cpu specific quirks, which alter the default ejtag behavior. First of those is EJTAG_QUIRK_PAD_DRET, which makes sure extra NOPs are placed after the DRET instruction on exit from debug mode. This fixes resume behavior on Ingenic JZ4780 SoC. The proper detection of some (currently unsupported) CPUs becomes quite complicated, so please consult the following Linux kernel code when adding new CPUs: * arch/mips/include/asm/cpu.h * arch/mips/kernel/cpu-probe.c Change-Id: I0f413d5096cd43ef346b02cea85024985b7face6 Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: https://review.openocd.org/c/openocd/+/7859 Tested-by: jenkins
2023-07-29target: fix messages and return values of failed op because not haltedTomas Vanek1-3/+3
Lot of messages was logged as LOG_WARNING, but the operation failed immediately. Sometimes no error message was logged at all. Add missing messages, change warnings to errors. Sometimes ERROR_TARGET_INVALID was returned. Some command handlers returned ERROR_OK! Always return ERROR_TARGET_NOT_HALTED. While on it use LOG_TARGET_ERROR() whenever possible. Prefix command_print() message with 'Error:' to get closer to LOG_TARGET_ERROR() variant. Error message was not added to get() and set() methods of struct xxx_reg_type - the return value is properly checked and a message is logged by the caller in case of ERROR_TARGET_NOT_HALTED. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I2fe4187c6025f0038956ab387edbf3f461c69398 Reviewed-on: https://review.openocd.org/c/openocd/+/7819 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27target: use unsigned int for timeout_msAntonio Borneo1-3/+3
Change the prototype of functions: - target_run_algorithm() - target_wait_algorithm() - target_wait_state() - struct target_type::run_algorithm() - struct target_type::wait_algorithm() to use unsigned int for timeout_ms instead of int. Change accordingly the variables passed as parameter. Change-Id: I0b8d6e691bb3c749eeb2911dc5a86c38cc0cb65d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7562 Tested-by: jenkins
2022-09-18openocd: fix SPDX tag format for files .cAntonio Borneo1-1/+1
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2021-06-18Use boolean argument for register_get_by_name()Marc Schink1-2/+2
Change-Id: Ie913630c6ab3b600532d8e375e2fc11ca202cf5e Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6295 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-09-05target: use proper format with uint32_tAntonio Borneo1-5/+5
Modify the format strings to properly handle uint32_t data types. While there, fix prototype mismatch between header and C file of the function armv7a_l1_d_cache_inval_virt(). Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5818 Tested-by: jenkins
2020-07-26target: fix minor typos and duplicated wordsAntonio Borneo1-1/+1
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-07-08coding style: fix space separationAntonio Borneo1-1/+1
The checkpatch script from Linux kernel v5.1 complains about using space before comma, before semicolon and between function name and open parenthesis. Fix them! Issue identified using the command find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types SPACING -f {} \; The patch only changes amount and position of whitespace, thus the following commands show empty diff git diff -w git log -w -p git log -w --stat Change-Id: I1062051d7f97d59922847f5061c6d6811742d30e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5627 Tested-by: jenkins
2019-05-14helper/command: change prototype of command_print/command_print_samelineAntonio Borneo1-9/+9
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should switch to CMD as first parameter. Change prototype of command_print() and command_print_sameline() to pass CMD instead of CMD_CTX. Since the first parameter is currently not used, the change can be done though scripts without manual coding. This patch is created using the command: sed -i PATTERN $(find src/ doc/ -type f) with all the following patters: 's/\(command_print(cmd\)->ctx,/\1,/' 's/\(command_print(CMD\)_CTX,/\1,/' 's/\(command_print(struct command_\)context \*context,/\1invocation *cmd,/' 's/\(command_print_sameline(cmd\)->ctx,/\1,/' 's/\(command_print_sameline(CMD\)_CTX,/\1,/' 's/\(command_print_sameline(struct command_\)context \*context,/\1invocation *cmd,/' This change is inspired by http://openocd.zylin.com/1815 from Paul Fertser but is now done through scripting. Change-Id: I3386d8f96cdc477e7a2308dd18269de3bed04385 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/5081 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-05-14target/mips32: change prototype of mips32_verify_pointer()Paul Fertser1-3/+3
To prepare for handling TCL return values consistently, all calls to command_print/command_print_sameline should be ready to switch to CMD as first parameter. Change prototype of mips32_verify_pointer() to pass CMD instead of CMD_CTX. This change was part of http://openocd.zylin.com/1815 from Paul Fertser and has been extracted and rebased to simplify the review. Change-Id: Ic4a4de10518ee009d6df420e7278fd028e1f22ca Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5062 Tested-by: jenkins
2019-03-14target/mips: Use 'bool' data typeMarc Schink1-11/+11
Change-Id: Ifb114bfc062ed7c0ff6e4f37a1a6d546f5415344 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4970 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-02-07target start_algorithm: Don't copy the IN mem_params fix uninitialised value.Jean-Christian de Rivaz1-0/+2
Fix the write only out params TODO on armv7m.c Fix conditional move depends on uninitialised value. It was detected while programming a LPC8Nxx with a FTDI adapter. valgrind --leak-check=full --show-leak-kinds=all --track-origins=yes [...] ==8696== Conditional jump or move depends on uninitialised value(s) ==8696== at 0x16E4D3: buf_set_u32 (binarybuffer.h:52) ==8696== by 0x16E4D3: ftdi_swd_queue_cmd (ftdi.c:1206) ==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271) ==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382) ==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420) ==8696== by 0x197CD9: target_write_buffer_default (target.c:2176) ==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383) ==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330) ==8696== by 0x19D846: target_run_algorithm (target.c:814) ==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== Uninitialised value was created by a heap allocation ==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299) ==8696== by 0x220EF9: init_mem_param (algorithm.c:30) ==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457) ==8696== by 0x1B7D99: run_command (command.c:623) ==8696== by 0x1B7D99: script_command_run (command.c:208) ==8696== by 0x1B7FD9: command_unknown (command.c:1033) ==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364) ==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814) ==8696== ==8696== Conditional jump or move depends on uninitialised value(s) ==8696== at 0x16E506: buf_set_u32 (binarybuffer.h:52) ==8696== by 0x16E506: ftdi_swd_queue_cmd (ftdi.c:1207) ==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271) ==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382) ==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420) ==8696== by 0x197CD9: target_write_buffer_default (target.c:2176) ==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383) ==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330) ==8696== by 0x19D846: target_run_algorithm (target.c:814) ==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== Uninitialised value was created by a heap allocation ==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299) ==8696== by 0x220EF9: init_mem_param (algorithm.c:30) ==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457) ==8696== by 0x1B7D99: run_command (command.c:623) ==8696== by 0x1B7D99: script_command_run (command.c:208) ==8696== by 0x1B7FD9: command_unknown (command.c:1033) ==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364) ==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814) Change-Id: I50f9a8c4516b686cf62ac3c76f47c53465e949da Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4811 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07target algo: do not write reg_param if direction is PARAM_INTomas Vanek1-0/+3
Without this change xxx_start_algorithm() writes all register parameters no matter of their direction. It usually results in writing of uninitialized reg_params[].value - possibly reported by valgrind. While on it fix the wrong parameter direction in kinetis_disable_wdog_algo(). This bug did not have any impact because of unconditional write of reg_params. Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4813 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10target, flash: prepare infrastructure for multi-block blank checkTomas Vanek1-6/+11
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2017-05-08mips32: add micromips isa handlingSalvador Arroyo1-14/+53
Read and save configuration registers, up to 4. Config3 holds the micromips implementation info. Added isa implementation info to mips32_common. Added isa filter to avoid common mistakes, but only if one isa mode is implemented. When resuming the isa requested is set if more than one isa mode is implemented. Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4123 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, convert miniprograms with code definitionSalvador Arroyo1-44/+63
Needed to run in micromips mode. Seems that if an isa is supported in debug mode it also supported in kernel mode. The contrary is not true. Change-Id: I1feb8e2c376f4db97089f05c20bc0cd177208fb3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4033 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add support for micromips in debug modeSalvador Arroyo1-2/+4
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-02-10target: Add 64-bit target address supportDongxue Zhang1-6/+6
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-10-30flash/nor: Add erased_value to drivers and pass it to targetsAndreas Färber1-3/+9
struct flash_driver has a default_padded_value field that is similar, but it can be changed by the user for the specific purpose of padding. Add a new erased_value field and initialize it for all targets, particularly stm32lx, xmc4xxx and virtual. Use this value in core.c:default_flash_mem_blank_check(), the slow path. Extend the target API to pass erased_value down to target code. Adding an argument ensures that we catch all callers. This allows us to merge xmc4xxx.c:xmc4xxx_blank_check_memory() into armv7m:armv7m_blank_check_memory(). It further allows us to use default_flash_blank_check() in place of xmc4xxx.c:xmc4xxx_flash_blank_check(), adding a potential slow path fallback, as well as stm32lx:stm32lx_erase_check(), adding the potential armv7m fast path with fallback to default_flash_mem_blank_check(). Fix a mips32 code comment while at it (zeroed -> erased). The armv4_5 and mips32 target implementations will now error out if an erase value other than 0xff is used, causing default_flash_blank_check() to fall back to the default_flank_mem_blank_check() slow path. Change-Id: I39323fbbc4b71c256cd567e439896d0245d4745f Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3497 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-10-04mips: Added #define for scan_delay legacy mode default valueKent Brinkley1-2/+2
Believe in using defines to make maintenance easier. Change-Id: I8edf151352131bbf2b884dfcd67ca5764b11b13c Signed-off-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-on: http://openocd.zylin.com/2350 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-02-13Change isa stringKent Brinkley1-1/+1
Laying the ground work for adding microAptiv core Change-Id: I161a8a8cb250240ebc8518c91e746d6f921c41c7 Signed-off-by: Kent Brinkley <jkbrinkley.imgtec@gmail.com> Reviewed-on: http://openocd.zylin.com/2400 Tested-by: jenkins Reviewed-by: Mindy Beseler <mbeseler@yahoo.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-02-11mips32: add gdb target description supportAntony Pavlov1-77/+166
This commit is inspired by commit 1255b18fc650193094666ba8afd2018089cc9794 Author: Spencer Oliver <spen@spen-soft.co.uk> Date: Fri Sep 13 09:44:36 2013 +0100 armv7m: add gdb target description support Change-Id: I75c3971fd0599d34ed49fb73975378b57f2a4af0 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> CC: Spencer Oliver <spen@spen-soft.co.uk> CC: Oleksij Rempel <linux@rempel-privat.de> CC: Paul Fertser <fercerpav@gmail.com> CC: Gregory Fong <gregory.0xf0@gmail.com> Reviewed-on: http://openocd.zylin.com/1972 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-02-11mips32: use 'unsigned int' for CPU register indicesAntony Pavlov1-14/+13
Change-Id: I77e94b2fe0943a87e1d18d88ebf2a0133aaad728 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2216 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-11-24mips32: fix typosAntony Pavlov1-1/+1
Change-Id: Ibb98fe3da68bf670a5bb83600bb49647db8a4163 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2338 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-08-19mips32.c: cache debug caps and support EJTAG 2.0 specific changesOleksij Rempel1-10/+15
EJTAG v2.0 indicated some debug caps in IMP register. V2.6 moved them to DCR register. To make it more universal, convert this values and store them for later use. Change-Id: Id6b9f47c9c2ea94d37281ebfcae5acf357261ddf Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1932 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-08-19mips32.c: fix IB and DB bits check for EJTAG v2.0Oleksij Rempel1-4/+9
Change-Id: I4e28dddc1d5d9c2b923ae17beacdd7f73591b1d0 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1931 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-05-09mips: load code in buffer modeSalvador Arroyo1-34/+23
Currently the functions mips32_checksum_memory() and mips32_blank_check_memory() load the code word by word. The bug in cache code is a good reason for doing so. If there is no other reason we can load the code as a buffer to save time. mips_m4k_write_memory() expect a buffer in target endianness, this is done by target_buffer_set_u32_array(). Cleaned up exit code. Tested on ar7241 big endian and pic32mx little endian with verify_image. Flash erase check only tested in pic32mx. Change-Id: Ib63ed98732b2e23b058e7349a0a57934b7604905 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1562 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-04-14mips32, dsp563xx: fix segfault on Gdb attachPaul Fertser1-1/+1
Since c6216201b249e6a97fcc085e413e3d34e0de6fb7 gdb target description generation support is enabled by default and it counts on checking "feature" pointer in reg_list. Both mips32 and dsp563xx neither used calloc nor explicitly set feature (as it was a newly introduced struct field). This patch changes all targets to use calloc for consistency. Change-Id: I9eceadef8b04aacb108e24ae23cb51ca3009586f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2102 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-02-24mips32: build register cache in a more clear wayAntony Pavlov1-50/+46
This commit is inspired by armv7m_build_reg_cache(). Change-Id: I62b51b2a5f0fed788af167b6f8e60c09b53181be Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/1943 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31Clean up many C99 integer types format specifiersPaul Fertser1-1/+1
This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-08-07gdb_server: support gdb target descriptionHsiangkai Wang1-1/+2
* Add a parameter in .get_gdb_reg_list() to return different register lists as generating target description. * Modify STRUCT REG to let gdb generate target description according to register information. The modified structure of register is struct reg { const char *name; uint32_t number; /* for regnum="num" */ struct reg_feature *feature; /* for register group feature name */ bool caller_save; /* for save-restore="yes|no" */ void *value; bool dirty; bool valid; bool exist; uint32_t size; struct reg_data_type *reg_data_type; /* for type="type" */ const char *group; /* for group="general|float|vector" */ void *arch_info; const struct reg_arch_type *type; }; Change-Id: I2096b67adf94518ba0b8b23d8c6a9f64ad7932b8 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1382 Tested-by: jenkins Reviewed-by: Franck Jullien <franck.jullien@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-07-17mips: add breakpoint support for EJTAG 2.0Oleksij Rempel1-6/+16
EJTAG 1.5, 2.0 and 2.5 have different breakpoint register addresses. This patch add support of EJTAG 2.0, which is part some broadcom SoCs. This work was testet on Broadcom BCM7401. Change-Id: I4b0ee23871fa9205f9001b7c9165e7b6ebe9ccbf Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1464 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-07-17mips32: add new functions mips32_configure_ibs and _dbsOleksij Rempel1-28/+53
Split function mips32_configure_break_unit to mips32_configure_ibs and mips32_configure_dbs to make code more readable. This will probably make work easyer with differnet EJTAG versions. Change-Id: I666f949fd7bc3656bdf75e7bcaadb164f15855dd Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/1463 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-04-20mips: m4k alternate pracc code. Patch 1Salvador Arroyo1-0/+33
This patch and the following patches define another way of doing processor access without the need to read back the pracc address as needed in current pracc code. Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200 and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start. Most of the processor accesses are fetch and some are store accesses. After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses. The pracc address for a store depends only on the store instruction given before. m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline. For reference: MD00249 mips32 m4k manual. A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by current code or by the new one to generate the sequence of pracc accesses. For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96(). This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution. The pracc bit is not checked before execution, is checked after the queue has been executed. Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay between scans is added by calling jtag_add_cloks(). A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it. A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set, current code is executed, if lower, new code is executed. Initial default values are set in function mips32_init_arch_info. A reset does not change this settings. Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1193 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-04-02mips: code cleanup in cp0 command handlersSalvador Arroyo1-4/+1
After calling mips32_cp0_read() nothing has been queued, the call to jtag_exec_queue() is unnecessary. Change-Id: Ie25438045a8e9b6b1b170df7b52609d45f284b5a Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1190 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-04-10Minor bug fixes in Mips32 codeSalvador1-3/+3
Now the the "Fast" version for memory blank check in pic32mx.c can be called: default_flash_blank_check() instead of the "fallback" default_flash_mem_blank_check(). The command "verify_image", without working area, now don't show: checksum mismatch - attempting binary compare when there are no real errors in flash. Change-Id: I256e8ae949289634e1de5c1c2861e4c4c4b7fdce Signed-off-by: Salvador <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/549 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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