riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2013-06-05	update files to correct FSF address	Spencer Oliver	1	-1/+1
2013-05-29	cortex_m, hla_target: do not try asserting SRST if it's not present	Paul Fertser	1	-1/+2
2013-03-15	target: Add default implementation of bulk_write_memory	Andreas Fritiofson	1	-8/+0
2013-02-25	target: hla correctly use target events	Spencer Oliver	1	-5/+16
2013-02-02	armv7m: use generic arm read/write_core_reg	Spencer Oliver	1	-2/+4
2013-02-02	armv7m: use generic register core_cache	Spencer Oliver	1	-7/+7
2013-02-02	armv7m: remove unused armv7m_regtype	Spencer Oliver	1	-2/+0
2013-02-02	armv7m: use generic arm::core_mode	Spencer Oliver	1	-5/+3
2013-01-27	hla: enable DWT component and fix watchpoints	Spencer Oliver	1	-4/+4
2013-01-02	hla: support setting DCB_DEMCR on resume	Spencer Oliver	1	-0/+5
2012-12-23	hla: add ability to configure read/write buffer size	Spencer Oliver	1	-6/+6
2012-12-23	hla: fix watchpoints not being set	Spencer Oliver	1	-0/+6
2012-12-23	stlink: rename stlink cmd names	Spencer Oliver	1	-2/+3
2012-12-23	target: add deprecated target name support	Spencer Oliver	1	-0/+809