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path: root/src/target/armv8_dpm.c
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2020-09-05target: use proper format with uint32_tAntonio Borneo1-3/+3
Modify the format strings to properly handle uint32_t data types. While there, fix prototype mismatch between header and C file of the function armv7a_l1_d_cache_inval_virt(). Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5818 Tested-by: jenkins
2020-07-26target: fix minor typos and duplicated wordsAntonio Borneo1-1/+1
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5766 Tested-by: jenkins
2020-05-09coding style: add parenthesis around the argument of sizeofAntonio Borneo1-2/+2
The script checkpatch available in new Linux kernel offers an experimental feature for automatically fix the code in place. While still experimental, the feature works quite well for simple fixes, like parenthesis. This patch has been created automatically with the script under review for inclusion in OpenOCD, using the command: find src/ -type f -exec ./tools/scripts/checkpatch.pl \ -q --types SIZEOF_PARENTHESIS --fix-inplace -f {} \; Change-Id: I8adb325bdb0e13211f8bae8b4770ec1979c176bf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5618 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2020-04-05armv8: log the register name which we failed to read or writeTarek BOCHKATI1-0/+7
when openocd fails to read armv8 register, the user is not informed which register has caused the error. for example, in AArch32 state ESR_EL3 read/write is not supported, thus armv8_dpm_read_current_registers is always failing without mentioning which register has caused the error. Change-Id: I24c5abbda9fac24fb77a01777ed15261aeaaf800 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5516 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-04armv8: allow halt on exceptionMatthias Welwarsky1-1/+3
add command 'catch_exc' to halt a core on entering any of Secure EL1 or EL3 or Non-Secure EL1 or EL2. Change-Id: I0c68e247af68dd96616855a9bc1063c277d222e5 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4479 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-30aarch64: support for aarch32 ARM_MODE_SYSMatthias Welwarsky1-0/+5
Treat ARM_MODE_SYS like all other Aarch32 processor modes, except for the special case of missing SPSR. Change-Id: I60b21703659b264f552884cdc0f85fd45f7836de Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4494 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2018-03-16aarch64: fix debug entry from EL0Matthias Welwarsky1-4/+5
If we enter debug state from EL0, some registers are not accessible. Temporarily move to EL1H and back to gain access. Also, fix armv8_dpm_modeswitch() to not immediately restore the previous state on elevating the privilege level. Change-Id: Ic2a92109230ff4eb6834c00ef544397a5b7ad56a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4461 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-10Support AArch64 SIMD/FP registers read/writeOmair Javaid1-22/+58
This patch adds support in openOCD to read/write AArch64 SIMD/FP registers. This patch depends on a previous patch which adds support to generation of target xml by openOCD with nested architecture defined types. AArch64 SIMD/FP registers assumes various types and to support all types we implement them as architecture defined type aarch64v which in turn consists of various architecture defined types. This is compatible with AArch64-FPU target xml in GDB. Please refer to binutils-gdb/gdb/features/aarch64-fpu.xml Change-Id: I7ffb0c21b3c2e08f13720b765408b30aab2a9808 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4373 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-01-16aarch64: simplify mode and state handlingMatthias Welwarsky1-6/+1
Aarch32 and Aarch64 modes don't conflict in CPSR, no need to deconflict ARMv7-M profile modes either. Change-Id: I4c437dfa657f9e8a1da3687bc9f21435384b7881 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4144 Tested-by: jenkins Reviewed-by: Yao Qi <qiyaoltc@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2017-02-24armv8_dpm: fix exception handlingMatthias Welwarsky1-0/+2
after handling of an exception in debug state, immediately restore the original core state. Change-Id: Ie53b63c9f19815f717f4df4390fbc13f0a204cc2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3996 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24armv8_dpm: retrieve only necessary registers on haltMatthias Welwarsky1-3/+11
to speed up debugging, don't load the complete register context on a halt event, load only those registers that might be clobbered during debugging. Change-Id: I0b58e97aad6f28aefce4a52e870af61e1ef1a44f Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3995 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: optimize core state detectionMatthias Welwarsky1-8/+2
Replace loop by right-shift. Inspired by patch from Alamy Liu Change-Id: I1285f4f54c0695a93fa42e9863ed8ffa4de00f70 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3985 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: reduce debug output to improve legibilityMatthias Welwarsky1-6/+0
Suppress some very verbose LOG_DEBUG's that are not really useful any more. Change-Id: I67f10ba9510a9e34a027f378f4b62b8901ddc8a4 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3984 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: remove mrs/msr functions from struct armMatthias Welwarsky1-58/+0
No longer needed, no users. Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3983 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-24aarch64: fix software breakpoints when in aarch32 stateMatthias Welwarsky1-0/+11
Use the correct opcode for Aarch32 state, both for the breakpoint instruction itself and the cache handling functions. Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3981 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10aarch64: use cached value of dscr register where neededMatthias Welwarsky1-25/+21
Instead of supplying a local, preinitialized "dscr" variable, use the cached value from arm_dpm, which is kept up-to-date anyway. Change-Id: I06d548d4dc6db68b9d984c83ed026fa9069d7875 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: improve debug outputMatthias Welwarsky1-4/+3
Make debug and error messages more informative, fix spelling and formatting errors Change-Id: I7245f42c5153bcc95676270814d30e91c113aaed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: consolidate sticky error handlingMatthias Welwarsky1-9/+4
Move clearing of DSCR "Sticky Error" condition to the exception handling function. Clear once on entering debug state. Change-Id: Iec1d09d6f2d9cdd7e92953da5ea19f3e399ca12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: discard async aborts on entering debug stateMatthias Welwarsky1-1/+6
recommended for Corte-A8 cores, not sure if necessary for ARMv8 based cores as well. Change-Id: Ibcb36170c5fac6a6b132de17f734c70a56919f9b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: handle exceptions taken in debug stateMatthias Welwarsky1-0/+57
When an armv8-a PE causes an exception while halted, e.g. by performing a prohibited memory or register access, its state is affected in the same way as if it was running. That means, a number of registers is overwritten (notably DLR and DSPSR, but also others) and also potentially the exception level and therefore also the PE state can change. This state must be restored before resuming normal operation. This is done by marking the relevant cached registers "dirty" so that they are written back before resume. Change-Id: I9b6967a62d7cb23a477a9f7839f8d2b7087eed09 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix mode switchingMatthias Welwarsky1-39/+89
DCPS only allows to enter higher ELs, for lower ELs you need to use DRPS. Also, of course the encoding differs between A64 and T32. Both DCPS and DRPS also clobber DLR and DSPSR, which then need to be restored on resume. Change-Id: Ifa3dcfa94212702e57170bd59fd0bb25495fb6fd Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: register access rewriteMatthias Welwarsky1-251/+122
All register access is now performed through common read/write functions, which delegate the actual register access to the armv8_common object. armv8_common contains function pointers to direct read and write requests to the respective low-level functions for each PE state. The respective read/write functions are selected on debug state entry. At the same time, T32 opcodes are now formatted for ITR in dpmv8_exec_opcode() and the T32_FMTITR macro is removed from global visibility. Change-Id: I9eaef017c7cc9e0c531e693c534901bfdbdb842c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: refactor armv8 dpmMatthias Welwarsky1-0/+427
Move all DPM related functions from aarch64.c to armv8_dpm.c. Change-Id: I43404ff5db414ae898787a523d3219e5bee44889 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: add basic Aarch32 supportMatthias Welwarsky1-20/+151
Add database for common, equivalent opcodes for Aarch32 and Aarch64 execution states Revisit all functions that access Aarch64 specific registers or use Aarch64 opcodes and rewrite them to act depending on current state of the core. Add core register access functions for Aarch32 state Add function to determine the core execution state without reading DSPSR. Change-Id: I345e9f6d682fb4ba454e4b1d16bb5e1b27570691 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: use correct instruction for software breakpointsMatthias Welwarsky1-2/+2
External debuggers need to use HLT, not BRK. HLT generates a halting debug event while BRK generates a debug exception for self-hosted debugging. Change-Id: I24024b83668107f73a14cc75d951134917269e5c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: report the correct reason for halting after singlestepMatthias Welwarsky1-1/+4
Don't report breakpoint as debug reason when halt is due to a single-step event. Change-Id: Ie6c3ca1e5427c73eb726a038301b6a29a47d1217 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: fix duplication of register cacheMatthias Welwarsky1-3/+5
Change-Id: Ib4422e39171f19eea3f0b5a86f9dccdbb7044265 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10aarch64: introduce dpm extension for ARMv8Matthias Welwarsky1-0/+985
Add or move ARMv8 related dpm function to their own source module Change-Id: Id93d50be0b8635bd40ddb2a74fe8746ff840d736 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
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