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2023-05-27target: use unsigned int for timeout_msAntonio Borneo1-4/+4
Change the prototype of functions: - target_run_algorithm() - target_wait_algorithm() - target_wait_state() - struct target_type::run_algorithm() - struct target_type::wait_algorithm() to use unsigned int for timeout_ms instead of int. Change accordingly the variables passed as parameter. Change-Id: I0b8d6e691bb3c749eeb2911dc5a86c38cc0cb65d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7562 Tested-by: jenkins
2023-01-15target/armv7m: Rename xPSR to xpsrBoris-Chengbiao Zhou1-1/+1
The org.gnu.gdb.arm.m-system GDB feature defines the name in lowercase letters.[1] Not adhering to the definition can cause issues with tools interacting with the GDB which expect the correct casing. [1]: https://sourceware.org/gdb/onlinedocs/gdb/ARM-Features.html Change-Id: I0b6584a78f86b053947d79686baad5dac3ec4a00 Signed-off-by: Boris-Chengbiao Zhou <bobo1239@web.de> Reviewed-on: https://review.openocd.org/c/openocd/+/7292 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15target/armv7m: check error in armv7m_restore_context()Tomas Vanek1-2/+5
Return error if arm.write_core_reg() fails. Change-Id: Ide8f5aa5958532b202dc9f5e13d3250a706d832d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7238 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15target/armv7m: fix feature name of ARMv8M security extension regsTomas Vanek1-17/+17
gdb requires this feature to enable stack unwinding of secure/nonsecure interstate calls and exceptions on an ARMv8M target with the security extension. Tested on STM32L5 (Cortex-M33). Change-Id: Ib09780c011afbc095b352074068597559ad14fcd Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ae7e2f45aa4798be449f282bbf75ad41e73f055e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7265 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15target/armv7m: prevent saving and restoring non existent regsTomas Vanek1-6/+12
armv7m_start_algorithm() saves register values to arch_info->context. armv7m_wait_algorithm() restores register values from arch_info->context. Exclude registers with flag exist = false from both loops. While on it refactor the register restore: introduce 'struct reg' pointer and dereference it instead of numerous accesses by a full path from armv7m pointer. Change-Id: I1600084db84809ee13bcf8e7828b79f8c9ff9077 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7276 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08target/armv7m: show target name in 'halted' messageTomas Vanek1-1/+2
Change-Id: I13e9a33677632d52122585203252fc4ef0c52a2a Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7237 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-08target/armv7m: prevent storing invalid registerTomas Vanek1-4/+7
armv7m_start_algorithm() stored all non-debug execution registers from register cache without checking validity. Check if the register cache is valid. Try to read from CPU if not valid. Issue a warning if register read fails. Change-Id: I365f86d65243230cf521b13909575e5986a87a50 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7240 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-09-18openocd: fix SPDX tag format for files .cAntonio Borneo1-1/+1
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
2022-09-13openocd: remove CamelCase symbols *xPSR*Antonio Borneo1-6/+6
We have left the camelcase symbols *xPSR* for some time, to avoid any conflict with possibly pending patches in gerrit. With the approaching v0.12.0-rc1, it's time to revisit it. The patches in gerrit that conflict with this rename are all not merge-able due to conflicts or due to negative review. Drop these CamelCase symbols. Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7155 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-08-14target/arm: do not expose 'arm reg', 'arm mcr/mrc' commands on Cortex-MTomas Vanek1-1/+5
Tcl commands 'arm reg', 'arm mcr/mrc' do not work on M-profile based devices. Isolate them from 'arm core_state' and 'arm disassemble' and do not chain them from armv7m_command_handlers. Change-Id: I2c6befdf82575e95cf05ed158ab5e6faa1a182c3 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7101 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2022-08-14target/arm: make 'arm core_state' command compatible with Cortex-MTomas Vanek1-0/+1
Tcl command 'arm core_state' was exposed even on Cortex-M devices. However it returned message "Unsupported Command" without error status on such device. Set the only possible arm->core_state ARM_STATE_THUMB in armv7m init. Block setting core_state to arm on Cortex-M. Change-Id: I9525553ac8863a6cf77bbacbcd57e354b6cfe1ca Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7100 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
2021-11-18target/cortex_m: faster reading of all CPU registersTomas Vanek1-2/+2
Without the change cortex_m_debug_entry() reads all registers calling cortex_m_load_core_reg_u32() for each register with a poor usage of JTAG/SWD queue. It is time consuming, especially on an USB FS based adapter. Moreover if target_request debugmsgs are enabled, DCB_DCRDR is saved and restored on each register read. This change introduces cortex_m_fast_read_all_regs() which queues all register reads and a single dap_run() transaction does all work. cortex_m_fast_read_all_regs() reads all registers unconditionally regardless register cache is valid or not. This is a difference from the original cortex_m_debug_entry() code. cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP (Kinetis K28F-FRDM kit) target_request | time [ms] debugmsgs | without the change | with the change ---------------+--------------------+----------------- disable | 186 | 27 enable | 232 | 29 Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen, cortex_m->slow_register_read is set and fallback to the old register read method cortex_m_slow_read_all_regs() is used instead of cortex_m_fast_read_all_regs(). Change-Id: I0665d94b97ede217394640871dc451ec93410254 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/5321 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-25armv7m.h: relax dependency from 'arm_adi_v5.h'Antonio Borneo1-0/+2
The include file 'armv7m.h' includes 'arm_adi_v5.h' only to get the definition of 'struct adiv5_ap', but doesn't need the struct content. Reducing the cross dependencies speeds-up the compile time during code development by avoiding re-compiling file. Relax the dependency by locally declaring 'struct adiv5_ap' in 'armv7m.h' and remove the include of 'arm_adi_v5.h'. Fix the other files that have now lost the includes file that 'arm_adi_v5.h' depends from. Change-Id: Ic0d40b17db6045fa43f348bda83eaf211a6b347d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6468 Tested-by: jenkins Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-07-24openocd: remove NULL comparisons with checkpatch [1/2]Antonio Borneo1-1/+1
Patch generated automatically through the new checkpatch with flags "--types COMPARISON_TO_NULL --fix-inplace". This only fixes the comparisons if (symbol == NULL) if (symbol != NULL) The case of NULL on the left side of the comparison is not tested. Some automatic fix is incorrect and has been massaged by hands: - if (*psig == NULL) + if (*!psig) changed as + if (!*psig) Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6351 Tested-by: jenkins
2021-07-24openocd: fix simple cases of NULL comparisonAntonio Borneo1-1/+1
There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-06-18Use boolean argument for register_get_by_name()Marc Schink1-2/+2
Change-Id: Ie913630c6ab3b600532d8e375e2fc11ca202cf5e Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6295 Tested-by: jenkins Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-05-18target/armv7m: fix static analyzer warningTomas Vanek1-4/+16
Despite of assert(is_packed) clang static analyser complains on use of the uninitialized offset variable. Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings src/target/armv7m.c: In function ‘armv7m_read_core_reg’: src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used uninitialized in this function [-Werror=maybe-uninitialized] It happens because mingw32 defines assert() without the attribute "noreturn", whatever NDEBUG is defined or not. Replace assert(is_packed) by if (is_packed) conditional and call assert(false) in the else branch. Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/6256 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
2021-05-11cortex_m: add armv8m special registersTarek BOCHKATI1-13/+44
Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6016 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-03-10cortex_m: avoid reading and writing non-existent registersTarek BOCHKATI1-4/+4
Change-Id: Iedc24352c8d3444372da06d00fcec9603540f950 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6059 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15target/armv7m, cortex_m: fix misleading commentsTomas Vanek1-2/+1
Change-Id: I4fea29f07f4d3b8b2578b538ef0eef5f1eea285f Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5876 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15target/armv7m: use arch_info[i].value instead of allocated memoryTomas Vanek1-5/+1
Change-Id: I9422cab484d0769404516947e16da1baa001a4e0 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5328 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15target/armv7m: rework Cortex-M register handling part 3Tomas Vanek1-46/+136
Move primask/basepri/faultmask/control packing/unpacking from cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg() and armv7m_write_core_reg() where also the FP 32/64-bit registers conversion takes place. Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL for packing/unpacking of special registers in the register cache. The new packing/unpacking is endianess safe. While on it improve returned error codes and LOG_ messages. Just minimal changes in cortex_m.c and hla_target.c, will be consolidated in the next patch. Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5863 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-11-15target/armv7m: rework Cortex-M register handling part 2Tomas Vanek1-0/+2
Make arm register id coherent with reg_list index. Without this reg_list[ARMV7M_R12] was possible but reg_list[ARMV7M_FPSCR] was out of bounds. Remove unused items from reg_list index. Change-Id: I84d3b5c496fc1839d07a5b74cb1fd1c3d4ff8989 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5862 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2020-11-15target/armv7m: rework Cortex-M register handling part 1Tomas Vanek1-9/+44
Define a new enum with DCRSR.REGSEL selectors. Introduce armv7m_map_id_to_regsel() to unify mapping in one place. Use DCRSR.REGSEL selectors for low level register read/write. Change-Id: Ida0ccdfa9cdb1257a1900b8bfbf172b076374d39 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5327 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
2020-10-22cortex_m: support control.FPCASylvain Chouleur1-1/+1
Bit 2 of control register is used if the processor includes the FP extension Change-Id: Ie21bc9de8cae5bad9d841e1908eff3aa0bb29d4b Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai> Reviewed-on: http://openocd.zylin.com/5853 Reviewed-by: Sylvain Chouleur <sylvain.chouleur@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2020-09-20armv8-m: add SecureFault exceptionTarek BOCHKATI1-1/+1
Change-Id: I4e1963631e834b6334bc917e956c2db4464b7b08 Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5797 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-03target/armv7m: cosmetic refactorizationTomas Vanek1-5/+7
Introduce a variable 'size' and reduce the number of dereferencing *reg_list_size by using the variable. Change-Id: I3bdf1485a4ed8e34435e8acb3efd0df8d802508c Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5326 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-04-21target/armv7m: minor fixes of target algo exit point checkTomas Vanek1-7/+8
Introduce a new ERROR_TARGET_ALGO_EXIT as currently used ERROR_TARGET_TIMEOUT should be reserved for the timeout only. Do not load PC directly from CPU HW as the register value has already been cached. Change-Id: I0d3630da41fd021676789dc12b52545cc0432ba8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5329 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2020-03-12arm: Use different enum for core_type and core_modeAntonio Borneo1-1/+1
The fields core_type and core_mode use the same enum arm_mode but encode different information, making the code less immediate to read. Use a different enum arm_core_type for the field core_type. The code behavior is not changed. Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5258 Tested-by: jenkins
2019-06-10target/armv7m: fix register number in armv7m_get_core_reg()Tomas Vanek1-1/+1
armv7m_get_core_reg() calls arm->read_core_reg() arm->read_core_reg() expects the register number as an index to core reglist, not an ARMv7M specific register code. Use reg->number instead of armv7m_reg->num. The change solves assert src/target/armv7m.c:222: armv7m_read_core_reg: Assertion `num < (int)armv7m->arm.core_cache->num_regs' failed. when gdb 'info reg' is issued on a Cortex-M target and no cortex_m_debug_entry() has been called since OpenOCD start (target was halted before OpenOCD start). Change-Id: I32a2294693ef979b613be93aeceb3b0eb06ee6df Ticket: https://sourceforge.net/p/openocd/tickets/216/ Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5203 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-03-06target/armv7m: Use 'bool' data typeMarc Schink1-16/+16
Change-Id: I9cfbba9d81601cc72e2b54ec410e21c7edc4f1c4 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4955 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2019-02-07target start_algorithm: Don't copy the IN mem_params fix uninitialised value.Jean-Christian de Rivaz1-1/+2
Fix the write only out params TODO on armv7m.c Fix conditional move depends on uninitialised value. It was detected while programming a LPC8Nxx with a FTDI adapter. valgrind --leak-check=full --show-leak-kinds=all --track-origins=yes [...] ==8696== Conditional jump or move depends on uninitialised value(s) ==8696== at 0x16E4D3: buf_set_u32 (binarybuffer.h:52) ==8696== by 0x16E4D3: ftdi_swd_queue_cmd (ftdi.c:1206) ==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271) ==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382) ==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420) ==8696== by 0x197CD9: target_write_buffer_default (target.c:2176) ==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383) ==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330) ==8696== by 0x19D846: target_run_algorithm (target.c:814) ==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== Uninitialised value was created by a heap allocation ==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299) ==8696== by 0x220EF9: init_mem_param (algorithm.c:30) ==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457) ==8696== by 0x1B7D99: run_command (command.c:623) ==8696== by 0x1B7D99: script_command_run (command.c:208) ==8696== by 0x1B7FD9: command_unknown (command.c:1033) ==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364) ==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814) ==8696== ==8696== Conditional jump or move depends on uninitialised value(s) ==8696== at 0x16E506: buf_set_u32 (binarybuffer.h:52) ==8696== by 0x16E506: ftdi_swd_queue_cmd (ftdi.c:1207) ==8696== by 0x18D76D: swd_queue_ap_write (adi_v5_swd.c:271) ==8696== by 0x18E33B: dap_queue_ap_write (arm_adi_v5.h:382) ==8696== by 0x18E33B: mem_ap_write (arm_adi_v5.c:420) ==8696== by 0x197CD9: target_write_buffer_default (target.c:2176) ==8696== by 0x2464B3: armv7m_start_algorithm (armv7m.c:383) ==8696== by 0x246AEB: armv7m_run_algorithm (armv7m.c:330) ==8696== by 0x19D846: target_run_algorithm (target.c:814) ==8696== by 0x1DF3A6: lpc2000_iap_call.isra.3 (lpc2000.c:818) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== Uninitialised value was created by a heap allocation ==8696== at 0x4C2BBAF: malloc (vg_replace_malloc.c:299) ==8696== by 0x220EF9: init_mem_param (algorithm.c:30) ==8696== by 0x1DF247: lpc2000_iap_call.isra.3 (lpc2000.c:777) ==8696== by 0x1E0CF6: lpc2000_erase (lpc2000.c:992) ==8696== by 0x185BDF: flash_driver_erase (core.c:44) ==8696== by 0x18650D: flash_iterate_address_range_inner (core.c:541) ==8696== by 0x18650D: flash_iterate_address_range (core.c:567) ==8696== by 0x18732F: flash_erase_address_range (core.c:584) ==8696== by 0x18732F: flash_write_unlock (core.c:928) ==8696== by 0x18ACDF: handle_flash_write_image_command (tcl.c:457) ==8696== by 0x1B7D99: run_command (command.c:623) ==8696== by 0x1B7D99: script_command_run (command.c:208) ==8696== by 0x1B7FD9: command_unknown (command.c:1033) ==8696== by 0x2E2D37: JimInvokeCommand (jim.c:10364) ==8696== by 0x2E3865: Jim_EvalObj (jim.c:10814) Change-Id: I50f9a8c4516b686cf62ac3c76f47c53465e949da Signed-off-by: Jean-Christian de Rivaz <jcamdr70@gmail.com> Reviewed-on: http://openocd.zylin.com/4811 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2019-02-07target algo: do not write reg_param if direction is PARAM_INTomas Vanek1-0/+3
Without this change xxx_start_algorithm() writes all register parameters no matter of their direction. It usually results in writing of uninitialized reg_params[].value - possibly reported by valgrind. While on it fix the wrong parameter direction in kinetis_disable_wdog_algo(). This bug did not have any impact because of unconditional write of reg_params. Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4813 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2019-01-08armv7m: always set xPSR.T=1 when starting an algorithmCody P Schafer1-0/+17
xPSR.T sets the processor to Thumb mode when set to 1. ARMv7-M only supports execution of Thumb instructions, so it must always be set to 1. If xPSR.T is set to 0 on armv7m, a usage fault is generated when a instruction execution is attempted. On armv7m, issuing a reset causes the vector table to be examined. PC and xPSR.T are loaded from the vector table at byte offset 4. xPSR.T is taken from the least significant bit this value, PC from the remaining bits. This occurs even with `reset halt`, as the reset itself causes this load to occur without the execution of any instructions. As a result of this, following a reset with a "bad" value programmed in the vector table, openocd would be unable to run algorithms on the target, as running them would immediately result in a usage fault due to xPSR.T being unset (0). Allow algorithms to run regardless of the content of the vector table by explicitly setting xPSR so that xPSR.T=1 prior to executing an algorithm. One can think of this as openocd more closely emulating a reset or branch instruction in executing it's algorithms. Ticket: https://sourceforge.net/p/openocd/tickets/203/ Signed-off-by: Cody P Schafer <openocd@codyps.com> Change-Id: I4dc3427ab195d06c3fd780ea768027fefccc4c28 Reviewed-on: http://openocd.zylin.com/4658 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2018-07-18Avoid null target->semihosting references.Liviu Ionescu1-3/+3
The new common semihosting code introduced a bug, in certain conditions target->semihosting was used without semihosting being initialised. The solution was to explicitly test for target->semihosting before dereferencing it. Change-Id: I4c83e596140c68fe4ab32e586e51f7e981a40798 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4603 Tested-by: jenkins Reviewed-by: Jonathan Larmour <jifl@eCosCentric.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-06-04Rework/update ARM semihostingLiviu Ionescu1-3/+7
In 2016, ARM released the second edition of the semihosting specs ("Semihosting for AArch32 and AArch64"), adding support for 64-bits. To ease the reuse of the semihosting logic for other platforms (like RISC-V), the semihosting code was isolated from the ARM target and updated to the latest specs. The new code is already in use since January (in GNU MCU Eclipse OpenOCD) and no problems were reported, neither for ARM nor for RISC-V targets, after more than 7K downloads. The 2 new files were formatted with uncrustify. Change-Id: Ie84dbd86a547323bb8a5d24eab68fc7dad013d96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4518 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10target armv7m: multi-block erase checkTomas Vanek1-39/+95
Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode, adapter_khz=1000. Plain read: flash read_bank 0 /dev/null takes 48 seconds. erase_check without this change: flash erase_check 0 takes horrible 149 seconds!! And the same command with the change applied takes 1.8 seconds. Quite a difference. Remove the erase-value=0 version of algorithm as the new one can check for any value. If the target is an insane slow clocked CPU (under 1MHz) algo timeouts. Blocks checked so far are returned and the next call uses increased timeout. Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4298 Tested-by: jenkins Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-04-10target, flash: prepare infrastructure for multi-block blank checkTomas Vanek1-5/+8
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-03-30target: restructure dap supportMatthias Welwarsky1-3/+0
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2017-02-10target: Add 64-bit target address supportDongxue Zhang1-6/+6
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-12-08semihosting: support fileio operationSteven Stallion1-2/+7
This patch adds support for bridging semihosting to GDB's File-I/O remote protocol extension. For the most part operations match up 1:1, however some require a working area to complete successfully, namely operations that devolve to read, stat, and gettimeofday. A new command was added to enable support for fileio named `arm semihosting_fileio`, which ensures that the default behavior remains intact for those that prefer it. Finally, redundant logging was removed from the target_arch_state function; this permits ARM targets to quiesce log output when polling for a fileio reply. This prevents filling the logs with halt/resume messages when using semihosting fileio. Change-Id: Ifbb864fc2373336a501cc0332675b887b552e1ee Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/3566 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-10-30flash/nor: Add erased_value to drivers and pass it to targetsAndreas Färber1-6/+22
struct flash_driver has a default_padded_value field that is similar, but it can be changed by the user for the specific purpose of padding. Add a new erased_value field and initialize it for all targets, particularly stm32lx, xmc4xxx and virtual. Use this value in core.c:default_flash_mem_blank_check(), the slow path. Extend the target API to pass erased_value down to target code. Adding an argument ensures that we catch all callers. This allows us to merge xmc4xxx.c:xmc4xxx_blank_check_memory() into armv7m:armv7m_blank_check_memory(). It further allows us to use default_flash_blank_check() in place of xmc4xxx.c:xmc4xxx_flash_blank_check(), adding a potential slow path fallback, as well as stm32lx:stm32lx_erase_check(), adding the potential armv7m fast path with fallback to default_flash_mem_blank_check(). Fix a mips32 code comment while at it (zeroed -> erased). The armv4_5 and mips32 target implementations will now error out if an erase value other than 0xff is used, causing default_flash_blank_check() to fall back to the default_flank_mem_blank_check() slow path. Change-Id: I39323fbbc4b71c256cd567e439896d0245d4745f Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3497 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-22armv7m: Integrate build of checksum codeAndreas Färber1-33/+1
Add rules to build armv7m_crc.inc and include it via preprocessor. Change-Id: I4482c7acb8454de28bdf210d9f06c0720ada490a Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3474 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-14armv7m: Improve armv7m_blank_check_memory() error handlingAndreas Färber1-1/+2
Clean up the working area in case writing fails. Adapted from armv7m_checksum_memory(). Change-Id: I4e5950f568ed70a72a1dcfd77e3321110b17e1de Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3469 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-02-29armv7m: Integrate build of erase check codeAndreas Färber1-9/+1
Instead of documenting the file path as a comment and inline-commenting the THUMB bytecode, include the hex array via preprocessor. This assures the path is actually up-to-date and facilitates updating the code. Change-Id: Ieb0a7cd0bc14882ac96750f524616d9768a0c6f5 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3134 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-09-30armv7m: Fix memory leak in register caching.Marc Schink1-0/+28
Change-Id: I184042d277a52f3940d6d6c13f3d94afc557933d Signed-off-by: Marc Schink <openocd-dev@marcschink.de> [andreas.fritiofson@gmail.com: don't check pointers before free()] Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/2881 Tested-by: jenkins
2015-03-25armv7m: add generic trace support (TPIU, ITM, etc.)Paul Fertser1-0/+3
This provides support for various trace-related subsystems in a generic and expandable way. Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2538 Tested-by: jenkins
2015-03-09armv7m: do not access FPU registers when not presentPaul Fertser1-4/+4
This is runtime and valgrind tested with l0, l1 and f3 hla boards. Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2516 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
generated by cgit v1.1 at 2024-09-28 06:13:35 +0000