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path: root/src/target/arm_adi_v5.c
AgeCommit message (Expand)AuthorFilesLines
2024-03-16target/arm_adi_v5: introduce adiv5_jim_configure_ext()Tomas Vanek1-9/+18
2024-01-06target/adiv5: probe MEM-AP supported transfer sizes including large dataTomas Vanek1-125/+241
2024-01-06target/arm_adi_v5: rework Nuvoton NPCX quirk workaround.Tomas Vanek1-15/+19
2024-01-06target/arm_adi_v5: simplify TI BE 32 quirk workaroundTomas Vanek1-51/+24
2023-12-29target/arm_adi_v5: fix DP SELECT logicTomas Vanek1-1/+5
2022-10-08target/adiv5: 64-bit TAR setup bugfixDaniel Goehring1-1/+1
2022-09-18openocd: fix SPDX tag format for files .cAntonio Borneo1-1/+1
2022-07-30arm_adi_v5: Adding Nuvoton NPCX quirkBen Bender1-0/+34
2022-07-23openocd: src/target: replace the GPL-2.0-or-later license tagAntonio Borneo1-13/+2
2022-06-24arm_adi_v5: parse ROM tables behind SoC-600 APv1 adapterAntonio Borneo1-3/+12
2022-06-24adiv6: stay in same AP during dap_lookup_cs_component()Antonio Borneo1-0/+7
2022-06-24adiv6: add support for ROM tables in APAntonio Borneo1-31/+141
2022-06-24adiv6: prepare for AP level ROM tablesAntonio Borneo1-16/+28
2022-06-24arm_adi_v5: add option 'root' to 'dap info' commandAntonio Borneo1-3/+41
2022-06-24adiv6: use struct adiv5_ap->ap_num to contain the AP base addressAntonio Borneo1-38/+98
2022-06-24adiv6: re-organize mem_ap registers definitionKevin Burke1-29/+25
2022-06-24arm_adi_v5: add ap refcount and add get/put around ap useAntonio Borneo1-21/+140
2022-06-10arm_adi_v5: check for calloc() return valueAntonio Borneo1-0/+4
2022-06-10arm_adi_v5: fix scan-build warning [3/3]Antonio Borneo1-0/+2
2022-06-10arm_adi_v5: fix scan-build warning [2/3]Antonio Borneo1-1/+3
2022-06-10arm_adi_v5: fix scan-build warning [1/3]Antonio Borneo1-2/+3
2022-05-14arm_adi_v5: add support for 64bit Class 0x9 ROM tablesAntonio Borneo1-11/+32
2022-05-14arm_adi_v5: replace dap_lookup_cs_component()Antonio Borneo1-73/+85
2022-05-14arm_adi_v5: let dap_lookup_cs_component() to get AP dbgbaseAntonio Borneo1-3/+17
2022-05-14arm_adi_v5: abstract actions during ROM table parsingAntonio Borneo1-30/+123
2022-05-14arm_adi_v5: separate ROM table parsing from command output [3/3]Antonio Borneo1-17/+41
2022-05-14arm_adi_v5: separate ROM table parsing from command output [2/3]Antonio Borneo1-65/+103
2022-05-14arm_adi_v5: separate ROM table parsing from command output [1/3]Antonio Borneo1-6/+44
2022-05-14arm_adi_v5: handle faulting entry in ROM tableAntonio Borneo1-2/+5
2022-05-14arm_adi_v5: report sysmem on class 0x9 ROM tablesAntonio Borneo1-1/+10
2022-05-14arm_adi_v5: split ROM table loop from generic coresightAntonio Borneo1-36/+66
2022-05-14arm_adi_v5: rework dap_read_part_id()Antonio Borneo1-69/+80
2022-05-14arm_adi_v5: add support for display Class 0x9 ROM tablesFlorian Fainelli1-22/+47
2022-05-14arm_adi_v5: describe Class 0x9 Device Architecture registerAntonio Borneo1-0/+49
2022-05-14arm_coresight: define ARM_CS_CIDR_CLASS()Antonio Borneo1-1/+1
2021-09-25arm_adi_v5: drop ANY_ID from table dap_part_numsAntonio Borneo1-16/+5
2021-09-25arm_adi_v5: add arm Neoverse N2 part numbersAntonio Borneo1-0/+1
2021-09-25arm_adi_v5: add arm Neoverse N1 part numbersKevin Burke1-0/+1
2021-09-25arm_adi_v5: add arm Cortex-R52 part numbersAntonio Borneo1-0/+5
2021-09-25arm_adi_v5: add arm SoC-600 part numbersAntonio Borneo1-0/+14
2021-09-25arm_adi_v5: add helper to search for part numberAntonio Borneo1-27/+26
2021-09-25arm_adi_v5: move in a separate function devtype decode/displayKevin Burke1-140/+149
2021-09-25arm_adi_v5: simplify handling of AP typeAntonio Borneo1-50/+31
2021-09-25arm_coresight: add include file and use itAntonio Borneo1-47/+39
2021-08-22jep106: use packed jedec manufacturer codeAntonio Borneo1-20/+20
2021-08-22arm_adi_v5: update coresight class namesAntonio Borneo1-7/+22
2021-08-14arm_adi_v5: use macro DP_APSEL_MAX in place of magic numberAntonio Borneo1-1/+1
2021-08-14arm_adi_v5: fix access to 64-bit MEM-APAntonio Borneo1-11/+22
2021-08-14arm_adi_v5: fix signed offset in Class 0x1 ROM tablesAntonio Borneo1-2/+2
2021-07-24arm_adi_v5: Added Cortex-A76 identifiersFlorian Fainelli1-0/+2
generated by cgit v1.1 at 2024-10-19 05:12:32 +0000