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2024-05-30Merge up to 437dde701c13e707e5fd912ef6403e09052e4d9b from upstreamEvgeniy Naydanov1-1/+0
Conflict in src/rtos/FreeRTOS.c due to fbea7d5d38d0dcbdd71cb574da9bd12c78b568cf -- resolved by replacing `target->type->name` with a call to `target_type_name()`. Change-Id: I56702c6133894458903de7a4d764903004aa8b86
2024-05-26openocd: drop include of target_type.hAntonio Borneo1-1/+0
Few files include target_type.h even if it is not needed. Drop the include. Other files access directly to target type's name instead of using the proper API target_type_name(). Use the API and drop the include. Change-Id: I86c0e0bbad51db93500c0efa27b7d6f1a67a02c2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8260 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-10-27Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstreamTim Newsome1-2/+0
Conflicts: HACKING src/target/riscv/riscv-013.c Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef
2023-07-06rtos/hwthread: Call rtos_free_threadlist() again.Tim Newsome1-0/+3
I think this was incorrectly removed in a merge. Change-Id: I49fce230f35ae7bd368d2ed780c6c1ffe5939fda
2023-05-18rtos: move prototype of rtos_thread_packet() in rtos.hAntonio Borneo1-2/+0
The function rtos_thread_packet() is used across rtos and declared locally as extern. Move the prototype of the function in common include rtos.h Change-Id: I50d311b583148a2de628de0997ef1afc9103a70e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7677 Tested-by: jenkins
2023-05-04Merge commit '228fe7300c7df7aa05ba2c0bc19edde6d0156401' into from_upstreamTim Newsome1-8/+22
Conflicts: doc/openocd.texi src/jtag/aice/aice_pipe.c src/jtag/aice/aice_usb.c src/rtos/FreeRTOS.c src/rtos/hwthread.c src/rtos/rtos_standard_stackings.c src/target/riscv/riscv.c Change-Id: I0c6228c499d60274325be895fbcd8007ed1699bc
2023-03-16Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstreamTim Newsome1-15/+1
This includes https://sourceforge.net/p/openocd/mailman/message/37710818/, which should fix #814. Conflicts: .travis.yml contrib/loaders/flash/stm32/stm32f1x.S contrib/loaders/flash/stm32/stm32f2x.S doc/openocd.texi src/rtos/FreeRTOS.c src/server/gdb_server.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h src/target/riscv/riscv_semihosting.c tcl/target/esp_common.cfg tcl/target/gd32vf103.cfg tools/scripts/checkpatch.pl Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
2022-12-03hwthread: Restore current_threadid in hwthread_update_threadsKoudai Iwahori1-0/+10
When OpenOCD receives a step-execution command from GDB and the target is configured as rtos=hwthread, OpenOCD reconstructs the thread-info. However, OpenOCD does not restore the thread id which is currently selected by GDB. Due to this issue, OpenOCD sends the information of wrong thread to GDB after the step execution. This commit fixes the above issue by adding a code to save/restore the thread id selected by GDB. Signed-off-by: Koudai Iwahori <koudai@google.com> Change-Id: I761a1141c04d48f1290e4f09baa7c7024f86f36a Reviewed-on: https://review.openocd.org/c/openocd/+/7358 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-12-03hwthread: Add register validity check in get_thread_reg_listKoudai Iwahori1-0/+9
When OpenOCD receives 'g' packet (read general registers) from GDB and target is configured as rtos=hwthread, hwthread_get_thread_reg_list is called. However, it does not check if the register valid or not. Due to this issue, OpenOCD returns invalid register values to GDB. This commit adds a validity check to hwthread_get_thread_reg_list. If the register is not valid, it tries to read the register from the target. Signed-off-by: Koudai Iwahori <koudai@google.com> Change-Id: Iad6424b62124271ec411b1dfc044b57dfc460280 Reviewed-on: https://review.openocd.org/c/openocd/+/7357 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-22rtos/hwthread: Hide unavailable targets from thread list.Tim Newsome1-2/+4
Change-Id: I53c6e2876d9bab70800a0f080e72a2abe0499120 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-11rtos: hwthread: fix clang error core.NullDereferenceAntonio Borneo1-4/+4
Clang spots a potential NULL pointer dereferencing that is instead an incorrect use of an array of pointers: src/rtos/hwthread.c:254:32: warning: Dereference of null pointer [core.NullDereference] (*rtos_reg_list)[j].number = (*reg_list)[i].number; ^~~~~~~~~~~~~~~~~~~~~ The error has not been spotted before because: - this function is not called for the first core of the SMP node, - for the other cores on Cortex-A it still returns valid register value for the first 12 ARM registers, then it diverges. Also Valgrind does not spot any issue at runtime. Address the array correctly. While there, use DIV_ROUND_UP() macro for the computation. Change-Id: Ib87e60e0edfd9671091f5dcfa9aedaf1aed800d1 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7337 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-11-11Revert "Remove duplicate of a counter in hwthread_update_threads"Tomas Vanek1-3/+7
Commit 0cedf10f8fd6 ("Remove duplicate of a counter in hwthread_update_threads") introduced a code bug. In the second foreach_smp_target() loop, variable "threads_found" gets passed to routine hwthread_fill_thread(). By removing the counting of threads_found from the second loop, the incorrect thread counter value gets passed to hwthread_fill_thread(). Change-Id: Ie89e53ccd28bb72b6838ef2f12106a1fe8d00994 Suggested-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7307 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-10Improve a couple of user/debug messages. (#763)Tim Newsome1-1/+1
* gdb_server: Improve info message. Add target name and state to "Not running when halt was requested" message. Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd Signed-off-by: Tim Newsome <tim@sifive.com> * rtos/hwthread: Nicer debug message in hwthread_update_threads() Change-Id: Ia5931a772476a2ae186ed87cd70d7e4be2f196fb Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-08Remove duplicate of a counter in hwthread_update_threadsEvgeniy Naydanov1-7/+3
There is no need to count number of examined threads twice. Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: Id32ead853d1ddcd4e67062d6f795700feb20cb4b Reviewed-on: https://review.openocd.org/c/openocd/+/7223 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-09-18openocd: fix SPDX tag format for files .cAntonio Borneo1-1/+1
With the old checkpatch we cannot use the correct format for the SPDX tags in the file .c, in fact the C99 comments are not allowed and we had to use the block comment. With the new checkpatch, let's switch to the correct SPDX format. Change created automatically through the command: sed -i \ 's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \ $(find src/ contrib/ -name \*.c) Change-Id: I6da16506baa7af718947562505dd49606d124171 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7153 Tested-by: jenkins
2022-07-23openocd: src/rtos: replace the GPL-2.0-or-later license tagAntonio Borneo1-15/+1
Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: If0194089baded7f58dc5d87a35d6e0aff9f43785 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7070 Tested-by: jenkins
2022-03-03From upstream (#684)Tim Newsome1-3/+5
* flash/nor/atsame5: add LAN9255 devices Support Microchip LAN9255 devices with embedded SAME53J MCU. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Change-Id: Ia811c593bf7cf73e588d32873c68eb67c6fafad7 Reviewed-on: https://review.openocd.org/c/openocd/+/6811 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * tcl/board: Add EVB-LAN9255 config Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10 connector. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7 Reviewed-on: https://review.openocd.org/c/openocd/+/6812 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * aarch64: support for aarch32 ARM_MODE_UND Fix: unrecognized psr mode: 0x1b cannot read system control register in this mode: (UNRECOGNIZED : 0x1b) Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3 Signed-off-by: Julien Massot <julien.massot@iot.bzh> Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5 Reviewed-on: https://review.openocd.org/c/openocd/+/6808 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Combine register lists of smp targets. This is helpful when you want to pretend to gdb that your heterogeneous multicore system is homogeneous, because gdb cannot handle heterogeneous systems. This won't always works, but works fine if e.g. one of the cores has an FPU while the other does not. (Specifically, HiFive Unleashed has 1 core with no FPU, plus 4 cores with an FPU.) Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: I05ff4c28646778fbc00327bc510be064bfe6c9f0 Reviewed-on: https://review.openocd.org/c/openocd/+/6362 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * semihosting: use open mode flags from GDB, not from sys/stat.h Values defined in sys/stat.h are not guaranteed to match the constants defined by the GDB remote protocol, which are defined in https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags. On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is defined as 0x40, whereas GDB requires it to be 0x400, causing all "w" file open modes to misbehave. This patch has been tested with STM32F446. Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910 Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6804 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * semihosting: User defined operation, Tcl command exec on host Enabling a portion (0x100 - 0x107) of the user defined semihosting operation number range (0x100 - 0x1FF) to be processed with the help of the existing target event mechanism, to implement a general-purpose Tcl interface for the target available on the host, via semihosting interface. Example usage: - The user configures a Tcl command as a callback for one of the newly defined events (semihosting-user-cmd-0x10X) in the configuration file. - The target can make a semihosting call with <opnum>, passing optional parameters for the call. If there is no callback registered to the user defined operation number, nothing happens. Example usage: Configure RTT automatically with the exact, linked control block location from target. Signed-off-by: Zoltán Dudás <zedudi@gmail.com> Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247 Reviewed-on: https://review.openocd.org/c/openocd/+/6748 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target/smp: use a struct list_head to hold the smp targets Instead of reinventing a simply linked list, reuse the list helper for the list of targets in a smp cluster. Using the existing helper, that implements a double linked list, makes trivial going through the list in reverse order. Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6783 Tested-by: jenkins * helper/list: add list_for_each_entry_direction() Use a bool flag to specify if the list should be forward or backward iterated. Change-Id: Ied19d049f46cdcb7f50137d459cc7c02014526bc Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6784 Tested-by: jenkins * target/riscv: revive 'riscv resume_order' This functionality was lost in [1], which was merged as commit 615709d14049 ("Upstream a whole host of RISC-V changes."). Now it works as expected again. Add convenience macro foreach_smp_target_direction(). Link: [1] https://github.com/riscv/riscv-openocd/pull/567 Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6785 Tested-by: jenkins * doxygen: fix some function prototype description Change-Id: I49311a643ea73143839d2f6bde976cfd76f8c67f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6830 Tested-by: jenkins * Cadence virtual debug interface (vdebug) integration Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6097 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * gdb_server: Include thread name as XML attribute Explicitly providing a thread name in the "thread" element produces better thread visualizations in downstream tools like IDEs. Signed-off-by: Ben McMorran <bemcmorr@microsoft.com> Change-Id: I102c14ddb8b87757fa474de8e3a3f6a1cfe10d98 Reviewed-on: https://review.openocd.org/c/openocd/+/6828 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Fix small memory leak. See https://github.com/riscv/riscv-openocd/pull/672 Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6831 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * server: remove remaining crust from dropped eCos code Commit 39650e2273bc ("ecosboard: delete bit-rotted eCos code") has removed eCos code but has left some empty function that was used during non-eCos build to replace eCos mutex. Drop the functions and the file that contain them. Change-Id: I31bc0237ea699c11bd70921660f960ee406ffa80 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6835 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * rtos: threadx: Add hla_target support for ThreadX Tested with an AZ3166 dev board (which uses the STM32F412ZGT6) running the Azure RTOS ThreadX demonstration system. Signed-off-by: Ben McMorran <bemcmorr@microsoft.com> Change-Id: I44c8f7701d9f1aaa872274166321cd7d34fb1855 Reviewed-on: https://review.openocd.org/c/openocd/+/6829 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * .gitmodules: switch away from repo.or.cz The host repo.or.cz is often offline, creating issues for cloning and building OpenOCD from scratch. Already 'jimtcl' developer has dropped repo.or.cz, triggering the OpenOCD commit 861e75f54efb ("jimtcl: switch to github"). Change also the link of the remaining submodules 'git2cl' and 'libjaylink' to their respective main repository. Change-Id: Ib513237427635359ce36a480a8f2060e2fb12ba4 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6834 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> * flash/nor/stm32f2x: Fix erase of bank 2 sectors This commit corrects the erase function for stm32f2x when dealing with sectors in bank 2, for STM32F42x/43x devices with 1MB flash. On STM32F42x/43x with 1MB flash in dual bank configuration, the sector numbering is not consecutive. The last sector in bank 1 is number 7, and the first sector in bank 2 is number 12. The sector indices used by openocd, however, _are_ consecutive (0 to 15 in this case). The arguments "first" and "last" to stm32x_erase() are of this type, and so the logic surrounding sector numbers needed to be corrected. Since the two banks in dual bank mode have the same number of sectors, a sector index in bank 2 is larger than or equal to half the total number of sectors. Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18 Signed-off-by: Simon Johansson <ampleyfly@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6810 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> * target/cortex_m: fix target_to_cm() helper The third parameter of container_of() should point to the same member as target->arch_info points to, struct arm. It worked just because struct arm is the first member in struct armv7m_common. If you move arm member from the first place, OpenOCD fails heavily. Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6749 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target/armv7m,cortex_m: introduce checked arch_info cast routines target_to_armv7m() and target_to_cm() do not match the magic number so they are not suitable for use outside of target driver code. Add checked versions of pointer getters. Match the magic number to ensure the returned value points to struct of the correct type. Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6750 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target/cortex_m: add Cortex-M part number getter The getter checks the magic numbers in arch_info to detect eventual type mismatch. Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6751 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> * flash/nor/stm32xx: fix segfault accessing Cortex-M part number Some of STM32 flash drivers read Cortex-M part number from cortex_m->core_info. In corner cases the core_info pointer was observed uninitialised even if target_was_examined() returned true. See also [1] Use the new and safe helper to get Cortex-M part number. While on it switch also target_to_cm()/target_to_armv7m() to the safe versions. This prevents a crash when the flash bank is misconfigured with non-Cortex-M target. Add missing checks for target_was_examined() to flash probes. [1] 6545: fix crash in case cortex_m->core_info is not set https://review.openocd.org/c/openocd/+/6545 Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Fixes: f5898bd93ff8 (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common) Reviewed-on: https://review.openocd.org/c/openocd/+/6752 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> * cpld: altera-epm240: Add additional IDCODEs This adds some additional IDCODEs from the datasheet. It also adds support for customizing the tap name. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e Reviewed-on: https://review.openocd.org/c/openocd/+/6846 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * cpld: altera-epm240: Increase adapter speed According to the datasheet, the minimum clock period with Vccio1 = 1.5V (the lowest voltage supported) is 143ns, or around 6MHz. Set the default adapter speed to 5 MHz. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target: Add support for ls1088a The LS1088A is an octo-core aarch64 processor from NXP in the layerscape family. The JTAG is undocumented, but I was able to figure things out from the output of `dap info`. This is the first in-tree example of using the hwthread rtos (as far as I know), so hopefully it can serve as an example to other developers. There are some ETMs, but I was unable to try them out because I got 'invalid command name "etm"' when trying to test things out. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2 Reviewed-on: https://review.openocd.org/c/openocd/+/6848 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target: ls1088a: Add service processor Normally the service processor is not necessary for debugging. However, if you are using the hard-coded RCW or your boot source is otherwise corrupt, then the general purpose processors will never be released from hold-off. This will cause GDB to become confused if it tries to attach, since they will appear to be running arm32 processors. To deal with this, we can release the CPUs manually with the BRRL register. This register cannot be written to from the axi target, so we need to do it from the service processor target. This involves halting the service processor, modifying the register, and then resuming it again. We try and determine what state the service processor was in to avoid resuming it if it was already halted. The reset vector for the general purpose processors is determined by the boot logation pointer registers in the device configuration unit. Normally these are set using pre-boot initialization commands, but if they are not set then they default to 0. This will cause the CPU to almost immediately hit an illegal instruction. This is fine because we will almost certainly want to attach to the processor and load a program anyway. I considered adding this as an event handler for either gdb-attach or reset-init. However, this command shouldn't be necessary most of the time, and so I don't think we should run it automatically. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c Reviewed-on: https://review.openocd.org/c/openocd/+/6850 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * board: Add NXP LS1088ARDB This adds a board file for the NXP LS1088ARDB. This only covers the "primary" JTAG header J55, and not the PCIe header (J91). The only oddity is that the LS1088A and CPLD are muxed by adding/removing a jumper from J48. Unfortunately, it doesn't look like OpenOCD supports this CPLD beyond determining the irlen, so it's not very useful. Those who are interested in experimenting can define CWTAP to access the CPLD, but the default is to access the CPU. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24 Reviewed-on: https://review.openocd.org/c/openocd/+/6849 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * gdb_server: fix double free Commit 6541233aa78d ("Combine register lists of smp targets.") unconditionally assigns the output pointers of the function smp_reg_list_noread(), even if the function fails and returns error. This causes a double free from the caller, that has assigned NULL to the pointers to simplify the error handling. Use local variables in smp_reg_list_noread() and assign the output pointers only on success. Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae Fixes: 6541233aa78d ("Combine register lists of smp targets.") Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6852 Tested-by: jenkins Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Reviewed-by: Tim Newsome <tim@sifive.com> * gdb_server: check target examined while combining reg list Commit 6541233aa78d ("Combine register lists of smp targets.") assumes that all the targets in the SMP cluster are already examined and unconditionally call target_get_gdb_reg_list_noread() that will in turn return error if the target is not examined yet. Skip targets not examined yet. Add an additional check in case the register list cannot be built, e.g. because no target in the SMP cluster is examined. This should never happen, but it's better to play safe. Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a Fixes: 6541233aa78d ("Combine register lists of smp targets.") Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6853 Tested-by: jenkins Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Reviewed-by: Tim Newsome <tim@sifive.com> * flash/stm32l4x: fix maybe-uninitialized compiler error using gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0 we get: error: ‘retval’ may be used uninitialized in this function fixes: 13cd75b6ecfd (flash/nor/stm32xx: fix segfault accessing Cortex-M part number) Change-Id: I897c40c5d2233f50a5385d251ebfa536023e5cf7 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6861 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Fix build. Change-Id: Ia60246246dd859d75659a43d1c59588dbb274d46 Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Co-authored-by: Julien Massot <julien.massot@iot.bzh> Co-authored-by: Pavel Kirienko <pavel.kirienko@gmail.com> Co-authored-by: Zoltán Dudás <zedudi@gmail.com> Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com> Co-authored-by: Jacek Wuwer <jacekmw8@gmail.com> Co-authored-by: Ben McMorran <bemcmorr@microsoft.com> Co-authored-by: Simon Johansson <ampleyfly@gmail.com> Co-authored-by: Tomas Vanek <vanekt@fbl.cz> Co-authored-by: Sean Anderson <sean.anderson@seco.com> Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-02-14target/smp: use a struct list_head to hold the smp targetsAntonio Borneo1-3/+5
Instead of reinventing a simply linked list, reuse the list helper for the list of targets in a smp cluster. Using the existing helper, that implements a double linked list, makes trivial going through the list in reverse order. Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6783 Tested-by: jenkins
2022-01-31Ask the RTOS which target to set swbp on. (#673)Tim Newsome1-0/+9
This lets the RTOS pick the "current" target, which matters if address translation differs between threads. Change-Id: I5b5510ab6a06621589c902f42a91562055817dc4 Signed-off-by: Tim Newsome <tim@sifive.com>
2021-10-05Dynamically allocate memory for RTOS registers. (#647)Tim Newsome1-10/+13
This makes things work on RISC-V cores with large vector registers (which can be up to kilobytes in size). Change-Id: Ie53cb43a88e2a475f695cd5c1e28605569926817 Signed-off-by: Tim Newsome <tim@sifive.com>
2021-08-30Merge branch 'master' into from_upstreamTim Newsome1-19/+19
Conflicts: src/flash/nor/fespi.c src/jtag/drivers/ftdi.c src/rtos/FreeRTOS.c src/rtos/hwthread.c src/rtos/rtos.c src/rtos/rtos.h src/rtos/rtos_ecos_stackings.c src/rtos/rtos_embkernel_stackings.c src/rtos/rtos_standard_stackings.c src/rtos/rtos_standard_stackings.h src/rtos/rtos_ucos_iii_stackings.c src/server/gdb_server.c src/server/server.c src/target/riscv/riscv-013.c src/target/target.c src/target/target.h Change-Id: If0924a3e799260c33fae5feb85975b1273b45a0f
2021-07-24openocd: remove NULL comparisons with checkpatch [1/2]Antonio Borneo1-6/+6
Patch generated automatically through the new checkpatch with flags "--types COMPARISON_TO_NULL --fix-inplace". This only fixes the comparisons if (symbol == NULL) if (symbol != NULL) The case of NULL on the left side of the comparison is not tested. Some automatic fix is incorrect and has been massaged by hands: - if (*psig == NULL) + if (*!psig) changed as + if (!*psig) Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6351 Tested-by: jenkins
2021-07-24openocd: fix simple cases of NULL comparisonAntonio Borneo1-9/+9
There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-07-02Add RTOS memory read/write functions.Tim Newsome1-0/+36
If not implemented, these specify to regular target read/write. However, if individual threads in an RTOS can have different address translation configured then the RTOS support can use this to do the right thing. Use this in hwthread, where of course address translation can be set up differently for different real cores. Change-Id: I62c501cff1f863d855ee197dee7b73204ea8885a Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/6327 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-04-13Merge branch 'master' into from_upstreamTim Newsome1-3/+3
Conflicts: .github/workflows/snapshot.yml NEWS configure.ac contrib/loaders/checksum/riscv_crc.c jimtcl src/helper/time_support.h src/jtag/drivers/arm-jtag-ew.c src/rtos/FreeRTOS.c src/target/image.c src/target/riscv/riscv.c Change-Id: I043624ba540d4672fc123dddb2066bcb9c6b5a05
2021-03-10rtos: Remove typedef'd structMarc Schink1-3/+3
The C style guide forbids typedef'd structs, see 'Naming Rules'. Change-Id: Ia7c8218fb61ff0c74b6dd0d10fb51a77cf059c14 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/6028 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-12-31Merge branch 'master' into from_upstreamTim Newsome1-13/+25
Conflicts: .github/workflows/snapshot.yml .gitmodules src/flash/nor/drivers.c src/helper/jep106.inc src/rtos/hwthread.c src/target/riscv/riscv.c src/target/target.c Change-Id: I62f65e10d15dcda4c405d4042cce1d96f8e1680a
2020-12-26rtos/hwthread: fix register list for armv7aAntonio Borneo1-5/+17
The targets armv7a in file cortex_a.c inherit the register list from file armv4_5.c thus, depending on the core status, some register get marked as not existing. For HW threads other than current target, the registers in the list are not checked for existence and are all forwarded to GDB that in turns complains for too many data: Remote 'g' packet reply is too long (expected 68 bytes, got 104 bytes) Check all the attributes of the registers and pass to GDB only the valid registers. To test it, use a SMP cortex-a target (2 cores are enough) and add -rtos hwthread to all the cores. Connect GDB to OpenOCD and issue the GDB command info threads Change-Id: Ie66119fe83a3c8d53e9d18dda39e60fd97769669 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5981 Tested-by: jenkins
2020-11-04rtos: declare local symbols as staticAntonio Borneo1-2/+2
Functions and variables that are not used outside the file should be declared as static. Change-Id: I9731a35496cd1c7421563c8961da5fa0e3cc71c3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5894 Tested-by: jenkins Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li>
2020-10-15Merge branch 'master' into from_upstream_histogramTim Newsome1-1/+1
Used histogram diff strategy, which was much better than the default. Conflicts: doc/openocd.texi src/flash/nor/fespi.c src/jtag/drivers/libjaylink src/rtos/rtos.c src/target/riscv/batch.c src/target/riscv/encoding.h src/target/riscv/riscv-011.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h src/target/target.c tcl/target/gd32vf103.cfg Change-Id: I1321f62ba719419e58f93b2195f2540bd62f50d2
2020-09-05openocd: use proper format with uint32_tAntonio Borneo1-1/+1
Modify the format strings to properly handle uint32_t data types. Change-Id: I4de49bf02c9e37b72240224c23fc83abe8a4fa83 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5819 Tested-by: jenkins
2020-06-23Fix build.Tim Newsome1-2/+2
Change-Id: Id96e590984eb8488f6367b4c8778e2dc5adf3c1b
2020-06-23Merge branch 'master' into from_upstreamTim Newsome1-5/+5
Conflicts: .gitmodules .travis.yml jimtcl src/jtag/core.c src/jtag/drivers/ftdi.c src/jtag/drivers/libjaylink src/jtag/drivers/mpsse.c src/jtag/drivers/stlink_usb.c src/rtos/hwthread.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c tcl/board/sifive-hifive1-revb.cfg Change-Id: I2d26ebeffb4c1374730d2e20e6e2a7710403657c
2020-05-07Add get_thread_reg() and set_reg() for hwthreadTim Newsome1-51/+90
get_thread_reg() allows gdb to request the register value of a specific "thread." set_reg() allows register writes without getting a giant list of registers first. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: I87faa1c8793916b9ee476dd696f0695a07ca2b41 Reviewed-on: http://openocd.zylin.com/5324 Tested-by: jenkins
2020-03-26Use the correct thread for memory accesses. (#459)Tim Newsome1-1/+37
* Deal with vlenb being unreadable. Instead of exiting during examine(), spit out a warning, and don't expose the vector data registers. We do provide access to the vector CSRs, because maybe they do work? It's just that we have no idea what the size of the data registers is. Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd * WIP Change-Id: I46292eefe537aeaf72bdd44e4aa58298b5120b00 * Use the correct thread for memory accesses. Previously, OpenOCD would perform RTOS memory accesses through the first thread in the RTOS. This doesn't work if different threads have a different memory view. For instance if `-rtos hwthread` is used, each configured core could have address translation configured differently. Change-Id: I61328c8f50065ecba5ce1797dbeaee482812f799
2019-08-14Don't fake step for hwthread rtos. (#393)Tim Newsome1-1/+7
Fake step is a hack introduced to make things work with real RTOSs that have a concept of a current thread. The hwthread rtos always has access to all threads, so doesn't need it. This fixes a bug when running my MulticoreRegTest against HiFive Unleashed where OpenOCD would return the registers of the wrong thread after gdb stepped a hart. Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
2019-04-03Merge branch 'master' into from_upstreamTim Newsome1-1/+1
Conflicts: src/flash/nor/at91sam4.c src/flash/nor/at91sam4l.c src/flash/nor/at91samd.c src/flash/nor/ath79.c src/flash/nor/atsame5.c src/flash/nor/cfi.c src/flash/nor/core.c src/flash/nor/fespi.c src/flash/nor/kinetis.c src/flash/nor/kinetis_ke.c src/flash/nor/lpc2000.c src/flash/nor/niietcm4.c src/flash/nor/nrf5.c src/flash/nor/numicro.c src/flash/nor/pic32mx.c src/flash/nor/stm32h7x.c src/flash/nor/stm32lx.c src/flash/nor/stmsmi.c src/flash/nor/tcl.c src/flash/nor/tms470.c src/flash/nor/virtual.c src/flash/nor/xmc4xxx.c src/rtos/hwthread.c src/rtos/rtos.c src/server/gdb_server.c src/target/riscv/riscv-011.c src/target/riscv/riscv-013.c src/target/riscv/riscv.c src/target/riscv/riscv.h Change-Id: I9f0f373d45a9e5845bca83ca52e977f727ea4425
2019-03-08rtos/hwthread: add hardware-thread pseudo rtosMatthias Welwarsky1-0/+347
This patch adds "hwthread", a pseudo rtos that represents cpu cores in an SMP system as threads to gdb. This allows to debug SMP system kernels in a more sensible manner and removes the current atrocities of switching gdb manually between CPU cores to update the context. Change-Id: Ib781c6c34097689d21d9e02011e4d74a4a742379 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3999 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Graham Sanderson <graham.sanderson@gmail.com>
2019-02-07Rtos riscv (#350)Tim Newsome1-3/+10
* Implement riscv_get_thread_reg(). This is necessary because riscv_get_gdb_reg_list() now reads all registers, which ended up causing `-rtos riscv` to read all registers whenever one was requested (because the register cache is wiped every time we switch to a different hart). CustomRegisterTest went from 1329s to 106s. Change-Id: I8e9918b7a532d44bca927f67aae5ac34954a8d32 * Also implement riscv_set_reg(). Now all the `-rtos riscv` tests pass again, at regular speed. Change-Id: I55164224672d9dcc9eb4d1184b47258ff3c2cff1 * Better error messages. Change-Id: I4125f9a54750d9d0ee22c4fa84b9dd3f5af203f5 * Add target_get_gdb_reg_list_noread(). Being explicit about what's expected gets `-rtos riscv` back to `-rtos hwthread` time. Change-Id: I6e57390c2fe79b5e6799bfda980d89697e2e29f7 * Revert a change I made that has no effect. I don't understand exactly what all this test protects against, and I shouldn't change it unless I do. Change-Id: Ib329d4e34d65d2b38559b89b7afb3678f439ad2c
2019-01-25Use more compatible printf formatting.Tim Newsome1-1/+1
Change-Id: I5d5b46f3e6c4f5abff1c0efa3ea8b4f589c1e635
2019-01-25Remove debug statements.Tim Newsome1-28/+2
Change-Id: If37bc883fea0b83740bfd6a7fcb2091db0ac61f0
2019-01-24WIP on hardware breakpoints.Tim Newsome1-3/+17
This is messy, but contains at least some bugfixes. 39/43 tests pass now. Change-Id: Ic9e8dad2a0ceb237e28c93906d1cd60876a5766d
2019-01-18Don't reset current thread id on single step.Tim Newsome1-13/+20
Now passing 36/45 tests. Change-Id: I244b045f84397b058cf526e3bff238cb05d8ad06
2019-01-17Fix reading of non-general registers for hwthreadTim Newsome1-3/+36
Previously the code made the assumption (which is valid for conventional RTOSs) that special registers (e.g. CSRs) are the same across threads. 26/45 tests pass. Change-Id: Ibb3398790d7354a995d506772375d869f608f1f0
2019-01-11rtos support to write registers on current threadTim Newsome1-47/+49
I don't understand how it was ever possible to change the registers on a thread that's not the current active one when a halt happened. Really instead of the RTOS tracking what the currently selected thread is, it would make more sense to have gdb_server do that and simply pass it along in every call to the RTOS layer. Now MulticoreRegTest passes. Change-Id: I399b9b2b05a147aa6b41463714ed3a39534b1fc8
2019-01-07Implement hwthread_get_thread_reg_list.Tim Newsome1-4/+22
MulticoreRegTest now gets past the first check on all GPRs. Change-Id: I35f3c51273542668985f7a86965c1e947fc12194
2019-01-03Neuter hwthread_get_thread_reg_list so it buildsTim Newsome1-66/+6
Change-Id: I07cf72ea1874ca7cb5557677ecb751c931174419
2019-01-02rtos/hwthread: add hardware-thread pseudo rtosMatthias Welwarsky1-0/+394
This patch adds "hwthread", a pseudo rtos that represents cpu cores in an SMP system as threads to gdb. This allows to debug SMP system kernels in a more sensible manner and removes the current atrocities of switching gdb manually between CPU cores to update the context. Change-Id: Ib781c6c34097689d21d9e02011e4d74a4a742379 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Source: http://openocd.zylin.com/#/c/3999
generated by cgit v1.1 at 2024-08-17 06:15:57 +0000