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2024-07-13flash/nor/nrf5: remove asserts on dereferenced pointersTomas Vanek1-32/+0
The driver code works reliably, no need to use assert() everywhere. Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: Idb1942bfd31d370a74610b8a8836bc2e64370557 Reviewed-on: https://review.openocd.org/c/openocd/+/8324 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13flash/nor/nrf5: split chip and bank probesTomas Vanek1-32/+72
nrf5_auto_probe() always re-probed chip hardware to get flash geometry. Introduce nrf5_probe_chip() and move chip related probing to it. Save all flash parameters needed for bank setup to struct nrf5_info. Introduce nrf5_setup_bank() and move bank setup code to it. Call both chip probe and bank setup unconditionally from nrf5_probe(): in case of manual issuing 'flash probe' command, we should refresh actual values from the device. Call chip probe and bank setup only if not done before from nrf5_auto_probe(). Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: Ib090a97fd7a41579b3d4f6e6634a5fdf93836c83 Reviewed-on: https://review.openocd.org/c/openocd/+/8322 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13target/xtensa: flag additional write-only registersIan Thompson1-3/+3
intsetN, intclearN (for LX8) mesrclr (for NX) Signed-off-by: Ian Thompson <ianst@cadence.com> Change-Id: I0bb59728fcec761a71c4789189f733a10bad6375 Reviewed-on: https://review.openocd.org/c/openocd/+/8235 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-07-13target: cortex_m: replace 'implementor' with 'implementer'Antonio Borneo3-28/+28
ARM documentation for Cortex-M reports the field 'implementer' in the register CPUID. OpenOCD used the miss-spelled 'implementor'. Fix it! Change-Id: I854d223971ae7a49346e1f7491c2c0415f5e2c1d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8318 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de>
2024-07-13target: cortex_m: add detection for Cortex-M52Antonio Borneo2-0/+7
Add Cortex-M52 to the list of known Cortex-M implementations to allow detection of the core. Values checked against the ARM document "Arm China Cortex®-M52 Processor Technical Reference Manual" 102776_0002_06_en. Reported-by: Joseph Yiu <Joseph.Yiu@arm.com> Change-Id: Id0bde8a0476f76799b7274835db9690f975e2dd6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8317 Tested-by: jenkins
2024-07-13target: cortex_m: fix detection of STAR-MC1 deviceAntonio Borneo2-1/+2
The detection of Cortex-M STAR-MC1 was introduced with [1], at a time when OpenOCD was only checking the field PartNo of the CPUID register. Later-on [2], OpenOCD extended the check to the field implementer of CPUID register. The value for ARM (0x41) implementer was used to all the Cortex-M, but no feedback for STAR-MC1 was available. A comment reporting the possible mismatch was added. As reported on OpenOCD mailing-list, the technical reference manual for STAR-MC1 is now available [3] and it reports the implementer as ARM China (0x63) [3]. Fix the STAR-MC1 implementer accordingly. Reported-by: Joseph Yiu <Joseph.Yiu@arm.com> Change-Id: I8ed1064a847b73065528ee7032be967b5c58b431 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Link: [1] 7dc4be3157d6 ("target/arm: Add support with identify STAR-MC1") Fixes: [2] 05ee88915520 ("target/cortex_m: check core implementor field") Link: [3] https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160 Reviewed-on: https://review.openocd.org/c/openocd/+/8316 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-07-13tcl: Replace 'hla_' prefix with 'hla' command groupMarc Schink3-8/+8
Change-Id: I99ec2dc7f300352d091cf9eb807a690901c33307 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8338 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-07-13jtag/hla: Restructure commandsMarc Schink3-11/+52
Use a command group 'hla' with subcommands instead of individual commands with 'hla_' prefix. The old commands are still available to ensure backwards compatibility, but are marked as deprecated. Change-Id: I612e3cc080d308735932aea0f11001428eadc570 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8335 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13openocd: fix some coding styleMark Zhuang2-2/+2
Add space around math operators. Change-Id: I50fce3da283a78ba02bf70b6a752f7bf778d79f5 Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7585 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13openocd: build: prevent old clone to fail on git submodulesAntonio Borneo1-2/+2
Working on an old local git repository, the git sub-modules could have been set before last changes in .gitmodules. The script 'bootstrap' does not update the url of the repositories and this can cause the script to fail. Add 'git submodule sync' to the script to update the url of the repositories. While there, fuse 'git submodule init' and git submodule update' in a single command. Reported-by: Karl Hammar <karl@aspodata.se> Change-Id: I61412f804dbbb7a843aa009139ddb4b8e71beefb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8375 Tested-by: jenkins
2024-07-13doc: Refurbish manual pageMarc Schink1-14/+7
Remove the outdated option '--pipe' and bring the description of OpenOCD up to date without focus on JTAG only. Change-Id: If52e936a366dde21c1dd514bd3960d100b540e77 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8347 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13AUTHORS: Refer to source code and Git historyMarc Schink1-12/+2
The list of authors and contributors is not maintained and outdated for years now. Refer to the source code and Git history instead of keeping a separate list. Change-Id: I9a92e8e0d5073b56030bc36086b76e28de96389f Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8346 Reviewed-by: Jonathan McDowell <noodles-openocd@earth.li> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13doc: Remove outdated '-pipe' optionMarc Schink1-2/+0
Change-Id: Ie3a7a3aaf69485f16b2447bd1dfa7622b584c7c0 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8348 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-07-13flash: psoc6: drop use of 'coreid' to identify the CPUAntonio Borneo2-4/+7
The flag '-coreid' is used by the command 'target create' to specify the debug controller of the target, either in case of a single debug controller for multiple CPU (e.g. RISC-V harts) or in case of multiple CPU on a DAP access port (e.g. Cortex-A SMP cluster). It is also currently used to specify the CPU ID in a SMP cluster, but this is going to be reworked. This flag has no effects on Cortex-M; ARM specifies that only one CPU Cortex-M can occupy the DAP access port by using hardcoded addresses. The flash driver 'psoc6' uses the flag '-coreid' to detect if the current target is the Cortex-M0 on AP#1 or the Cortex-M4 on AP#2 in the SoC. There are other ways to run such detection, without using such unrelated '-coreid' flag, e.g. using the AP number or the arch type of the target. Use the arch type to detect Cortex-M0 (ARM_ARCH_V6M) vs Cortex-M4 (ARM_ARCH_V7M). Drop the flags '-coreid' from the psoc6 configuration file. Change-Id: I0b9601c160dd4f2421a03ce6e3e7c55c6212f714 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8128 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-07-13doc: document 'target create' flags '-dbgbase' and '-coreid'Antonio Borneo1-0/+32
Add to the command 'target create' the description for the flags '-dbgbase' and '-coreid'. Report that '-coreid' is currently used for purposes other than CPU detection/examination, and that such uses are going to be re-considered. Change-Id: I25c839e3653101234c5862ce9da77019a5bb3249 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8129 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2024-07-12Merge pull request #1099 from en-sc/en-sc/sb-addr-batchEvgeniy Naydanov1-38/+37
target/riscv: write SB address using batch
2024-07-10target/riscv: write SB address using batchEvgeniy Naydanov1-38/+37
Reduces the number of JTAG queue flushes. Change-Id: Id103f5da1a3ea3177447046711e0e62a22c98c75 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-09Merge pull request #1096 from en-sc/en-sc/run-batch-busyEvgeniy Naydanov1-3/+7
target/riscv: reset `dmi.busy` after batches
2024-07-09Merge pull request #1083 from en-sc/en-sc/deprecate-reset-timeoutEvgeniy Naydanov5-77/+41
target/riscv: deprecate `riscv set_reset_timeout_sec`
2024-07-09Merge pull request #1081 from en-sc/en-sc/sb_read_v1Evgeniy Naydanov1-62/+32
target/riscv: use batch interface in `read_memory_bus_v1()`
2024-07-09Merge pull request #1093 from en-sc/en-sc/v-ext-csrsEvgeniy Naydanov1-0/+8
target/riscv: vector CSRs are optional
2024-07-09Align include guards with OpenOCD coding guidelinesTommy Murphy12-26/+35
Fixes: https://github.com/riscv-collab/riscv-openocd/issues/1097
2024-07-04target/riscv: deprecate `riscv set_reset_timeout_sec`Evgeniy Naydanov5-77/+41
Change-Id: I46bf3e4dab2a99c97b7ab133a85c13332365f9b7 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-04Merge pull request #1082 from en-sc/en-sc/sbcs-readEvgeniy Naydanov1-20/+8
target/riscv: simplify `sbcs` read in `write_memory_bus_v1()`
2024-07-03target/riscv: reset `dmi.busy` after batchesEvgeniy Naydanov1-3/+7
Additionally, avoid calling `riscv_batch_finished_scans()` / decrementing reset counter if the batch run failed. Change-Id: I3eb7b23e4dc029090e92e3e543719824add623e1 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-03target/riscv: vector CSRs are optionalEvgeniy Naydanov1-0/+8
This is a fix to a mistake made in ea7e17491d56ced52ab803949b23aa9579bb3c57. The newly introduced `gdb_regno_exist()` function was missing a part regarding vector CSRs. Link: https://github.com/riscv-collab/riscv-openocd/pull/1022/commits/ea7e17491d56ced52ab803949b23aa9579bb3c57#diff-b4aa16f9e42cb8f0934baa7c8e0ec9c70a369bef98b99b26ae2e896c8aa95d6aL6163-L6171 Change-Id: I0361ea4dce8df5be748e2c6e7e6838029d3a7120 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-03target/riscv: use batch interface in `read_memory_bus_v1()`Evgeniy Naydanov1-62/+32
Fixes #1080 Change-Id: Ifc1a48fcd0b28f7cdb1e5ad3cbd20d53ea3560a5 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-03Merge pull request #1087 from en-sc/en-sc/delay-typesEvgeniy Naydanov3-110/+167
target/riscv: replace `info->*_delay` with `riscv_scan_delays`
2024-07-03Merge pull request #1084 from en-sc/en-sc/ref-reg-filesEvgeniy Naydanov17-1486/+1678
target/riscv: separate register cache stuff into files
2024-07-02target/riscv: simplify `sbcs` read in `write_memory_bus_v1()`Evgeniy Naydanov1-20/+8
Change-Id: Ifc94614eaaa191925d44d8963cd6d1e5e8427cba Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-02target/riscv: separate register cache stuff into filesEvgeniy Naydanov17-1486/+1678
This commit creates file structure for register cache related functions. Specifically: * `riscv_reg.h` -- general interface to registers. Safe to use after register cache initialization is successful. * `riscv_reg_impl.h` -- helper functions to use while implementing register cache initialization. * `riscv_reg.c` -- definitions of functions from `riscv_reg.h` and `riscv_reg_impl.h`. * `riscv-011_reg.h` -- register cache interface specific to 0.11 targets. * `riscv-013_reg.h` -- register cache interface specific to 0.13+ targets. * `riscv-011/0.13.h` -- version-specific methods used to access registers. Will be extended as needed once other functionality (not related to register access) is separated (e.g. DM/DTM specific stuff). Change-Id: I7918f78d0d79b97188c5703efd0296660e529f2a Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-01target/riscv: replace `info->*_delay` with `riscv_scan_delays`Evgeniy Naydanov3-110/+167
* Improves error handling. * Handles possible overflow. Change-Id: Iae0df9356af06cc21dc71c86ba7c923d1515bdc5 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2024-07-01Merge pull request #1085 from en-sc/en-sc/checkpatch-check-gitEvgeniy Naydanov1-7/+1
.github/workflows: check git revisions instead of a diff
2024-07-01Merge pull request #1094 from en-sc/en-sc/from_upstreamEvgeniy Naydanov62-843/+1469
Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstream
2024-07-01target/cortex_m: workaround Cortex-M7 erratum 3092511Tomas Vanek3-2/+84
When an asynchronous exception occurs at the same time as a breakpoint event (either hardware breakpoint or software breakpoint), it is possible for the processor to halt at the beginning of the exception handler instead of the instruction address pointed by the breakpoint. During debug entry in exception handler state and with BKPT bit set as the only break reason in DFSR, check if there is a breakpoint, which have triggered the debug halt. If there is no such breakpoint, resume execution. The processor services the interrupt and halts again at the correct breakpoint address. The workaround is not needed during target algo run (debug_execution) because interrupts are disabled in PRIMASK register. Also after single step the workaround resume never takes place: the situation is treated as error. Link: https://developer.arm.com/documentation/SDEN1068427/latest/ Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Change-Id: I8b23f39cedd7dccabe7e7066d616fb972b69f769 Reviewed-on: https://review.openocd.org/c/openocd/+/8332 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Liviu Ionescu
2024-06-25Merge up to ad87fbd1cf28760795c4e18f3318a2d720e5a8a6 from upstreamEvgeniy Naydanov62-843/+1469
Conflicts: * `doc/openocd.texi`: due to d382c95d57c0ad9ed2dcc83c95404babb7647708, resolved by selecting the upstream version. * `src/server/gdb_server.c`: between 944fe66f104e356c5fcd2b5c25200cebef9b389c and 92e8823ebdb6d01b41bb5d79af49501d525acd1d. Resolved by adopting the use of `LOG_TARGET_*`. * `src/target/target.c`: between 639e68a621b7ae8c4a296ca7e45b47075268fded and c5358c84ad0d3e7497498e0457cec7785f72910a, selected the version from `riscv-openocd`. Change-Id: Ic1327f25e147945e0ec82947a82452501e8ee5de
2024-06-25tcl/interface: support for Raspberry Pi 5Tomas Vanek3-12/+51
Make sure raspberrypi-native.cfg cannot be used on RPi5. Add raspberrypi5-gpiod.cfg which uses linuxgpiod adapter driver. Issue a warning if PCIe is in power save mode. While on it, re-format warnings issued from Tcl to look similar to LOG_WARNING() output. Change-Id: If19b0350bd5fff83d9a0c65999e33b161fb6957a Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/8333 Tested-by: jenkins Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2024-06-23Remove other '_s' suffix from structsAntonio Borneo6-16/+16
Most of the work is already done by [1]. Remove few more '_s' suffix and also fix some comment referring to the old name of the struct. Link: https://review.openocd.org/c/openocd/+/8340 Change-Id: Ifddc401c3b05e62ece3aa7926af1e78f0c4a671e Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8341 Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2024-06-23Remove '_s' suffix from structsMarc Schink9-186/+186
Change-Id: I956acce316e60252b317daa41274403d87f704b8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8340 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-23server/gdb: Use LOG_TARGET_xxx() to show target nameMarc Schink1-20/+18
The output "gdb port disabled" is confusing without reference to the target. Use LOG_TARGET_INFO() to output the target name. While at it, use LOG_TARGET_xxx() for all log statements where the target name is already used. Change-Id: I70b134145837db623e008a4a6c0be0008d9a0d87 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/8313 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2024-06-23remote_bitbang: fix assertion failure for the cases when connection is ↵Timur Golubovich1-1/+8
abruptly terminated Changes affect the function remote_bitbang_fill_buf. When read_socket returns 0, socket reached EOF and there is no data to read. But if request was blocking, the caller expected some data. Such situations should be treated as ERROR. Change-Id: I02ed484e61fb776c1625f6e36ab14c85891939b2 Signed-off-by: Timur Golubovich <timur.golubovich@syntacore.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8325 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2024-06-23itm: fix default initializationAntonio Borneo3-12/+16
Commit f9509c92dba3 ("itm: rework itm commands before 'init'") ignores the default enable of ITM channel 0, that is applied when no 'itm port[s]' is issued. Call armv7m_trace_itm_config() unconditionally to handle it. Change-Id: I3e85d0b063ed38c1552f6af9ea9eea2e76aa9025 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reported-by: Paul Fertser <fercerpav@gmail.com> Fixes: f9509c92dba3 ("itm: rework itm commands before 'init'") Reviewed-on: https://review.openocd.org/c/openocd/+/7900 Reviewed-by: <post@frankplowman.com> Tested-by: jenkins
2024-06-23target: aarch64: access reg SPSR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-7/+15
The register SPSR_EL1 is accessible and it's content is relevant only when the target is in EL1 or EL2 or EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd5384000, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $SPSR_EL1 or through OpenOCD command reg SPSR_EL1 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: Ia0f984d52920cc32b8ee31157d62c13dea616a3a Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8276 Tested-by: jenkins
2024-06-23target: aarch64: access reg ESR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-7/+15
The register ESR_EL1 is accessible and it's content is relevant only when the target is in EL1 or EL2 or EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd5385200, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ESR_EL1 or through OpenOCD command reg ESR_EL1 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: Icd65470c279e5cfd03091db6435cdaa1c447644c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8275 Tested-by: jenkins
2024-06-23target: aarch64: access reg ELR_EL1 only in EL1, EL2 and EL3Antonio Borneo1-0/+10
The register ELR_EL1 is accessible and it's content is relevant only when the target is in EL1 or EL2 or EL3. Without this patch, an error: Error: Opcode 0xd5384020, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ELR_EL1 or through OpenOCD command reg ELR_EL1 Detect the EL and return error if the register cannot be accessed. Change-Id: I402dda4cd9dae502b05572fc6c1a8f0edf349bb1 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8274 Tested-by: jenkins
2024-06-23target: aarch64: access reg SPSR_EL2 only in EL2 and EL3Antonio Borneo1-7/+15
The register SPSR_EL2 is accessible and it's content is relevant only when the target is in EL2 or EL3. Virtualization SW in EL1 can also access it, but this either triggers a trap to EL2 or returns SPSR_EL1. Debugger should not mix the real SPSR_EL2 with the virtual register. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $SPSR_EL2 or through OpenOCD command reg SPSR_EL2 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8273 Tested-by: jenkins
2024-06-23target: aarch64: access reg ESR_EL2 only in EL2 and EL3Antonio Borneo1-7/+15
The register ESR_EL2 is accessible and it's content is relevant only when the target is in EL2 or EL3. Virtualization SW in EL1 can also access it, but this either triggers a trap to EL2 or returns ESR_EL1. Debugger should not mix the real ESR_EL2 with the virtual register. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53c5200, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ESR_EL2 or through OpenOCD command reg ESR_EL2 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: Icb32b44886d50907f29b068ce61e4be8bed10208 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8272 Tested-by: jenkins
2024-06-23target: aarch64: access reg ELR_EL2 only in EL2 and EL3Antonio Borneo1-0/+10
The register ELR_EL2 is accessible and it's content is relevant only when the target is in EL2 or EL3. Virtualization SW in EL1 can also access it, but this either triggers a trap to EL2 or returns ELR_EL1. Debugger should not mix the real ELR_EL2 with the virtual register. Without this patch, an error: Error: Opcode 0xd53c4020, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ELR_EL2 or through OpenOCD command reg ELR_EL2 Detect the EL and return error if the register cannot be accessed. Change-Id: Idf02b42a7339df83260c1e44ceabbb05fbf392b9 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8271 Tested-by: jenkins
2024-06-23target: aarch64: access reg SPSR_EL3 only in EL3Antonio Borneo1-7/+15
The register SPSR_EL3 is accessible and it's content is relevant only when the target is in EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53e4000, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $SPSR_EL3 or through OpenOCD command reg SPSR_EL3 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Change-Id: I00849d99feeb96589c426fcafda98127dbd19a67 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8270 Tested-by: jenkins
2024-06-23target: aarch64: access reg ESR_EL3 only in EL3Antonio Borneo1-9/+17
The register ESR_EL3 is accessible and it's content is relevant only when the target is in EL3. Plus, the register is 64 bits wide. Without this patch, an error: Error: Opcode 0xd53e5200, DSCR.ERR=1, DSCR.EL=1 is triggered by GDB register window or through GDB command x/p $ESR_EL3 or through OpenOCD command reg ESR_EL3 Detect the EL and return error if the register cannot be accessed. Handle the register as 64 bits. Drop the FIXME comment on Aarch32 case, as the register exists in Aarch64 only. Change-Id: Ie8c69dc7b50ae81a52506cf151c8e64e15752d0d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8269 Tested-by: jenkins
generated by cgit v1.1 at 2025-09-20 08:26:21 +0000