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2017-06-21Don't set breakpoints on disabled hartsv20170621Palmer Dabbelt1-0/+6
2017-06-21No longer hard-code the non-RTOS hart to 0Palmer Dabbelt1-3/+4
2017-06-21Allow memory writes to proceed on all hartsPalmer Dabbelt1-6/+0
2017-06-21Refactor examine, to avoid some assertionsPalmer Dabbelt1-9/+16
2017-06-21Factor out checking if harts should be usedPalmer Dabbelt3-18/+35
2017-06-20Set current_hartid from coreidPalmer Dabbelt3-7/+5
2017-06-20Merge pull request #68 from riscv/multicorePalmer Dabbelt4-38/+89
2017-06-20Set hardware triggers on all harts.multicoreTim Newsome1-33/+69
2017-06-20Don't immediately segfault with -rtos on v0.11.Tim Newsome1-0/+3
2017-06-20Comment curious code.Tim Newsome1-0/+4
2017-06-20Update list of "threads" when harts are discovered.Tim Newsome3-5/+13
2017-06-20Merge pull request #67 from riscv/cosmeticsTim Newsome3-77/+147
2017-06-19Put early DEBUG notice of XLEN back.Tim Newsome1-0/+5
2017-06-16Update debug_defines. Clarify debug output.Tim Newsome2-52/+118
2017-06-16Fix comment.Tim Newsome1-1/+1
2017-06-16Tell the user about detected harts.Tim Newsome1-8/+10
2017-06-16Tighten up debug output.Tim Newsome1-17/+14
2017-06-16Merge pull request #66 from riscv/whitespaceTim Newsome6-335/+333
2017-06-15Fix indentation to match OpenOCD style.Tim Newsome6-335/+333
2017-06-15Merge pull request #64 from riscv/release-fixesTim Newsome2-5/+12
2017-06-15Merge pull request #65 from riscv/print64Palmer Dabbelt1-4/+7
2017-06-15Fix print statements to work with 64-bit addressesTim Newsome1-4/+7
2017-06-15Jump to the RTOS hartid after haltingPalmer Dabbelt1-0/+7
2017-06-15Clear abstract errors from register_read_directPalmer Dabbelt1-5/+5
2017-06-15Merge pull request #63 from riscv/crc64Palmer Dabbelt1-1/+1
2017-06-15Accept 64-bit addresses in CRC requests.Tim Newsome1-1/+1
2017-06-14Merge pull request #62 from riscv/riscv64Palmer Dabbelt308-10671/+17226
2017-06-13Fix the build.Tim Newsome5-77/+85
2017-06-13Merge branch 'remotes/openocd/master' into riscv64Tim Newsome303-10594/+17141
2017-06-08Merge pull request #60 from riscv/timTim Newsome1-25/+25
2017-06-08Fix dmi_read() indentation; remove \n in LOG_ERRORTim Newsome1-25/+25
2017-06-07riscv: Move the initialization of the field inside the structure for consistencyMegan Wachs1-5/+1
2017-06-07riscv: v13 -- dmi_write must still check for the OP resultv20170608Megan Wachs1-21/+17
2017-06-06%p already includes 0x (on gcc)Tim Newsome1-4/+4
2017-06-06Don't leave fd undefined.Tim Newsome1-1/+1
2017-06-02flash: nor: ath79: fix build failure due to recent MIPS changesPaul Fertser1-37/+35
2017-05-31flash: Add support for Atheros (ath79) SPI interfaceTobias Diedrich6-1/+948
2017-05-31imx_gpio: add mmap based jtag interface for IMX processorsGrzegorz Kostka6-2/+623
2017-05-25Return 5 (SIGBREAK) not 2 (SIGINT) after a stepPalmer Dabbelt1-1/+1
2017-05-25Pass EVENT_RESUMED in the RTOSPalmer Dabbelt1-2/+3
2017-05-25Invalidate the register cache when rtos_hartid==-1Palmer Dabbelt1-1/+4
2017-05-25Invalidate the register cache on step, resume, resetPalmer Dabbelt2-0/+14
2017-05-25Merge pull request #52 from riscv/v11_read_without_intMegan Wachs1-1/+1
2017-05-22riscv-v11: Don't perform unexpected operation in cache_writeMegan Wachs1-1/+1
2017-05-15Check for abstractcs.busy, not just CMDERR_BUSYPalmer Dabbelt1-0/+4
2017-05-15Go back to 32-word read/write buffersPalmer Dabbelt1-2/+2
2017-05-15Don't re-read registers after they're writtenPalmer Dabbelt1-8/+0
2017-05-15Print out the actual CSR that's readPalmer Dabbelt1-0/+1
2017-05-15Build fixesPalmer Dabbelt2-3/+3
2017-05-15riscv: Remove some compile warningsMegan Wachs1-2/+0