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2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs3-5/+19
2018-05-22Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs74-913/+1614
2018-05-22Merge pull request #257 from riscv/commentTim Newsome2-0/+8
Comment riscv_set_register, register_write_direct
2018-05-22Delay trigger enumeration until it's required.Tim Newsome3-5/+19
This improves startup time, which is important when connecting to simulators. One problem is that triggers that are set when the debugger connects are not cleared until enumeration happens. Execution may halt due to a trigger set by a previous debug session, which could confuse the user. If this happens, triggers will be instantly enumerated, so it will only happen once per session. Change-Id: I3396f713f16980a8b74745a1672fe8b8a2d4abae
2018-05-22Merge pull request #260 from dlrobertson/fix_segfaultTim Newsome1-3/+10
Fix posible null deref in get_target_type
2018-05-22Fix posible null deref in get_target_typeDan Robertson1-3/+10
A null deref occurs if riscv_deinit_target is called and the target has not been initialized. Change-Id: Ic34057508ed6686eb48e9fe8220110c42ba2fc5e
2018-05-17Review feedback.Tim Newsome1-1/+1
Change-Id: If58c011fc8d89d329d65a6c624ffb631f111cef2
2018-05-17Comment riscv_set_register, register_write_directTim Newsome2-0/+8
Fixes #241 Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
2018-05-17Merge pull request #251 from riscv/from_upstreamTim Newsome73-910/+1596
From upstream
2018-05-17Merge pull request #255 from riscv/reset-unexpected-checkMegan Wachs1-8/+0
riscv: remove unexpected check during reset
2018-05-16Merge remote-tracking branch 'origin/reset-unexpected-check' into ↵Megan Wachs1-8/+0
riscv-compliance
2018-05-16riscv: remove unexpected check during resetMegan Wachs1-8/+0
I'm not sure what this check is adding, and it causes problems for implementations that take some time to report that they are halted out of reset (e.g. by executing Debug ROM).
2018-05-14Remove FSF address to satisfy checkpatchTim Newsome4-20/+0
It was giving this error: ERROR: Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. OpenOCD already includes a copy of the GPL. Change-Id: Iae50c2b38f1845d826d7d631072c8c3ded8859da
2018-05-14Merge remote-tracking branch 'megan/riscv-compliance' into riscv-complianceMegan Wachs0-0/+0
2018-05-14Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs6-104/+237
2018-05-08blank_check_memory prototype has changed.Tim Newsome1-17/+0
Just remove our nop implementation. The default behavior when this is left NULL does the same thing. Change-Id: I865976c694d24661941584cb0efc92fc26612316
2018-05-08arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
Neither the initial loop to clear dirty registers (which visits all registers starting at R2 and counting upwards) nor the final explicit flushes ensure a write-back in arm_dpm_write_dirty_registers. This change makes sure that both our scratch registers (i.e. R0 and R1) are written back to the target. Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-on: http://openocd.zylin.com/4506 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08doc: fix several typos in openocd.texiAntonio Borneo1-75/+75
Mostly trivial fixes spotted by spell checker One fix s/are/is/ No changes in the content of the document Change-Id: Ic2d8696860c540e901e8c5190f8f1e7dce80545f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4402 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08ChibiOS thread states: Update thread state to label mappingFaisal Shah1-4/+3
Fixed style issue. Removed #define with list of strings, and just put the strings in the array initialization directly. Removed empty space at the start of line. Change-Id: I76580be203d7d69b8c5b5440f820156543e0d5cc Signed-off-by: Faisal Shah <faisal.shah@gmail.com> Reviewed-on: http://openocd.zylin.com/4488 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08psoc6: Run flash algorithm asynchronously to improve performanceBohdan Tymkiv2-142/+236
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .incTomas Vanek16-178/+87
Flash loaders refactored to the new style - use generated .inc instead of hexadecimal machine code in the flash driver source. Change-Id: If65a2099589e210f9450819b467d67819fd841fc Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4439 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08board: add configuration for stm32f103c8 "Blue Pill"Matthias Welwarsky2-1/+23
The "Blue Pill" is a popular development board with an STM32F103C8 micro controller. According to sources, it has a 128kB Flash on board even though the option bytes only report 64kB. This patch therefore also modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into account which the board file sets to 0x20000. Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4495 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08tcl/target: Add Renesas R-Car R8A7790 H2 targetMarek Vasut1-0/+36
Add configuration for the Renesas R-Car R8A7790 H2 target. This is an SoC with four Cortex A15 and four Cortex A7 ARMv7a cores, only the four A15 cores are supported. Change-Id: I6099b257cc0f04e6858ed5f5f8c8d8ad82ef7650 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4490 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08jtag: adapter: fix indentation in handle_interface_commandAntonio Borneo1-8/+8
Minor fix, no code change, just align it to the block it belongs to. Change-Id: I4c3b0d0bd00a55d5109d3723e5c4bfb2fc72e366 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4492 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08target: add Cortex-M4 target to VF6xx targetMatthias Welwarsky1-1/+1
The Vybrid VF6xx SoCs contain an additional Cortex-M4 core connected to AP number 3 of the main DAP. Change-Id: I59c020fdfc53e909b1f0dac1a8627a62cdaa74f2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3640 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08target/cortex_m: allow setting the type of a breakpointTomas Vanek3-32/+5
Cortex-M target used 'auto_bp_type' mode. The requested type of breakpoint was ignored and hard (FPB) breakpoints were set in 'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above 0x20000000. The code memory area of Cortex-M does not mean the memory is flash and vice versa. External flash (parallel or QSPI) is usually mapped above code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis has a RAM block under 0x20000000 boundary. Remove 'auto_bp_type' mode, set breakpoints to requested type. Change 'cortex_m maskisr auto' handling to use a hard temporary breakpoint everywhere: it can also workaround not working soft breakpoints on Cortex-M7 with ICache enabled. Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4429 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08armv8: valgrind memleak fixesMatthias Welwarsky7-9/+74
Various fixes for memory leaks, adds a target cleanup for aarch64 and ARM CTI objects. Change-Id: I2267f0894df655fdf73d70c11ed03df0b8f8d07d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4478 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08target: add configuration for NXP MC-IMX8M-EVKMatthias Welwarsky2-0/+77
includes target configuration for i.MX8M SoC family, board file needs to set up CHIPNAME and CHIPCORES to match the actual hardware configuration Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4434 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08tcl/board: add board configuration for NXP IMX7SABREMatthias Welwarsky1-0/+114
configuration also contains a reset-init procedure that disables the watchdog and initilizes the boards DDR memory so that you can upload baremetal (e.g. boot loader) code into DDR and start it from there. Change-Id: I4d2311b3708a5fcb5174a3447f34ae3904de7243 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4227 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08flash/nor/at91sam: implement flash bank deallocation for SAM seriesTomas Vanek4-53/+61
Microchip (former Atmel) SAM drivers allocate a struct per chip. at91sam3, at91sam34: Deallocate all chip structs from the list at once, on the first bank deallocation. at91samd and at91sam4l drivers do not handle more than one bank. Convert them to simple driver_priv allocation and use default_flash_free_driver_priv(). Change-Id: I49d7200f38a4568c7e12f306c27d1b1b72646736 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4416 Tested-by: jenkins
2018-05-08flash/nor/kinetis: implement flash bank deallocationTomas Vanek1-1/+18
Change-Id: I8ef80eae646d3b3eb7f6dd42067f8516adc5abef Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4415 Tested-by: jenkins
2018-05-08flash/nor: handle flash write alignment/padding in the infrastructureTomas Vanek3-121/+312
Most of flash drivers have to ensure proper flash write block alignment and padding. As there was no support for it in the flash infrastructure, each driver does it its own way. Sometimes this part of code is not properly tested and contains bugs. flash_write(_unlock) joins all image sections targeted to one flash bank using padded areas as a glue. This solves alignment problems on section boundaries but imposes other problems. Introduce new flash bank parameters write_start_alignment, write_end_alignment and minimal_write_gap. New flash drivers can just properly set these values instead of handling alignment by its own. Adapt infrastructure (namely flash_write_unlock(), handle_flash_fill_command() and handle_flash_write_bank_command()) to prepare write data padded to an alignment required by the flash bank. Rework flash_write_unlock() to discontinue write block when the gap between sections is bigger than minimum specified in minimal_write_gap. minimal_write_gap is set to one sector by default. Change-Id: I4368dd402dfaf51c193bcbf1332cffff092b239b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4399 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-05-08target armv7m: multi-block erase checkTomas Vanek6-98/+137
Tested on PSoC6 (Cortex-M0+ core), onboard KitProg2 in CMSIS-DAP mode, adapter_khz=1000. Plain read: flash read_bank 0 /dev/null takes 48 seconds. erase_check without this change: flash erase_check 0 takes horrible 149 seconds!! And the same command with the change applied takes 1.8 seconds. Quite a difference. Remove the erase-value=0 version of algorithm as the new one can check for any value. If the target is an insane slow clocked CPU (under 1MHz) algo timeouts. Blocks checked so far are returned and the next call uses increased timeout. Change-Id: Ic0899011256d2114112e67c0b51fab4f6230d9cd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4298 Tested-by: jenkins Reviewed-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-05-08target, flash: prepare infrastructure for multi-block blank checkTomas Vanek12-95/+82
'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
2018-05-08tcl/target: Add Renesas R-Car R8A7791 M2W targetNiklas Söderlund1-0/+27
Add configuration for the Renesas R-Car R8A7791 M2W target. This is an SoC with two Cortex A15 ARMv7a cores, both cores are supported. This patch is based on initial submission by Adam Bass and improvements by Niklas Söderlund. Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Adam Bass <adam.bass@renesas.com> Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se> Reviewed-on: http://openocd.zylin.com/4485 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08HACKING: document practices to improve code qualityPaul Fertser1-4/+50
Change-Id: I58a7d978b7d5bca3037c4535f06746b9f4411950 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4343 Tested-by: jenkins
2018-05-08configure: disable all drivers when zy1000 is enabledPaul Fertser2-4/+4
This also fixes the transport_is_hla FIXME. Change-Id: I33960f373f11e3e203f9aed9c6d02bf7ca48ac97 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4473 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08gdb_server: gdb_memory_map() reworkTomas Vanek1-17/+21
Use sector sizes instead of bank size. Detect a gap between sectors and emit xml blocks accordingly. Detect sector overflow over the bank size. Change-Id: If0e0e44b0c3b93067b4d717c9c7b07c08582e57b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4436 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08rtos: Fix XPSR_OFFSET for cortex_m4f stackingArmin van der Togt1-2/+21
Structures rtos_standard_Cortex_M4F_stacking and rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c where using rtos_standard_Cortex_M3_stack_align for the stack-align function. This function calls rtos_Cortex_M_stack_align with XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for cortex-M4F and cortex-M4F with fpu. This patch adds stack_align functions for M4F an M4F_FPU Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47 Signed-off-by: Armin van der Togt <armin@otheruse.nl> Reviewed-on: http://openocd.zylin.com/4037 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08target: free target SMP list on shutdownMatthias Welwarsky1-0/+12
On SMP targets, the "target smp" command creates a list of targets that belong to the SMP cluster. Free this list when a target gets destroyed on shutdown. For simplicity, the complete list is free'd as soon as the first target of the SMP cluster is destroyed instead of individually removing targets from the list. Change-Id: Ie217ae1efb2e819c288ff3b1155aeaf0a19b06be Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4481 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-05-08target/arm_adi_v5: extend apcsw command to accept arbitrary bitsTomas Vanek4-21/+75
apcsw command was limited to SPROT bit only. Now user can manipulate any bit except size and addrinc fields. Can be used e.g. to set bus signal 'cacheable' on Cortex-M7 Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4431 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bitMatthias Welwarsky5-10/+38
The CTRL/STAT register in the ARM DAP DP has a debug power up ack bit and a system power up ack bit. Some devices do not set the system power up ack bit until sometime later. To avoid having the initial target examination fail due to this or to have a sticky bit error report claim power failure due to this a user can now specify that this bit should be ignored. Change-Id: I2451234bbe904984e29562ef6f616cc6d6f60732 Signed-off-by: Eric Katzfey <eric.katzfey@mentalbee.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3710 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-05-08Merge pull request #248 from riscv/fix_011Megan Wachs1-1/+1
Don't error if hart select isn't implemented.
2018-05-07Don't error if hart select isn't implemented.Tim Newsome1-1/+1
It's not implemented for 0.11 because we don't need it. Returning error caused 0.11 targets to not be debuggable since change 848062d0d11679de25be573981df45e2c4880db8. Change-Id: I8b04a1fcf3c3e8bf8340cbf39aaf475d2a213519
2018-05-07Merge pull request #236 from riscv/optimizeTim Newsome1-25/+69
Small speed improvements.
2018-05-03Conform to OpenOCD styleTim Newsome1-2/+1
Change-Id: I3954a8ac254b460560fa1414c5921777e4005645
2018-05-03Merge branch 'riscv' into optimizeTim Newsome221-1855/+8790
Change-Id: I2693eb05dee72acd2df5d8594c51e9da08ea1cc6
2018-05-03counter*h registers only exist on RV32Tim Newsome1-0/+66
Fixes #245. Change-Id: If05ec9773dc9975931434f09c431eba122a6e8d0
2018-05-01Merge pull request #246 from darius-bluespec/sysbus-bugfixTim Newsome1-1/+3
Bug fixes for system bus access
2018-05-01Merge pull request #226 from riscv/notice_resetTim Newsome5-178/+242
Notice when a hart is reset while it's being debugged, and let the user know that it happened
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