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2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs3-5/+19
2018-05-22Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs74-913/+1614
2018-05-22Merge pull request #257 from riscv/commentTim Newsome2-0/+8
2018-05-22Delay trigger enumeration until it's required.Tim Newsome3-5/+19
2018-05-22Merge pull request #260 from dlrobertson/fix_segfaultTim Newsome1-3/+10
2018-05-22Fix posible null deref in get_target_typeDan Robertson1-3/+10
2018-05-17Review feedback.Tim Newsome1-1/+1
2018-05-17Comment riscv_set_register, register_write_directTim Newsome2-0/+8
2018-05-17Merge pull request #251 from riscv/from_upstreamTim Newsome73-910/+1596
2018-05-17Merge pull request #255 from riscv/reset-unexpected-checkMegan Wachs1-8/+0
2018-05-16Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compl...Megan Wachs1-8/+0
2018-05-16riscv: remove unexpected check during resetMegan Wachs1-8/+0
2018-05-14Remove FSF address to satisfy checkpatchTim Newsome4-20/+0
2018-05-14Merge remote-tracking branch 'megan/riscv-compliance' into riscv-complianceMegan Wachs0-0/+0
2018-05-14Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs6-104/+237
2018-05-08blank_check_memory prototype has changed.Tim Newsome1-17/+0
2018-05-08arm_dpm: flush both scratch registers (R0 and R1)Philipp Tomsich1-5/+7
2018-05-08doc: fix several typos in openocd.texiAntonio Borneo1-75/+75
2018-05-08ChibiOS thread states: Update thread state to label mappingFaisal Shah1-4/+3
2018-05-08psoc6: Run flash algorithm asynchronously to improve performanceBohdan Tymkiv2-142/+236
2018-05-08flash/nor, contrib/loaders: add stm32 loaders Makefile and generated .incTomas Vanek16-178/+87
2018-05-08board: add configuration for stm32f103c8 "Blue Pill"Matthias Welwarsky2-1/+23
2018-05-08tcl/target: Add Renesas R-Car R8A7790 H2 targetMarek Vasut1-0/+36
2018-05-08jtag: adapter: fix indentation in handle_interface_commandAntonio Borneo1-8/+8
2018-05-08target: add Cortex-M4 target to VF6xx targetMatthias Welwarsky1-1/+1
2018-05-08target/cortex_m: allow setting the type of a breakpointTomas Vanek3-32/+5
2018-05-08armv8: valgrind memleak fixesMatthias Welwarsky7-9/+74
2018-05-08target: add configuration for NXP MC-IMX8M-EVKMatthias Welwarsky2-0/+77
2018-05-08tcl/board: add board configuration for NXP IMX7SABREMatthias Welwarsky1-0/+114
2018-05-08flash/nor/at91sam: implement flash bank deallocation for SAM seriesTomas Vanek4-53/+61
2018-05-08flash/nor/kinetis: implement flash bank deallocationTomas Vanek1-1/+18
2018-05-08flash/nor: handle flash write alignment/padding in the infrastructureTomas Vanek3-121/+312
2018-05-08target armv7m: multi-block erase checkTomas Vanek6-98/+137
2018-05-08target, flash: prepare infrastructure for multi-block blank checkTomas Vanek12-95/+82
2018-05-08tcl/target: Add Renesas R-Car R8A7791 M2W targetNiklas Söderlund1-0/+27
2018-05-08HACKING: document practices to improve code qualityPaul Fertser1-4/+50
2018-05-08configure: disable all drivers when zy1000 is enabledPaul Fertser2-4/+4
2018-05-08gdb_server: gdb_memory_map() reworkTomas Vanek1-17/+21
2018-05-08rtos: Fix XPSR_OFFSET for cortex_m4f stackingArmin van der Togt1-2/+21
2018-05-08target: free target SMP list on shutdownMatthias Welwarsky1-0/+12
2018-05-08target/arm_adi_v5: extend apcsw command to accept arbitrary bitsTomas Vanek4-21/+75
2018-05-08arm_adi_v5: Add ability to ignore the CSYSPWRUPACK bitMatthias Welwarsky5-10/+38
2018-05-08Merge pull request #248 from riscv/fix_011Megan Wachs1-1/+1
2018-05-07Don't error if hart select isn't implemented.Tim Newsome1-1/+1
2018-05-07Merge pull request #236 from riscv/optimizeTim Newsome1-25/+69
2018-05-03Conform to OpenOCD styleTim Newsome1-2/+1
2018-05-03Merge branch 'riscv' into optimizeTim Newsome221-1855/+8790
2018-05-03counter*h registers only exist on RV32Tim Newsome1-0/+66
2018-05-01Merge pull request #246 from darius-bluespec/sysbus-bugfixTim Newsome1-1/+3
2018-05-01Merge pull request #226 from riscv/notice_resetTim Newsome5-178/+242
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