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2017-06-12Jump to the RTOS hartid after haltingv20170612releasePalmer Dabbelt1-0/+7
2017-06-12Clear abstract errors from register_read_directPalmer Dabbelt1-5/+5
2017-06-07riscv: v13 -- dmi_write must still check for the OP resultv20170608Megan Wachs1-21/+17
2017-06-06%p already includes 0x (on gcc)Tim Newsome1-4/+4
2017-06-06Don't leave fd undefined.Tim Newsome1-1/+1
2017-05-25Return 5 (SIGBREAK) not 2 (SIGINT) after a stepPalmer Dabbelt1-1/+1
2017-05-25Pass EVENT_RESUMED in the RTOSPalmer Dabbelt1-2/+3
2017-05-25Invalidate the register cache when rtos_hartid==-1Palmer Dabbelt1-1/+4
2017-05-25Invalidate the register cache on step, resume, resetPalmer Dabbelt2-0/+14
2017-05-25Merge pull request #52 from riscv/v11_read_without_intMegan Wachs1-1/+1
2017-05-22riscv-v11: Don't perform unexpected operation in cache_writeMegan Wachs1-1/+1
2017-05-15Check for abstractcs.busy, not just CMDERR_BUSYPalmer Dabbelt1-0/+4
2017-05-15Go back to 32-word read/write buffersPalmer Dabbelt1-2/+2
2017-05-15Don't re-read registers after they're writtenPalmer Dabbelt1-8/+0
2017-05-15Print out the actual CSR that's readPalmer Dabbelt1-0/+1
2017-05-15Build fixesPalmer Dabbelt2-3/+3
2017-05-15riscv: Remove some compile warningsMegan Wachs1-2/+0
2017-05-11Shim back in some old interfaces for nowPalmer Dabbelt1-16/+72
2017-05-09Allow all harts to be resetPalmer Dabbelt3-39/+112
2017-05-05 Avoid accessing null target->reg_cacheMegan Wachs1-0/+6
2017-05-05Merge pull request #43 from riscv/read-from-0Megan Wachs1-4/+4
2017-05-01riscv-013: more consistent parensMegan Wachs1-2/+2
2017-05-01riscv-013: Correct sign extension of address on read_memory for lower bits as...Megan Wachs1-1/+1
2017-05-01riscv-013: Correct sign extension of address on read_memoryMegan Wachs1-2/+2
2017-05-01Correct debugging print in read_memoryMegan Wachs1-1/+1
2017-05-01Fix an assertion when reading from 0Palmer Dabbelt1-1/+1
2017-05-01Correct previous hart caching logicPalmer Dabbelt1-1/+2
2017-04-27Clean up unused read_memory codePalmer Dabbelt1-31/+0
2017-04-26Correct an off-by-one in argument parsingPalmer Dabbelt1-1/+1
2017-04-26Keep calling the old poll on v0.11 targetsPalmer Dabbelt1-2/+11
2017-04-26Initialize all registers in examinePalmer Dabbelt1-0/+3
2017-04-26riscv: Fix some blocking compile warningsMegan Wachs2-5/+7
2017-04-26fespi: Allow the ctrl_base address specified as a parameterMegan Wachs1-14/+25
2017-04-26Add 64-bit and multihart supportPalmer Dabbelt22-1451/+3210
2017-04-10Properly consider 'reset halt' and do halt or resume as neededMegan Wachs1-3/+30
2017-04-10fespi: Reset may have occurred. Need to set TXWM again. There are probably mo...Megan Wachs1-12/+24
2017-04-10riscv: Implement the assert/deassert reset functions for v13Megan Wachs2-2/+11
2017-04-04Merge pull request #28 from sifive/readmem_autoexecMegan Wachs1-11/+27
2017-04-04riscv: move value read to after autoexec is cleared.Megan Wachs1-8/+15
2017-04-04riscv: Correct the autoexec in read_memMegan Wachs1-4/+13
2017-03-30Merge pull request #23 from sifive/w1-to-clear-cmderrPalmer Dabbelt1-9/+5
2017-03-30riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.Megan Wachs1-9/+5
2017-03-23Revert "(WIP) Force algorithms to 64 bit"Palmer Dabbelt1-2/+2
2017-03-23(WIP) Force algorithms to 64 bitPalmer Dabbelt1-2/+2
2017-03-23some devicePalmer Dabbelt1-0/+1
2017-03-23Don't set abstractauto at the startPalmer Dabbelt1-1/+2
2017-03-22Merge pull request #21 from sifive/read_memory_retryPalmer Dabbelt1-66/+75
2017-03-22Merge remote-tracking branch 'origin/riscv' into read_memory_retryMegan Wachs0-0/+0
2017-03-22riscv: Retry failed memory readsMegan Wachs1-65/+75
2017-03-22Turn off autoexec after read_memory()Palmer Dabbelt1-0/+1