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2023-02-21More descriptive names for some stepsregression_test_janmat_experimJan Matyas1-5/+5
Change-Id: I38cd396e578e840e5b3e8dd96f8b2674d8d05498 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Fixed typo in package nameJan Matyas1-1/+1
Change-Id: Ie2169e5a38e56bb56b44036c911344a1db5adbf8 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Fixed path to the test logsJan Matyas1-1/+1
Change-Id: I420d736a793ea6225cd643a4adefe999efaaadcd Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Packages must be installed always, regardless of cacheJan Matyas1-6/+5
Change-Id: Ib9bd4b689013cf43624898f4f673ed17aa4f1167 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Add step to archive test logs as an artifactJan Matyas1-0/+8
Change-Id: I219820c33d3b3ebf73d44083ec66e3b8200d4f97 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Empty commit to just re-run the CI and see the cache speedup.Jan Matyas0-0/+0
Change-Id: Ibb40468b9c5cb850959d7b1006687caf16a5c7c4
2023-02-21Included toolchain URL into the cache keyJan Matyas1-3/+4
Change-Id: Icabdd7bee4e92b33989813f3d95905e66dc11be0 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Fixed cache keyJan Matyas1-1/+1
Change-Id: Ifc8fa2ada75da9987c4a4f844f8842c549ef8bae Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Changed 'apt' to 'apt-get' to supress a warning.Jan Matyas1-2/+2
Change-Id: I4bc1d8ec09a323272764b9a09e7473866c1eee92 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Added apt update. Added mising 'cd'.Jan Matyas1-1/+3
Change-Id: I9b57365994c77b2adfe68c3d0b7c32ee990123b1 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Added mkdir /opt/riscvJan Matyas1-1/+3
Change-Id: Ifa01513b73c449be09c5d8cf54f4cd11516db804 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Fixed tar command syntaxJan Matyas1-1/+1
Change-Id: I5cdd3dd018481fe94e1f9a549cfac45fbff46fc9 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Added cache key. Fixed spike rev.Jan Matyas1-7/+11
Change-Id: Ia2715f78dbb3be1bdf0b5ac0936f6320eaa98b73 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-21Several tweaks and experiments with Gitlab CIJan Matyas1-31/+42
- made the runner name explicit (ubuntu-22.04 instead of ubuntu-latest) - use checkout action v3 (not v2) - silences a Github warning - attempted to cache dependencies - reordered the actions a bit so that the cached items are handled first - installed all dependencies to /opt/riscv so that they can be cached more easily as a bulk Change-Id: Icc9c31b20d6302ca378cfafb4f7b283b6e481520 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-17Smoke test OpenOCD against spike.Tim Newsome1-0/+76
Choosing to grab the latest version of each component. I'd rather deal with the rare failure that causes, than realize that we've been testing against really old stuff. Change-Id: I17321d70e2b54086e8f3fbb01744746633d7a119 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-16Merge pull request #799 from riscv/icountTim Newsome2-17/+146
Add `riscv icount` command.
2023-02-15target/riscv: hide_csrs configuration option (#787)Anatoly Parshintsev3-0/+65
* target/riscv: hide_csrs configuration option This option allows users to mark certain CSRs as hidden so they could be expluded from *reg* output and target.xml Change-Id: Iddf8456cd3901f572f8590329ebba5229974d24a * Update doc/openocd.texi Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> --------- Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2023-02-15Add command "exec_progbuf" (#795)Jan Matyas4-9/+98
* Add command "exec_progbuf" Command "exec_progbuf" allows to execute a user-specified sequence of instructions using the program buffer. Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98 Signed-off-by: Jan Matyas <jan.matyas@codasip.com> * Updated the doc: - Minor reword and reorder of the sentences. - Added information about C-instructions in progbuf. - Fixed a typo (per the review). - Added examples. Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7 Signed-off-by: Jan Matyas <jan.matyas@codasip.com> * Cosmetic changes Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f Signed-off-by: Jan Matyas <jan.matyas@codasip.com> --------- Signed-off-by: Jan Matyas <jan.matyas@codasip.com> Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
2023-02-15Merge pull request #796 from Du-Chao/freertos_logTim Newsome1-1/+1
Improve a debug log in freertos_update_threads()
2023-02-15Clarify that RISC-V triggers are optional.Tim Newsome1-2/+3
Change-Id: I3a1f5a30385969964351b6ccadf09a3796d34d6b Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-15Add `riscv icount` command.Tim Newsome2-15/+143
Also refactor shared code for clearing itrigger/etrigger/icount. Change-Id: Iac2e756332c89d2ed43435391e3c097abc825255 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-14Merge pull request #794 from riscv/fix-fence-instructionTim Newsome4-7/+8
Fix opcode for the "fence" instruction
2023-02-10Merge pull request #797 from riscv/Zve32Tim Newsome3-39/+65
If XLEN=64 and vsew=64 fails, fall back to vsew=32.
2023-02-10Don't reuse a single riscv_program.Tim Newsome1-5/+7
Because riscv_program_exec() tries to add an instruction every time through. This would cause an error accessing vector registers where VL > 14(?). Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10If XLEN=64 and vsew=64 fails, fall back to vsew=32.Tim Newsome3-27/+51
This should make vector accesses work on 64-bit harts that implement Zve32*. There doesn't appear to be any way to easily determine what vsew values are allowed, so try and notice the failure. Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-02-10Merge pull request #798 from aap-sc/aap-sc/mcounteren_fixupTim Newsome1-0/+3
CSR_MCOUNTEREN should not exist if U-mode is not supported
2023-02-10CSR_MCOUNTEREN should not exist if U-mode is not supportedParshintsev Anatoly1-0/+3
Change-Id: I1a2420fb88bd3ee37f6a539992e8dc119fdd6e0e
2023-02-08Print out debug value after the assignment is made.Tim Newsome1-1/+1
Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
2023-02-08Move yes_no_maybe_t into riscv.h.Tim Newsome2-6/+6
Change-Id: I5bbdc1af3147e05e25612bf496f409111248c979
2023-02-08Improve a debug log in freertos_update_threads()duchao1-1/+1
To make the log more accurate and comprehensible. In case the offset is non-zero. Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-02-01Fix opcode for the "fence" instructionJan Matyas4-7/+8
OpenOCD currently uses improper "fence" instruction: "FENCE" opcode with empty predecessor and successor sets. Such instruction has no effect and is reserved for future use as a HINT instruction (RISC-V Unprivileged ISA spec V20191213, section 2.9). This patch fixes it by using the proper "fence rw,rw" instruction. Change-Id: Ia2a66059009153efef27279410850ddfd73dae38 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-01-18Merge pull request #786 from aap-sc/aap-sc/vcsr_supportTim Newsome3-0/+3
target/riscv: added support for missing VCSR register
2023-01-10target/riscv: added support for missing VCSR registerParshintsev Anatoly3-0/+3
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
2023-01-04Merge pull request #777 from riscv/itriggerTim Newsome3-22/+326
target/riscv: Add `riscv` `itrigger` and `etrigger` commands.
2023-01-03target/riscv: Remove `riscv test_sba_config_reg` command. (#780)Tim Newsome3-404/+0
This command is supposed to be a start at a compliance test for system bus access. It doesn't pass against spike because it doesn't handle all cases where the interface might be busy. It's not documented. As far as I know nobody uses it. So delete 400 lines of code instead of trying to fix it. Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03target/riscv: Use unsigned int for trigger indexes.Tim Newsome1-7/+12
Change-Id: I1f7cf3a5c8b86f3d6825f45a67ff05822ea67d28 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03target/riscv: Read back tdata2 in set_trigger()Tim Newsome1-4/+14
Change-Id: I2a9271c66565a4c93de3322e14be8b75577ed1b6 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02target/riscv: Add `riscv etrigger` command.Tim Newsome3-0/+133
Change-Id: I7982231c5067b82e4ddb2999bca51dba06ccac7a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02target/riscv: Add `riscv itrigger` command.Tim Newsome3-7/+163
This lets the user set an itrigger trigger, which doesn't fit in the normal breakpoint abstraction. This implementation only allows control of a single itrigger. Hardware could support more than one, and that may be useful to catch different interrupts in different execution modes. But it would make the code/UI more complex and it feels like an unlikely use case. Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27target/riscv: Use macros for trigger types.Tim Newsome1-6/+6
Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27flash: fix clang static analyzer build errors (#778)Tim Newsome2-5/+0
Fixes "variable set but not used" errors. Tested with Homebrew clang version 13.0.1 Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ia90baf5b4857db2b5569ebe6adbbb832de772aad Reviewed-on: https://review.openocd.org/c/openocd/+/6971 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Co-authored-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-12-02riscv/run_algorithm : Add support for memory parameters (#773)Dolu19901-5/+27
* riscv/run_algorithm : Add support for memory parameters Change-Id: I5045a3843dcd96edb0cf8cc54bbd41969e3260a6 Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> * riscv/run_algorithm : better parameter handeling Change-Id: If3da8b83f784ef7b13ca83e98bc629e2219cc632 Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> * riscv/run_algorithm : Better mem param error reporting Change-Id: I09f99ca117f7e5373b23cad0f69d9d5b2a77e61d Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
2022-11-30Merge pull request #772 from riscv/resume_stateTim Newsome1-2/+14
target/riscv: Set target->state in riscv013_halt_go()
2022-11-29target/riscv: Set target->state in riscv013_halt_go()Tim Newsome1-2/+14
Then also set it when we resume in examine(), which doesn't use the full abstractions because not all required data structures are filled out yet. Hopefully fixes #749. Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-25Merge pull request #767 from riscv/unavailableTim Newsome6-172/+303
Handle harts becoming unavailable while they're being debugged.
2022-11-23target/riscv: Fix small riscv013_halt_go() bugTim Newsome1-1/+1
Exit the loop when no harts are running, instead of when at least one hart has halted. Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAKTim Newsome3-4/+4
Simple rename to make code slightly more clear. Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23target/riscv: Set correct target->state in riscv013_halt_go()Tim Newsome1-3/+26
It used to set all states to halted, but that's not right for harts that are now unavailable. (It might be possible to call poll() at the right time instead of duplicating some of its code, but I didn't see an easy way to do that. The real requirement is that target->state is set to TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in halt_finish(), because that's what triggers hwthread_update_threads(), which must know about unavailable harts so they can be hidden from gdb. Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22gdb_server: Operate on available targets.Tim Newsome1-16/+40
When SMP is enabled, gdb will always use the first target in the SMP group. That doesn't work when that first target is unavailable, but others in the SMP group are still available. For cases where gdb expects an operation to affect the entire group (run control, memory access), find the first available target in an SMP group and use that. Change-Id: I4bed600da3ac0fdfe4287d8fdd090a58452db501 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22target/riscv: Don't resume unavailable harts.Tim Newsome2-7/+19
Change-Id: I30a2e9ec6c1b99fb92ab1a160ddb63682167c6d8 Signed-off-by: Tim Newsome <tim@sifive.com>
generated by cgit v1.1 at 2024-10-12 11:53:04 +0000