riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-21	More descriptive names for some stepsregression_test_janmat_experim	Jan Matyas	1	-5/+5
2023-02-21	Fixed typo in package name	Jan Matyas	1	-1/+1
2023-02-21	Fixed path to the test logs	Jan Matyas	1	-1/+1
2023-02-21	Packages must be installed always, regardless of cache	Jan Matyas	1	-6/+5
2023-02-21	Add step to archive test logs as an artifact	Jan Matyas	1	-0/+8
2023-02-21	Empty commit to just re-run the CI and see the cache speedup.	Jan Matyas	0	-0/+0
2023-02-21	Included toolchain URL into the cache key	Jan Matyas	1	-3/+4
2023-02-21	Fixed cache key	Jan Matyas	1	-1/+1
2023-02-21	Changed 'apt' to 'apt-get' to supress a warning.	Jan Matyas	1	-2/+2
2023-02-21	Added apt update. Added mising 'cd'.	Jan Matyas	1	-1/+3
2023-02-21	Added mkdir /opt/riscv	Jan Matyas	1	-1/+3
2023-02-21	Fixed tar command syntax	Jan Matyas	1	-1/+1
2023-02-21	Added cache key. Fixed spike rev.	Jan Matyas	1	-7/+11
2023-02-21	Several tweaks and experiments with Gitlab CI	Jan Matyas	1	-31/+42
2023-02-17	Smoke test OpenOCD against spike.	Tim Newsome	1	-0/+76
2023-02-16	Merge pull request #799 from riscv/icount	Tim Newsome	2	-17/+146
2023-02-15	target/riscv: hide_csrs configuration option (#787)	Anatoly Parshintsev	3	-0/+65
2023-02-15	Add command "exec_progbuf" (#795)	Jan Matyas	4	-9/+98
2023-02-15	Merge pull request #796 from Du-Chao/freertos_log	Tim Newsome	1	-1/+1
2023-02-15	Clarify that RISC-V triggers are optional.	Tim Newsome	1	-2/+3
2023-02-15	Add `riscv icount` command.	Tim Newsome	2	-15/+143
2023-02-14	Merge pull request #794 from riscv/fix-fence-instruction	Tim Newsome	4	-7/+8
2023-02-10	Merge pull request #797 from riscv/Zve32	Tim Newsome	3	-39/+65
2023-02-10	Don't reuse a single riscv_program.	Tim Newsome	1	-5/+7
2023-02-10	If XLEN=64 and vsew=64 fails, fall back to vsew=32.	Tim Newsome	3	-27/+51
2023-02-10	Merge pull request #798 from aap-sc/aap-sc/mcounteren_fixup	Tim Newsome	1	-0/+3
2023-02-10	CSR_MCOUNTEREN should not exist if U-mode is not supported	Parshintsev Anatoly	1	-0/+3
2023-02-08	Print out debug value after the assignment is made.	Tim Newsome	1	-1/+1
2023-02-08	Move yes_no_maybe_t into riscv.h.	Tim Newsome	2	-6/+6
2023-02-08	Improve a debug log in freertos_update_threads()	duchao	1	-1/+1
2023-02-01	Fix opcode for the "fence" instruction	Jan Matyas	4	-7/+8
2023-01-18	Merge pull request #786 from aap-sc/aap-sc/vcsr_support	Tim Newsome	3	-0/+3
2023-01-10	target/riscv: added support for missing VCSR register	Parshintsev Anatoly	3	-0/+3
2023-01-04	Merge pull request #777 from riscv/itrigger	Tim Newsome	3	-22/+326
2023-01-03	target/riscv: Remove `riscv test_sba_config_reg` command. (#780)	Tim Newsome	3	-404/+0
2023-01-03	target/riscv: Use unsigned int for trigger indexes.	Tim Newsome	1	-7/+12
2023-01-03	target/riscv: Read back tdata2 in set_trigger()	Tim Newsome	1	-4/+14
2023-01-02	target/riscv: Add `riscv etrigger` command.	Tim Newsome	3	-0/+133
2023-01-02	target/riscv: Add `riscv itrigger` command.	Tim Newsome	3	-7/+163
2022-12-27	target/riscv: Use macros for trigger types.	Tim Newsome	1	-6/+6
2022-12-27	flash: fix clang static analyzer build errors (#778)	Tim Newsome	2	-5/+0
2022-12-02	riscv/run_algorithm : Add support for memory parameters (#773)	Dolu1990	1	-5/+27
2022-11-30	Merge pull request #772 from riscv/resume_state	Tim Newsome	1	-2/+14
2022-11-29	target/riscv: Set target->state in riscv013_halt_go()	Tim Newsome	1	-2/+14
2022-11-25	Merge pull request #767 from riscv/unavailable	Tim Newsome	6	-172/+303
2022-11-23	target/riscv: Fix small riscv013_halt_go() bug	Tim Newsome	1	-1/+1
2022-11-23	target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK	Tim Newsome	3	-4/+4
2022-11-23	target/riscv: Set correct target->state in riscv013_halt_go()	Tim Newsome	1	-3/+26
2022-11-22	gdb_server: Operate on available targets.	Tim Newsome	1	-16/+40
2022-11-22	target/riscv: Don't resume unavailable harts.	Tim Newsome	2	-7/+19