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2018-01-22Fix 2 more bitbang drivers.rbb_cleanupTim Newsome2-10/+17
2018-01-22Update parport to return errors.Tim Newsome1-10/+20
2018-01-22Propagate errors from remote_bitbang; don't exit()Tim Newsome3-92/+146
2018-01-22Format comments to be doxygen style.Tim Newsome1-13/+12
2018-01-22fdopen() for writing and reading.Tim Newsome1-1/+1
2018-01-19Incorporate review feedback from OpenOCD teamTim Newsome1-17/+9
2018-01-17Merge pull request #184 from riscv/cleanupTim Newsome1-9/+0
2018-01-15Remove dead code.Tim Newsome1-9/+0
2018-01-10Merge pull request #172 from riscv/dbus_read_commentMegan Wachs1-1/+6
2018-01-10Merge pull request #178 from riscv/cleanupTim Newsome1-2/+2
2018-01-10Merge pull request #181 from riscv/propagate_errorsTim Newsome6-63/+128
2018-01-09Muck with mstatus to always be able to read FPRsTim Newsome1-1/+13
2018-01-08Propagate register read errors.Tim Newsome6-62/+115
2018-01-05Merge pull request #179 from riscv/multicore_hart_selectionTim Newsome1-4/+12
2018-01-05Merge pull request #173 from riscv/warn_namesTim Newsome2-6/+5
2018-01-05Rename dummy variable to be correct.Tim Newsome1-2/+2
2018-01-05Merge pull request #174 from riscv/delay_infoTim Newsome2-4/+4
2018-01-04Select current hart before reading memory.Tim Newsome1-4/+12
2018-01-04Make delay update messages debug instead of info.Tim Newsome2-4/+4
2018-01-04Add a comment in dbus_readMegan Wachs1-1/+6
2018-01-04Use register names instead of numbers in warningsTim Newsome2-6/+5
2018-01-03Merge pull request #170 from riscv/strtoullTim Newsome1-1/+1
2018-01-02Parse 64-bit CRC addrs even on 32-bit hostsTim Newsome1-1/+1
2018-01-02Merge pull request #169 from riscv/unused_boardsTim Newsome3-96/+0
2017-12-29Remove board files that I shouldn't have addedTim Newsome3-96/+0
2017-12-29Merge pull request #168 from gnu-mcu-eclipse/sifive-cfgv20171231Tim Newsome3-0/+78
2017-12-29add configs for the SiFive boardsLiviu Ionescu3-0/+78
2017-12-28Merge pull request #167 from riscv/sifive_cfgTim Newsome3-0/+96
2017-12-28Merge pull request #165 from riscv/typoTim Newsome1-1/+1
2017-12-28Add config files for SiFive RISC-V hardware.Tim Newsome3-0/+96
2017-12-28Fix typo.Tim Newsome1-1/+1
2017-12-27Merge pull request #163 from riscv/no_abortTim Newsome5-54/+77
2017-12-27Get rid of abort() calls.Tim Newsome5-54/+77
2017-12-27Merge pull request #162 from riscv/no_abortTim Newsome3-34/+62
2017-12-26Propagate error instead of calling abort().Tim Newsome3-34/+62
2017-12-26Merge pull request #161 from riscv/dead_codeTim Newsome2-18/+0
2017-12-26Remove unused code.Tim Newsome2-18/+0
2017-12-26Merge pull request #160 from riscv/styleTim Newsome16-735/+848
2017-12-26Conform to OpenOCD style guide.Tim Newsome16-735/+848
2017-12-26Merge pull request #159 from riscv/updateTim Newsome109-906/+5299
2017-12-22Merge branch 'master' into updateTim Newsome109-906/+5299
2017-12-22Merge pull request #156 from riscv/fespiTim Newsome2-15/+20
2017-12-21Fix flash/run algorithm with new register namesTim Newsome2-5/+8
2017-12-21Make functions static. Free memory.Tim Newsome1-10/+12
2017-12-21Merge pull request #155 from riscv/debug_definesMegan Wachs1-22/+48
2017-12-21Merge pull request #148 from riscv/macbuildMegan Wachs1-1/+1
2017-12-21Update debug_defines to the one used with spike.Tim Newsome1-22/+48
2017-12-21Merge pull request #145 from riscv/rbb_winTim Newsome3-8/+40
2017-12-21Merge pull request #151 from riscv/use_parenTim Newsome1-1/+1
2017-12-21Use parens after if.Tim Newsome1-1/+1