riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-05-09	Work around another race conditionrace	Palmer Dabbelt	1	-0/+1
2017-05-09	Work around a race condition in an old debug spec	Palmer Dabbelt	1	-2/+2
2017-05-09	Allow all harts to be reset	Palmer Dabbelt	3	-39/+112
2017-05-05	Avoid accessing null target->reg_cache	Megan Wachs	1	-0/+6
2017-05-05	Merge pull request #43 from riscv/read-from-0	Megan Wachs	1	-4/+4
2017-05-01	riscv-013: more consistent parens	Megan Wachs	1	-2/+2
2017-05-01	riscv-013: Correct sign extension of address on read_memory for lower bits as...	Megan Wachs	1	-1/+1
2017-05-01	riscv-013: Correct sign extension of address on read_memory	Megan Wachs	1	-2/+2
2017-05-01	Correct debugging print in read_memory	Megan Wachs	1	-1/+1
2017-05-01	Fix an assertion when reading from 0	Palmer Dabbelt	1	-1/+1
2017-05-01	Correct previous hart caching logic	Palmer Dabbelt	1	-1/+2
2017-04-27	Clean up unused read_memory code	Palmer Dabbelt	1	-31/+0
2017-04-26	Correct an off-by-one in argument parsing	Palmer Dabbelt	1	-1/+1
2017-04-26	Keep calling the old poll on v0.11 targets	Palmer Dabbelt	1	-2/+11
2017-04-26	Initialize all registers in examine	Palmer Dabbelt	1	-0/+3
2017-04-26	riscv: Fix some blocking compile warnings	Megan Wachs	2	-5/+7
2017-04-26	fespi: Allow the ctrl_base address specified as a parameter	Megan Wachs	1	-14/+25
2017-04-26	Add 64-bit and multihart support	Palmer Dabbelt	22	-1451/+3210
2017-04-10	Properly consider 'reset halt' and do halt or resume as needed	Megan Wachs	1	-3/+30
2017-04-10	fespi: Reset may have occurred. Need to set TXWM again. There are probably mo...	Megan Wachs	1	-12/+24
2017-04-10	riscv: Implement the assert/deassert reset functions for v13	Megan Wachs	2	-2/+11
2017-04-04	Merge pull request #28 from sifive/readmem_autoexec	Megan Wachs	1	-11/+27
2017-04-04	riscv: move value read to after autoexec is cleared.	Megan Wachs	1	-8/+15
2017-04-04	riscv: Correct the autoexec in read_mem	Megan Wachs	1	-4/+13
2017-03-30	Merge pull request #23 from sifive/w1-to-clear-cmderr	Palmer Dabbelt	1	-9/+5
2017-03-30	riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.	Megan Wachs	1	-9/+5
2017-03-23	Revert "(WIP) Force algorithms to 64 bit"	Palmer Dabbelt	1	-2/+2
2017-03-23	(WIP) Force algorithms to 64 bit	Palmer Dabbelt	1	-2/+2
2017-03-23	some device	Palmer Dabbelt	1	-0/+1
2017-03-23	Don't set abstractauto at the start	Palmer Dabbelt	1	-1/+2
2017-03-22	Merge pull request #21 from sifive/read_memory_retry	Palmer Dabbelt	1	-66/+75
2017-03-22	Merge remote-tracking branch 'origin/riscv' into read_memory_retry	Megan Wachs	0	-0/+0
2017-03-22	riscv: Retry failed memory reads	Megan Wachs	1	-65/+75
2017-03-22	Turn off autoexec after read_memory()	Palmer Dabbelt	1	-0/+1
2017-03-21	riscv: add missing variable declaration.	Megan Wachs	1	-0/+1
2017-03-21	Clear autoexec correctly	Palmer Dabbelt	1	-1/+1
2017-03-21	Wrong autoexec	Palmer Dabbelt	1	-2/+2
2017-03-21	Builds	Palmer Dabbelt	2	-425/+533
2017-03-21	Merge pull request #20 from sifive/delay_after_autoexec	Megan Wachs	1	-3/+10
2017-03-15	riscv-v13: wait for idle in read_memory	Megan Wachs	1	-3/+10
2017-02-27	Remove more cruft.	Tim Newsome	1	-35/+1
2017-02-27	Merge pull request #18 from sifive/halt_correctly	Tim Newsome	1	-2/+4
2017-02-27	riscv: Ensure that hart is halted before attempting to examine it.	Megan Wachs	1	-2/+4
2017-02-25	Remove cruft.	Tim Newsome	1	-47/+11
2017-02-25	Use DCSR constants from the debug spec.	Tim Newsome	1	-170/+21
2017-02-25	Update bits to latest spec.	Tim Newsome	2	-587/+591
2017-02-22	Speed things up by ignoring return values.	Tim Newsome	1	-13/+45
2017-02-21	Optimize memory write code, used in download.	Tim Newsome	1	-92/+216
2017-02-20	Better error checking in memory access.	Tim Newsome	1	-4/+8
2017-02-20	Properly restore s0 and s1 on resume.	Tim Newsome	1	-8/+8