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AgeCommit message (Expand)AuthorFilesLines
2017-04-14stwnewprogramPalmer Dabbelt2-4/+5
2017-04-14memoizePalmer Dabbelt1-6/+28
2017-04-14runs hart0Palmer Dabbelt3-66/+193
2017-04-14read bytePalmer Dabbelt1-4/+4
2017-04-14endianPalmer Dabbelt1-3/+8
2017-04-14regaddrPalmer Dabbelt1-2/+2
2017-04-14fence.iPalmer Dabbelt1-0/+6
2017-04-14unhaltPalmer Dabbelt1-0/+2
2017-04-14laterPalmer Dabbelt3-47/+70
2017-04-13off by onePalmer Dabbelt1-2/+2
2017-04-13Fix a buffer overflowPalmer Dabbelt4-12/+36
2017-04-13Check for stepPalmer Dabbelt1-0/+4
2017-04-13Replace the 0.13-specific "program_t" with a generic onePalmer Dabbelt10-508/+982
2017-04-10Remove Off By 1 FIXME because HW is fixedmwachs51-3/+1
2017-04-07Implement the "vCont" GDB packetPalmer Dabbelt7-13/+74
2017-04-07typo in commentMegan Wachs1-1/+1
2017-04-07Determine the trigger count dynamicallyPalmer Dabbelt3-9/+39
2017-04-07Determine the hart count dynamicallyPalmer Dabbelt4-1/+24
2017-04-06Call riscv_xlen() to support 32-bit FESPI targetsPalmer Dabbelt1-4/+6
2017-04-06Add a RISC-V RTOS, which natievly supports multiple hartsPalmer Dabbelt11-948/+1396
2017-04-04Merge pull request #28 from sifive/readmem_autoexecMegan Wachs1-11/+27
2017-04-04riscv: move value read to after autoexec is cleared.Megan Wachs1-8/+15
2017-04-04riscv: Correct the autoexec in read_memMegan Wachs1-4/+13
2017-03-30Merge pull request #23 from sifive/w1-to-clear-cmderrPalmer Dabbelt1-9/+5
2017-03-30riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.Megan Wachs1-9/+5
2017-03-23Revert "(WIP) Force algorithms to 64 bit"Palmer Dabbelt1-2/+2
2017-03-23(WIP) Force algorithms to 64 bitPalmer Dabbelt1-2/+2
2017-03-23some devicePalmer Dabbelt1-0/+1
2017-03-23Don't set abstractauto at the startPalmer Dabbelt1-1/+2
2017-03-22Merge pull request #21 from sifive/read_memory_retryPalmer Dabbelt1-66/+75
2017-03-22Merge remote-tracking branch 'origin/riscv' into read_memory_retryMegan Wachs0-0/+0
2017-03-22riscv: Retry failed memory readsMegan Wachs1-65/+75
2017-03-22Turn off autoexec after read_memory()Palmer Dabbelt1-0/+1
2017-03-21riscv: add missing variable declaration.Megan Wachs1-0/+1
2017-03-21Clear autoexec correctlyPalmer Dabbelt1-1/+1
2017-03-21Wrong autoexecPalmer Dabbelt1-2/+2
2017-03-21BuildsPalmer Dabbelt2-425/+533
2017-03-21Merge pull request #20 from sifive/delay_after_autoexecMegan Wachs1-3/+10
2017-03-15riscv-v13: wait for idle in read_memoryMegan Wachs1-3/+10
2017-02-27Remove more cruft.Tim Newsome1-35/+1
2017-02-27Merge pull request #18 from sifive/halt_correctlyTim Newsome1-2/+4
2017-02-27riscv: Ensure that hart is halted before attempting to examine it.Megan Wachs1-2/+4
2017-02-25Remove cruft.Tim Newsome1-47/+11
2017-02-25Use DCSR constants from the debug spec.Tim Newsome1-170/+21
2017-02-25Update bits to latest spec.Tim Newsome2-587/+591
2017-02-22Speed things up by ignoring return values.Tim Newsome1-13/+45
2017-02-21Optimize memory write code, used in download.Tim Newsome1-92/+216
2017-02-20Better error checking in memory access.Tim Newsome1-4/+8
2017-02-20Properly restore s0 and s1 on resume.Tim Newsome1-8/+8
2017-02-17Fix access FPU registers again.Tim Newsome1-46/+80