riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-09-17	Update mpsse.cmpsse_flush	Megan Wachs	1	-0/+1
2018-09-12	Add wall clock timeout to mpsse_flush()	Tim Newsome	1	-0/+6
2018-09-06	Don't report exact watchpoint to gdb. (#300)	Tim Newsome	1	-1/+5
2018-09-04	Merge pull request #235 from rmac-sifive/sba_tests	Ryan Macdonald	3	-9/+413
2018-08-31	More style fixes	Ryan Macdonald	1	-1/+1
2018-08-31	Style fixes	Ryan Macdonald	1	-5/+4
2018-08-31	Add pass message for SBA and compliance tests	Ryan Macdonald	1	-14/+42
2018-08-31	Merge remote-tracking branch 'origin/riscv' into sba_testssba_tests	Megan Wachs	53	-10/+13337
2018-08-30	Merge pull request #298 from riscv/jimtcl-mirror	Andrew Waterman	48	-8/+12849
2018-08-30	Merge pull request #137 from riscv/riscv-compliance	Megan Wachs	5	-2/+490
2018-08-30	riscv-compliance: fix comment typoriscv-compliance	Megan Wachs	1	-1/+1
2018-08-30	Exclude submodules from code style check.	Tim Newsome	1	-1/+3
2018-08-30	riscv-compliance: fix whitespace	Megan Wachs	1	-25/+25
2018-08-30	riscv-compliance: incorporate review feedback	Megan Wachs	1	-123/+108
2018-08-29	Flatten libjaylink submodule	Andrew Waterman	42	-3/+11697
2018-08-29	Flatten git2cl submodule	Andrew Waterman	6	-3/+1148
2018-08-29	Fix typo.	Tim Newsome	1	-1/+1
2018-08-29	Fix strange merge.	Tim Newsome	1	-2/+0
2018-08-29	Merge branch 'riscv' into sba_tests	Tim Newsome	387	-4435/+33234
2018-08-29	Merge remote-tracking branch 'origin/riscv' into riscv-compliance-rebase	Megan Wachs	189	-1706/+22858
2018-08-29	Use official mirror of jimtcl	Megan Wachs	1	-1/+1
2018-08-29	Add command to expose custom registers (#293)	Tim Newsome	4	-42/+148
2018-08-28	Fix gdb_signal_reply() allocating too small buffer (#296)	Tim Newsome	1	-2/+2
2018-08-27	Match on qC, but not qCRC. (#294)	Tim Newsome	1	-1/+1
2018-08-27	Handle hardware watchpoints hit by RV32 loads and stores (#291)	craigblackmore	3	-1/+86
2018-08-27	Handle the qC packet (#292)	craigblackmore	1	-0/+7
2018-08-23	Switch active rtos thread on any hart halt. (#290)	Dmitry Ryzhov	1	-0/+1
2018-08-21	From upstream (#288)	Tim Newsome	0	-0/+0
2018-08-20	From upstream (#286)	Tim Newsome	138	-517/+15329
2018-08-20	Remove unused variable. (#284)	Tim Newsome	1	-2/+0
2018-08-08	Update s25fl256 flash device id, cypress now. (#285)	Ken Zhang	1	-0/+1
2018-08-06	Fix target not halting when GDB jumps to a hardware breakpoint (#283)	craigblackmore	1	-12/+0
2018-07-19	Merge pull request #277 from riscv/fespi_free	Tim Newsome	1	-1/+2
2018-07-18	Merge pull request #282 from riscv/makefile	Tim Newsome	2	-10/+20
2018-07-18	Mimic openrisc Makefile structure	Tim Newsome	2	-10/+20
2018-07-17	Merge pull request #281 from riscv/docs	Tim Newsome	1	-2/+5
2018-07-17	Explain what RISC-V targets are supported.	Tim Newsome	1	-2/+5
2018-07-17	Merge pull request #280 from riscv/docs	Tim Newsome	1	-0/+78
2018-07-17	Merge pull request #275 from riscv/cleanup	Tim Newsome	2	-2/+3
2018-07-17	Merge pull request #279 from riscv/work_area	Tim Newsome	3	-52/+40
2018-07-17	Merge pull request #274 from riscv/comment	Tim Newsome	1	-1/+3
2018-07-16	Document RISC-V commands.	Tim Newsome	1	-0/+78
2018-07-16	Use work area instead of riscv-specific config	Tim Newsome	3	-52/+40
2018-07-12	Define free_driver_priv for fespi flash driver	Tim Newsome	1	-1/+2
2018-06-25	Revert unnecessary change.	Tim Newsome	2	-2/+3
2018-06-20	Explain why reg_cache_values isn't per-hart.	Tim Newsome	1	-1/+3
2018-06-12	Merge pull request #266 from gnu-mcu-eclipse/semihosting	Tim Newsome	5	-0/+270
2018-06-12	target/riscv: fix trailing spaces	Liviu Ionescu	1	-10/+10
2018-06-12	target/riscv: explain why `arm` commands are used	Liviu Ionescu	1	-0/+13
2018-06-12	Merge pull request #267 from riscv/cleanup	Tim Newsome	1	-1/+1