riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-06-21	Don't set breakpoints on disabled hartsv20170621	Palmer Dabbelt	1	-0/+6
2017-06-21	No longer hard-code the non-RTOS hart to 0	Palmer Dabbelt	1	-3/+4
2017-06-21	Allow memory writes to proceed on all harts	Palmer Dabbelt	1	-6/+0
2017-06-21	Refactor examine, to avoid some assertions	Palmer Dabbelt	1	-9/+16
2017-06-21	Factor out checking if harts should be used	Palmer Dabbelt	3	-18/+35
2017-06-20	Set current_hartid from coreid	Palmer Dabbelt	3	-7/+5
2017-06-20	Merge pull request #68 from riscv/multicore	Palmer Dabbelt	4	-38/+89
2017-06-20	Set hardware triggers on all harts.multicore	Tim Newsome	1	-33/+69
2017-06-20	Don't immediately segfault with -rtos on v0.11.	Tim Newsome	1	-0/+3
2017-06-20	Comment curious code.	Tim Newsome	1	-0/+4
2017-06-20	Update list of "threads" when harts are discovered.	Tim Newsome	3	-5/+13
2017-06-20	Merge pull request #67 from riscv/cosmetics	Tim Newsome	3	-77/+147
2017-06-19	Put early DEBUG notice of XLEN back.	Tim Newsome	1	-0/+5
2017-06-16	Update debug_defines. Clarify debug output.	Tim Newsome	2	-52/+118
2017-06-16	Fix comment.	Tim Newsome	1	-1/+1
2017-06-16	Tell the user about detected harts.	Tim Newsome	1	-8/+10
2017-06-16	Tighten up debug output.	Tim Newsome	1	-17/+14
2017-06-16	Merge pull request #66 from riscv/whitespace	Tim Newsome	6	-335/+333
2017-06-15	Fix indentation to match OpenOCD style.	Tim Newsome	6	-335/+333
2017-06-15	Merge pull request #64 from riscv/release-fixes	Tim Newsome	2	-5/+12
2017-06-15	Merge pull request #65 from riscv/print64	Palmer Dabbelt	1	-4/+7
2017-06-15	Fix print statements to work with 64-bit addresses	Tim Newsome	1	-4/+7
2017-06-15	Jump to the RTOS hartid after halting	Palmer Dabbelt	1	-0/+7
2017-06-15	Clear abstract errors from register_read_direct	Palmer Dabbelt	1	-5/+5
2017-06-15	Merge pull request #63 from riscv/crc64	Palmer Dabbelt	1	-1/+1
2017-06-15	Accept 64-bit addresses in CRC requests.	Tim Newsome	1	-1/+1
2017-06-14	Merge pull request #62 from riscv/riscv64	Palmer Dabbelt	308	-10671/+17226
2017-06-13	Fix the build.	Tim Newsome	5	-77/+85
2017-06-13	Merge branch 'remotes/openocd/master' into riscv64	Tim Newsome	303	-10594/+17141
2017-06-08	Merge pull request #60 from riscv/tim	Tim Newsome	1	-25/+25
2017-06-08	Fix dmi_read() indentation; remove \n in LOG_ERROR	Tim Newsome	1	-25/+25
2017-06-07	riscv: Move the initialization of the field inside the structure for consistency	Megan Wachs	1	-5/+1
2017-06-07	riscv: v13 -- dmi_write must still check for the OP resultv20170608	Megan Wachs	1	-21/+17
2017-06-06	%p already includes 0x (on gcc)	Tim Newsome	1	-4/+4
2017-06-06	Don't leave fd undefined.	Tim Newsome	1	-1/+1
2017-06-02	flash: nor: ath79: fix build failure due to recent MIPS changes	Paul Fertser	1	-37/+35
2017-05-31	flash: Add support for Atheros (ath79) SPI interface	Tobias Diedrich	6	-1/+948
2017-05-31	imx_gpio: add mmap based jtag interface for IMX processors	Grzegorz Kostka	6	-2/+623
2017-05-25	Return 5 (SIGBREAK) not 2 (SIGINT) after a step	Palmer Dabbelt	1	-1/+1
2017-05-25	Pass EVENT_RESUMED in the RTOS	Palmer Dabbelt	1	-2/+3
2017-05-25	Invalidate the register cache when rtos_hartid==-1	Palmer Dabbelt	1	-1/+4
2017-05-25	Invalidate the register cache on step, resume, reset	Palmer Dabbelt	2	-0/+14
2017-05-25	Merge pull request #52 from riscv/v11_read_without_int	Megan Wachs	1	-1/+1
2017-05-22	riscv-v11: Don't perform unexpected operation in cache_write	Megan Wachs	1	-1/+1
2017-05-15	Check for abstractcs.busy, not just CMDERR_BUSY	Palmer Dabbelt	1	-0/+4
2017-05-15	Go back to 32-word read/write buffers	Palmer Dabbelt	1	-2/+2
2017-05-15	Don't re-read registers after they're written	Palmer Dabbelt	1	-8/+0
2017-05-15	Print out the actual CSR that's read	Palmer Dabbelt	1	-0/+1
2017-05-15	Build fixes	Palmer Dabbelt	2	-3/+3
2017-05-15	riscv: Remove some compile warnings	Megan Wachs	1	-2/+0