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AgeCommit message (Expand)AuthorFilesLines
2017-09-20set hartid in riscv013_is_halted functioneclipse_multicore_fixGleb Gagarin1-0/+2
2017-09-16Fixes for multicore debug in EclipseGleb Gagarin2-6/+13
2017-08-15Merge pull request #99 from riscv/castv20170818Tim Newsome1-4/+4
2017-08-15Remove some unnecessary casts.Tim Newsome1-4/+4
2017-08-13Merge pull request #94 from riscv/memreadGleb Gagarin1-2/+2
2017-08-13Fix a corner case in block memory read.Tim Newsome1-2/+2
2017-08-13Merge pull request #92 from riscv/FE_402_fixTim Newsome1-1/+4
2017-08-12Force actual read from prog buffer for the last transaction in read_memory()FE_402_fixGleb Gagarin1-2/+5
2017-08-11Fixed off-by-one error in previous commitGleb Gagarin1-1/+1
2017-08-10Merge pull request #90 from riscv/FE_402_fixPalmer Dabbelt1-37/+60
2017-08-10fixed memory leak introduced by previous commitGleb Gagarin1-0/+2
2017-08-10Fix reads beyond requested memory rangeGleb Gagarin1-37/+58
2017-08-09Merge pull request #88 from riscv/read0Palmer Dabbelt1-1/+3
2017-08-09Fix assertion failure when reading from address 0.Tim Newsome1-1/+3
2017-08-08Merge pull request #87 from riscv/gdb_next_portTim Newsome2-2/+9
2017-08-07When gdb_port is 0, don't increment it.gdb_next_portTim Newsome2-2/+9
2017-07-27Merge pull request #86 from riscv/debugTim Newsome2-4/+55
2017-07-27Display register numbers in a more usable format.Tim Newsome2-4/+55
2017-07-26Merge pull request #85 from riscv/print_portTim Newsome1-0/+6
2017-07-25Print out which port OpenOCD is listening on.print_portTim Newsome1-0/+6
2017-07-16Merge pull request #84 from riscv/resetTim Newsome1-2/+23
2017-07-16Use a wall clock timeout to complete reset.Tim Newsome1-5/+9
2017-07-14Fix infinite loop in reset.Tim Newsome1-1/+18
2017-07-13Merge pull request #83 from riscv/triggersTim Newsome4-643/+359
2017-07-12Share trigger code between 0.11 and 0.13 code.Tim Newsome4-643/+359
2017-07-12Merge pull request #82 from riscv/commentTim Newsome1-0/+3
2017-07-12Forgot to commit this follow up to PR #79Tim Newsome1-0/+3
2017-07-12Merge pull request #79 from riscv/abstract_regsTim Newsome1-99/+287
2017-07-12Keep around cmderr for callers to inspect.Tim Newsome1-26/+39
2017-07-12Try abstract register writes as well.Tim Newsome1-55/+133
2017-07-12Try using abstract commands to read registersTim Newsome1-62/+159
2017-07-11Merge pull request #80 from riscv/triggersTim Newsome4-82/+135
2017-07-10Merge pull request #81 from riscv/llp64Palmer Dabbelt1-27/+27
2017-07-10Use LL for 64-bit defines, as Windows is LLP64Palmer Dabbelt1-27/+27
2017-07-10Disable debugger-set triggers on connectTim Newsome4-82/+135
2017-07-06Merge pull request #78 from riscv/build32Tim Newsome2-1/+14
2017-07-06Fix 32-bit build.build32Tim Newsome1-1/+1
2017-07-06Build 32- and 64-bit binaries with Travis.Tim Newsome1-0/+13
2017-07-06Merge pull request #74 from riscv/build32Tim Newsome3-7/+10
2017-07-06Merge pull request #77 from riscv/travisTim Newsome1-0/+5
2017-07-05Perform regular build with travis.Tim Newsome1-0/+5
2017-07-03Merge pull request #73 from riscv/old_triggersTim Newsome1-44/+130
2017-07-03Merge pull request #69 from riscv/multi-gdbPalmer Dabbelt3-43/+66
2017-07-03Merge pull request #72 from dmitryryzhov/examine_restore_temp_regPalmer Dabbelt1-0/+12
2017-07-03Fix 32-bit build errors.Tim Newsome3-7/+10
2017-07-03Fix trigger set/clear bug.Tim Newsome1-2/+2
2017-07-03Add back support for type 1 triggers.old_triggersTim Newsome1-42/+120
2017-07-01Fix comment about saving the temporary register in examine procedure.Dmitry Ryzhov1-2/+6
2017-06-30Restore value of temporary register (s0) in examine OpenOCD procedure in case...Dmitry Ryzhov1-0/+8
2017-06-27Check for errors in read_csr().Tim Newsome1-2/+10
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