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2018-06-25Revert unnecessary change.Tim Newsome2-2/+3
2018-06-20Explain why reg_cache_values isn't per-hart.Tim Newsome1-1/+3
2018-06-12Merge pull request #266 from gnu-mcu-eclipse/semihostingTim Newsome5-0/+270
2018-06-12target/riscv: fix trailing spacesLiviu Ionescu1-10/+10
2018-06-12target/riscv: explain why `arm` commands are usedLiviu Ionescu1-0/+13
2018-06-12Merge pull request #267 from riscv/cleanupTim Newsome1-1/+1
2018-06-12Revert 7927e90a42c4990fbb787b72fa2f049d49f1fdb2Tim Newsome1-1/+1
2018-06-12target/riscv: add semihosting supportLiviu Ionescu5-0/+257
2018-06-11Merge pull request #265 from riscv/cleanupTim Newsome1-11/+0
2018-06-11Merge pull request #264 from riscv/from_upstreamTim Newsome41-823/+6568
2018-06-11Remove dead code.Tim Newsome1-11/+0
2018-06-11Merge branch 'master' into from_upstreamTim Newsome41-823/+6568
2018-06-08Merge pull request #263 from riscv/hartselTim Newsome3-300/+324
2018-06-06Update debug defines to match specTim Newsome3-300/+324
2018-06-06psoc5lp: Add NV Latch flash driverAndreas Färber4-0/+344
2018-06-06flash/nor/psoc5lp: fix bad commit 2d5f2ede55150235352773a976166c3ab68297bcTomas Vanek1-27/+39
2018-06-06drivers: xds110: Remove unnecessary and deprecated libusb function.Edward Fewell1-6/+2
2018-06-06psoc5lp: Add EEPROM flash driverAndreas Färber4-0/+285
2018-06-06flash/nor: Add PSoC 5LP flash driverAndreas Färber6-2/+1036
2018-06-06flash/nor: Add support for TI CC3220SF internal flashEdward Fewell13-54/+804
2018-06-06Fix Semihosting FileIO for targets using vcont packetOmair Javaid1-0/+2
2018-06-06target/target.c: free semihosting memberLiviu Ionescu1-0/+3
2018-06-05Fix libusb-1.0.22 deprecated libusb_set_debug with libusb_set_optionKhem Raj1-1/+4
2018-06-05target/cortex_m: constify some variablesChristopher Head1-4/+4
2018-06-05flash/nor/virtual: copy missing fields from master flash_bank structureBohdan Tymkiv1-0/+5
2018-06-05flash/nor/core: fix double-free crash with 'virtual' flash banksBohdan Tymkiv1-2/+10
2018-06-04Merge pull request #262 from riscv/from_upstreamTim Newsome16-82/+84
2018-06-04breakpoints: simplify the test to find a breakpointAntonio Borneo1-5/+2
2018-06-04target: fix syntax in help messageAntonio Borneo1-3/+1
2018-06-04target: aarch64: Adding mcr, mrc 32-bit coprocesor read/write supportKamal Dasu1-0/+153
2018-06-04Rework/update ARM semihostingLiviu Ionescu13-747/+1895
2018-05-31jtag: drivers: sysfsgpio: lift upper gpio number limitPaul Fertser1-4/+4
2018-05-31jtag/drivers: Add support for TI XDS110 debug probeEdward Fewell7-2/+2009
2018-05-30Merge branch 'master' into from_upstreamTim Newsome16-82/+84
2018-05-30Fix warnings exposed by GCC8Paul Fertser4-10/+12
2018-05-25Merge pull request #261 from riscv/trigger_enumv20180629Tim Newsome3-5/+19
2018-05-22Merge remote-tracking branch 'origin/trigger_enum' into riscv-complianceriscv-compliance-devMegan Wachs3-5/+19
2018-05-22Merge remote-tracking branch 'origin/riscv' into riscv-complianceMegan Wachs74-913/+1614
2018-05-22Merge pull request #257 from riscv/commentTim Newsome2-0/+8
2018-05-22Delay trigger enumeration until it's required.Tim Newsome3-5/+19
2018-05-22Merge pull request #260 from dlrobertson/fix_segfaultTim Newsome1-3/+10
2018-05-22Fix posible null deref in get_target_typeDan Robertson1-3/+10
2018-05-19configure.ac: Fix required libjaylink versionMarc Schink1-1/+1
2018-05-17Review feedback.Tim Newsome1-1/+1
2018-05-17Comment riscv_set_register, register_write_directTim Newsome2-0/+8
2018-05-17Merge pull request #251 from riscv/from_upstreamTim Newsome73-910/+1596
2018-05-17Merge pull request #255 from riscv/reset-unexpected-checkMegan Wachs1-8/+0
2018-05-16Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compl...Megan Wachs1-8/+0
2018-05-16riscv: remove unexpected check during resetMegan Wachs1-8/+0
2018-05-14Remove FSF address to satisfy checkpatchTim Newsome4-20/+0
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