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2022-12-14flash: fix clang static analyzer build errorsdsp5680_buildErhan Kurubas2-5/+0
2022-11-30Merge pull request #772 from riscv/resume_stateTim Newsome1-2/+14
2022-11-29target/riscv: Set target->state in riscv013_halt_go()Tim Newsome1-2/+14
2022-11-25Merge pull request #767 from riscv/unavailableTim Newsome6-172/+303
2022-11-23target/riscv: Fix small riscv013_halt_go() bugTim Newsome1-1/+1
2022-11-23target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAKTim Newsome3-4/+4
2022-11-23target/riscv: Set correct target->state in riscv013_halt_go()Tim Newsome1-3/+26
2022-11-22gdb_server: Operate on available targets.Tim Newsome1-16/+40
2022-11-22target/riscv: Don't resume unavailable harts.Tim Newsome2-7/+19
2022-11-22target/riscv: Share single-target and SMP resume code.Tim Newsome1-30/+33
2022-11-22rtos/hwthread: Hide unavailable targets from thread list.Tim Newsome1-2/+4
2022-11-22target/riscv: Make poll() use TARGET_UNAVAILABLE.Tim Newsome2-60/+152
2022-11-21target/riscv: Refactor riscv_openocd_poll()Tim Newsome1-101/+74
2022-11-21target/riscv: Error when hart becomes unavailable during resumeTim Newsome1-0/+2
2022-11-21Merge pull request #769 from riscv/0.11Tim Newsome2-27/+22
2022-11-17target/riscv: 0.11, call handle_halt() after stepTim Newsome1-1/+3
2022-11-17target/riscv: Ignore maskmax when reading back tdata1Tim Newsome1-15/+18
2022-11-17target/riscv: Don't always read on DMI batch write (#768)Tim Newsome3-13/+19
2022-11-17target/riscv: Ignore debug_execution in 0.11 resumeTim Newsome1-11/+1
2022-11-16Fix breackpoint_add for rtos swbp (#734)Evgeniy Naydanov2-14/+11
2022-11-15Workaround for fp register access in case fp unit is disabled (#766)Evgeniy Naydanov1-11/+11
2022-11-10Improve a couple of user/debug messages. (#763)Tim Newsome2-2/+3
2022-11-10target/riscv: Use vlenb to check whether vector registers exist (#762)Tim Newsome3-24/+13
2022-11-10riscv/target: Replace is_halted() with get_hart_state() (#756)Tim Newsome3-61/+84
2022-11-09Use match field for trigger (#725)Xiang W3-193/+305
2022-11-09target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)Tim Newsome1-5/+16
2022-11-01Fix dm->current_hartid corruption on hartsellen discovery (#754)Dolu19901-1/+9
2022-10-31github/workflow: enable libftdi based adapters (#755)Tim Newsome2-4/+19
2022-10-27target: Add TARGET_UNAVAILABLE state. (#752)Tim Newsome2-0/+4
2022-10-21target/riscv: Correctly set target->state in deassert_reset (#750)Tim Newsome1-2/+7
2022-10-14[riscv] step operation handler should respect handle_breakpoints parameter (#...Anatoly Parshintsev1-3/+22
2022-10-12Properly track selecting multiple harts at once. (#743)Tim Newsome1-59/+64
2022-10-12filter_openocd: Prefer high repetitions.Tim Newsome1-1/+1
2022-10-11target/riscv: Clean up halt_go for multiple harts.Tim Newsome1-6/+11
2022-10-10Merge pull request #745 from dmitryryzhov/fix-bracesTim Newsome1-2/+2
2022-10-10Merge pull request #744 from mrv96/cjtagTim Newsome1-5/+6
2022-10-07(Re)Init cJTAG before move JTAG to reset statemrv961-1/+1
2022-10-07(Re)Init cJTAG only after trst (not after srst)mrv961-4/+5
2022-10-07Fix incorrect braces caused by #732Dmitry Ryzhov1-2/+2
2022-10-06Merge pull request #742 from mrv96/cjtagTim Newsome1-5/+3
2022-10-05Fix Digilent JTAG-HS2 cJTAG configuration scriptmrv961-5/+3
2022-10-05riscv: Minor formatting cleanup.Tim Newsome1-9/+7
2022-10-05Use TMSC_EN signal for cJTAG escape seq if definedmrv961-0/+5
2022-10-05Support cJTAG JScan3 modemrv963-14/+69
2022-10-05Rename ftdi_oscan1 to ftdi_cjtagmrv963-14/+14
2022-10-05OScan1 code cleanupmrv962-119/+119
2022-10-04Merge pull request #738 from riscv/current_hartidTim Newsome4-121/+79
2022-09-30Remove riscv_info_t.current_hartidTim Newsome4-121/+79
2022-09-29Use LOG_TARGET_FOO() functions in more places. (#731)Tim Newsome3-43/+34
2022-09-27Merge pull request #727 from riscv/poll_backoffTim Newsome2-35/+34
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