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-rw-r--r--tcl/board/vd_a53x2_jtag.cfg31
-rw-r--r--tcl/board/vd_m4_jtag.cfg30
-rw-r--r--tcl/board/vd_pulpissimo_jtag.cfg32
-rw-r--r--tcl/board/vd_swerv_jtag.cfg32
-rw-r--r--tcl/interface/vdebug.cfg33
-rw-r--r--tcl/target/vd_aarch64.cfg37
-rw-r--r--tcl/target/vd_cortex_m.cfg12
-rw-r--r--tcl/target/vd_riscv.cfg18
8 files changed, 225 insertions, 0 deletions
diff --git a/tcl/board/vd_a53x2_jtag.cfg b/tcl/board/vd_a53x2_jtag.cfg
new file mode 100644
index 0000000..869bc4d
--- /dev/null
+++ b/tcl/board/vd_a53x2_jtag.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CORES 2
+set _CHIPNAME a53
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x1000000
+set _CPUTAPID 0x5ba00477
+
+# vdebug select transport
+#transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_aarch64.cfg]
diff --git a/tcl/board/vd_m4_jtag.cfg b/tcl/board/vd_m4_jtag.cfg
new file mode 100644
index 0000000..ca21476
--- /dev/null
+++ b/tcl/board/vd_m4_jtag.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex m4 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME m4
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x10000
+set _CPUTAPID 0x4ba00477
+
+# vdebug select transport
+#transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 25000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_cortex_m.cfg]
diff --git a/tcl/board/vd_pulpissimo_jtag.cfg b/tcl/board/vd_pulpissimo_jtag.cfg
new file mode 100644
index 0000000..69dd9e6
--- /dev/null
+++ b/tcl/board/vd_pulpissimo_jtag.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV Ibex core with Pulpissimo through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME ibex
+set _HARTID 0x20
+set _CPUTAPID 0x249511c3
+
+# vdebug select transport
+#transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 12500
+adapter srst delay 10
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 40ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000
+vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000
+
+# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_riscv.cfg]
diff --git a/tcl/board/vd_swerv_jtag.cfg b/tcl/board/vd_swerv_jtag.cfg
new file mode 100644
index 0000000..ff6c683
--- /dev/null
+++ b/tcl/board/vd_swerv_jtag.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV swerv core with Swerv through JTAG
+
+source [find interface/vdebug.cfg]
+
+set _CHIPNAME rv32
+set _HARTID 0x00
+set _CPUTAPID 0x1000008b
+set _MEMSTART 0x00000000
+set _MEMSIZE 0x10000
+
+# vdebug select transport
+#transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor (up to 4)
+vdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE
+
+# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag arp_init-reset
+
+source [find target/vd_riscv.cfg]
diff --git a/tcl/interface/vdebug.cfg b/tcl/interface/vdebug.cfg
new file mode 100644
index 0000000..9cca6aa
--- /dev/null
+++ b/tcl/interface/vdebug.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+
+if { [info exists VDEBUGHOST] } {
+ set _VDEBUGHOST $VDEBUGHOST
+} else {
+ set _VDEBUGHOST localhost
+}
+if { [info exists VDEBUGPORT] } {
+ set _VDEBUGPORT $VDEBUGPORT
+} else {
+ set _VDEBUGPORT 8192
+}
+
+adapter driver vdebug
+# vdebug server:port
+vdebug server $_VDEBUGHOST:$_VDEBUGPORT
+
+# example config debug level and log
+#debug_level 3
+#log_output vd_ocd.log
+
+# example config listen on all interfaces, disable tcl/telnet server
+bindto 0.0.0.0
+#gdb_port 3333
+#telnet_port disabled
+tcl_port disabled
+
+# transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw
+vdebug batching 1
+
+# Polling values
+vdebug polling 100 1000 \ No newline at end of file
diff --git a/tcl/target/vd_aarch64.cfg b/tcl/target/vd_aarch64.cfg
new file mode 100644
index 0000000..619134a
--- /dev/null
+++ b/tcl/target/vd_aarch64.cfg
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm v8 64b Cortex A
+
+if {![info exists _CORES]} {
+ set _CORES 1
+}
+if {![info exists _CHIPNAME]} {
+ set _CHIPNAME aarch64
+}
+set _TARGETNAME $_CHIPNAME.cpu
+set _CTINAME $_CHIPNAME.cti
+
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
+
+dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
+$_CHIPNAME.dap apsel 1
+
+for { set _core 0 } { $_core < $_CORES } { incr _core } \
+{
+ cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
+ set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
+ -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+ if { $_core != 0 } {
+ # non-boot core examination may fail
+ set _command "$_command -defer-examine"
+ set _smp_command "$_smp_command $_TARGETNAME.$_core"
+ } else {
+ set _smp_command "target smp $_TARGETNAME.$_core"
+ }
+ eval $_command
+}
+eval $_smp_command
+
+# default target is core 0
+targets $_TARGETNAME.0
diff --git a/tcl/target/vd_cortex_m.cfg b/tcl/target/vd_cortex_m.cfg
new file mode 100644
index 0000000..4d7b0df
--- /dev/null
+++ b/tcl/target/vd_cortex_m.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# ARM Cortex M
+
+if {![info exists _CHIPNAME]} {
+ set _CHIPNAME cortex_m
+}
+set _TARGETNAME $_CHIPNAME.cpu
+
+dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
+
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
diff --git a/tcl/target/vd_riscv.cfg b/tcl/target/vd_riscv.cfg
new file mode 100644
index 0000000..b42b25a
--- /dev/null
+++ b/tcl/target/vd_riscv.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# RISCV core
+
+if {![info exists _HARTID]} {
+ set _HARTID 0x00
+}
+if {![info exists _CHIPNAME]} {
+ set _CHIPNAME riscv
+}
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+# prefer to use sba for system bus access
+riscv set_prefer_sba on
generated by cgit v1.1 at 2024-07-18 12:33:08 +0000