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-rw-r--r--tcl/board/icnova_imx53_sodimm.cfg2
-rw-r--r--tcl/board/imx53loco.cfg2
-rw-r--r--tcl/target/am335x.cfg4
-rw-r--r--tcl/target/amdm37x.cfg4
-rw-r--r--tcl/target/imx51.cfg4
-rw-r--r--tcl/target/imx53.cfg4
-rw-r--r--tcl/target/omap3530.cfg4
-rw-r--r--tcl/target/omap4430.cfg2
-rw-r--r--tcl/target/omap4460.cfg2
-rw-r--r--tcl/target/u8500.cfg8
10 files changed, 18 insertions, 18 deletions
diff --git a/tcl/board/icnova_imx53_sodimm.cfg b/tcl/board/icnova_imx53_sodimm.cfg
index 9ea78b9..e37887e 100644
--- a/tcl/board/icnova_imx53_sodimm.cfg
+++ b/tcl/board/icnova_imx53_sodimm.cfg
@@ -19,7 +19,7 @@ adapter_khz 3000
$_TARGETNAME configure -event "reset-assert" {
echo "Reseting ...."
- #cortex_a8 dbginit
+ #cortex_a dbginit
}
$_TARGETNAME configure -event reset-init { sodimm_init }
diff --git a/tcl/board/imx53loco.cfg b/tcl/board/imx53loco.cfg
index d9d75f4..4c8a8da 100644
--- a/tcl/board/imx53loco.cfg
+++ b/tcl/board/imx53loco.cfg
@@ -20,7 +20,7 @@ adapter_khz 3000
$_TARGETNAME configure -event "reset-assert" {
echo "Reseting ...."
- #cortex_a8 dbginit
+ #cortex_a dbginit
}
$_TARGETNAME configure -event reset-init { loco_init }
diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg
index 99693dc..9a24ef0 100644
--- a/tcl/target/am335x.cfg
+++ b/tcl/target/am335x.cfg
@@ -64,13 +64,13 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# Cortex A8 target
#
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
# SRAM: 64K at 0x4030.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
$_TARGETNAME configure -event gdb-attach {
- cortex_a8 dbginit
+ cortex_a dbginit
halt
}
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 3121e8f..ab2ccab 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -141,7 +141,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.
@@ -200,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
# reset sequence.
proc amdm37x_dbginit {target} {
# General Cortex A8 debug initialisation
- cortex_a8 dbginit
+ cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# access to the signal appears to be implementation specific. TI does not
diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg
index 706875d..0ee388c 100644
--- a/tcl/target/imx51.cfg
+++ b/tcl/target/imx51.cfg
@@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
@@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx51_dbginit {target} {
# General Cortex A8 debug initialisation
- cortex_a8 dbginit
+ cortex_a dbginit
}
# Slow speed to be sure it will work
diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg
index 7194783..61fabc8 100644
--- a/tcl/target/imx53.cfg
+++ b/tcl/target/imx53.cfg
@@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
@@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx53_dbginit {target} {
# General Cortex A8 debug initialisation
- cortex_a8 dbginit
+ cortex_a dbginit
}
# Slow speed to be sure it will work
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 018363a..0e20852 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
# SRAM: 64K at 0x4020.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
@@ -54,7 +54,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
proc omap3_dbginit {target} {
# General Cortex A8 debug initialisation
- cortex_a8 dbginit
+ cortex_a dbginit
# Enable DBGU signal for OMAP353x
$target mww phys 0x5401d030 0x00002000
}
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 2e9f554..6f3525a 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -94,7 +94,7 @@ set _coreid 0
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
echo "Using dbgbase = [format 0x%x $_dbgbase]"
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase $_dbgbase
# SRAM: 56KiB at 0x4030.0000
diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg
index 5fdd654..9c40e62 100644
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/omap4460.cfg
@@ -94,7 +94,7 @@ set _coreid 0
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
echo "Using dbgbase = [format 0x%x $_dbgbase]"
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase $_dbgbase
# SRAM: 56KiB at 0x4030.0000
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 348058c..66fc075 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -19,12 +19,12 @@ proc ocd_gdb_restart {target_id} {
global _SMP
targets $_TARGETNAME_1
if { [expr ($_SMP == 1)] } {
- cortex_a8 smp_off
+ cortex_a smp_off
}
rst_run
halt
if { [expr ($_SMP == 1)]} {
- cortex_a8 smp_on
+ cortex_a smp_on
}
}
@@ -202,7 +202,7 @@ if { [info exists DAP_DBG2] } {
set _DAP_DBG2 0x801AA000
}
-target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
+target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
$_TARGETNAME_1 configure -event gdb-attach {
halt
@@ -217,7 +217,7 @@ global _TARGETNAME_2
set _TARGETNAME_2 $TARGETNAME_2
}
-target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
+target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
$_TARGETNAME_2 configure -event gdb-attach {
halt
generated by cgit v1.1 at 2024-07-18 07:34:45 +0000