diff options
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/board/esp32s2-kaluga-1.cfg | 18 | ||||
| -rw-r--r-- | tcl/interface/ftdi/esp32s2_kaluga_v1.cfg | 29 | ||||
| -rw-r--r-- | tcl/target/esp32s2.cfg | 30 |
3 files changed, 77 insertions, 0 deletions
diff --git a/tcl/board/esp32s2-kaluga-1.cfg b/tcl/board/esp32s2-kaluga-1.cfg new file mode 100644 index 0000000..783ea21 --- /dev/null +++ b/tcl/board/esp32s2-kaluga-1.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Example OpenOCD configuration file for ESP32-S2 Kaluga board. +# +# For example, OpenOCD can be started for ESP32-S2 debugging on +# +# openocd -f board/esp32s2-kaluga-1.cfg +# + +source [find interface/ftdi/esp32s2_kaluga_v1.cfg] +source [find target/esp32s2.cfg] + +# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +# On ESP32-S2, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz +# if CPU frequency is 160MHz or 240MHz. +adapter speed 20000 diff --git a/tcl/interface/ftdi/esp32s2_kaluga_v1.cfg b/tcl/interface/ftdi/esp32s2_kaluga_v1.cfg new file mode 100644 index 0000000..1880bcb --- /dev/null +++ b/tcl/interface/ftdi/esp32s2_kaluga_v1.cfg @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Driver for the FT2232H JTAG chip on the Espressif Kaluga-1 ESP32-S2 board +# (and most other FT2232H and FT232H based boards) +# +# JTAG DIP switch (labelled SW5 in the schematic) should be "ON" for lines +# labelled TCK, TDO, TDI and TWS, to connect the FT2232H to the ESP32-S2. +# + +adapter driver ftdi +ftdi vid_pid 0x0403 0x6010 0x0403 0x6014 + +# interface 1 is the uart +ftdi channel 0 + +# TCK, TDI, TDO, TMS: ADBUS0-3 +# TRST/SRST: ADBUS5 (unused for now) +# LEDs: ACBUS3-4 (inverted) + +ftdi layout_init 0x0008 0x180b +ftdi layout_signal LED -ndata 0x0800 +ftdi layout_signal LED2 -ndata 0x1000 + +# ESP32* series chips do not have a TRST input, and the SRST line is connected +# to the EN pin. +# The target code doesn't handle SRST reset properly yet, so this is +# commented out: +# ftdi layout_signal nSRST -oe 0x0020 +# reset_config srst_only diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg new file mode 100644 index 0000000..ab64c31 --- /dev/null +++ b/tcl/target/esp32s2.cfg @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# The ESP32-S2 only supports JTAG. +transport select jtag + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME esp32s2 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x120034e5 +} + +set _TARGETNAME $_CHIPNAME +set _CPUNAME cpu +set _TAPNAME $_CHIPNAME.$_CPUNAME + +jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID + +target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME + +xtensa maskisr on + +$_TARGETNAME configure -event reset-assert-post { soft_reset_halt } + +gdb_breakpoint_override hard |