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-rw-r--r--tcl/target/allwinner_v3s.cfg2
-rw-r--r--tcl/target/ampere_emag.cfg2
-rw-r--r--tcl/target/bl702.cfg60
-rw-r--r--tcl/target/esi32xx.cfg2
-rw-r--r--tcl/target/esp_common.cfg2
-rw-r--r--tcl/target/icepick.cfg2
-rw-r--r--tcl/target/omap4430.cfg2
-rw-r--r--tcl/target/omap4460.cfg2
-rw-r--r--tcl/target/omapl138.cfg2
-rw-r--r--tcl/target/psoc6.cfg4
-rw-r--r--tcl/target/rp2040.cfg2
-rw-r--r--tcl/target/ti_k3.cfg10
-rw-r--r--tcl/target/u8500.cfg6
-rw-r--r--tcl/target/xtensa.cfg2
14 files changed, 85 insertions, 15 deletions
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 437bd95..6c3435e 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -28,7 +28,7 @@
# UART2_TX PB0 Per default disabled
# UART2_RX PB1 Per default disabled
#
-# JTAG is enabled by default after power on on listed JTAG_* pins. So far the
+# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the
# boot sequence is:
# Time Action
# 0000ms Power ON
diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg
index 0b0bd9e..fd68fcd 100644
--- a/tcl/target/ampere_emag.cfg
+++ b/tcl/target/ampere_emag.cfg
@@ -8,7 +8,7 @@
#
# Configure defaults for target
-# Can be overriden in board configuration file
+# Can be overridden in board configuration file
#
if { [info exists CHIPNAME] } {
diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg
new file mode 100644
index 0000000..6d4a048
--- /dev/null
+++ b/tcl/target/bl702.cfg
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL702, BL704 and BL706 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=8
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TMS - GPIO0
+# TDI - GPIO1
+# TCK - GPIO2
+# TDO - GPIO9
+#
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME bl702
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+
+$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 4000
+
+$_TARGETNAME configure -event reset-assert-pre {
+ halt
+
+ # Switch clock to internal RC32M
+ # In HBN_GLB, set ROOT_CLK_SEL = 0
+ mmw 0x4000f030 0x0 0x00000003
+ # Wait for clock switch
+ sleep 10
+
+ # GLB_REG_BCLK_DIS_FALSE
+ mww 0x40000ffc 0x0
+
+ # HCLK is RC32M, so BCLK/HCLK doesn't need divider
+ # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+ mmw 0x40000000 0x0 0x00FFFF00
+ # Wait for clock to stabilize
+ sleep 10
+
+ # Do reset
+ # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
+ mmw 0x40000018 0x0 0x00000007
+ # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
+ mmw 0x40000018 0x6 0x0
+}
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index a8b0823..d29c636 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -35,4 +35,4 @@ reset_config none
# The default linker scripts provided by the eSi-RISC toolchain do not
# specify attributes on memory regions, which results in incorrect
# application of software breakpoints by GDB.
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
index af2f6ad..5ea9bc8 100644
--- a/tcl/target/esp_common.cfg
+++ b/tcl/target/esp_common.cfg
@@ -200,7 +200,7 @@ proc configure_esp_xtensa_default_settings { } {
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
}
- gdb_breakpoint_override hard
+ gdb breakpoint_override hard
if { [info exists _FLASH_VOLTAGE] } {
$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 5509532..e5d5706 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -6,7 +6,7 @@
#
# Utilities for TI ICEpick-C/D used in most TI SoCs
-# Details about the ICEPick are available in the the TRM for each SoC
+# Details about the ICEPick are available in the TRM for each SoC
# and http://processors.wiki.ti.com/index.php/ICEPICK
# create "constants"
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index a448550..4bc7fe1 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
$_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg
index bbc824b..85ba96c 100644
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/omap4460.cfg
@@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
$_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 2d670b9..78c456d 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -64,5 +64,5 @@ arm7_9 dcc_downloads enable
etm config $_TARGETNAME 16 normal full etb
etb config $_TARGETNAME $_CHIPNAME.etb
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
arm7_9 dbgrq enable
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index d69515c..52b04f5 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -113,7 +113,7 @@ proc psoc6_deassert_post { target } {
}
if { $_ENABLE_CM0 } {
- target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+ target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1
${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
@@ -128,7 +128,7 @@ if { $_ENABLE_CM0 } {
}
if { $_ENABLE_CM4 } {
- target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+ target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2
${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4
diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg
index de76b4e..5e78c69 100644
--- a/tcl/target/rp2040.cfg
+++ b/tcl/target/rp2040.cfg
@@ -96,7 +96,7 @@ if { $_USE_CORE == 1 } {
set _FLASH_TARGET $_TARGETNAME_0
}
# Backup the work area. The flash probe runs an algorithm on the target CPU.
-# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+# The flash is probed during gdb connect if gdb memory_map is enabled (by default).
$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index ebea821..2ae0f75 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -209,6 +209,16 @@ switch $_soc {
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+ # Setup DMEM access descriptions
+ # DAPBUS (Debugger) description
+ set _dmem_base_address 0x740002000
+ set _dmem_ap_address_offset 0x100
+ set _dmem_max_aps 10
+ # Emulated AP description
+ set _dmem_emu_base_address 0x760000000
+ set _dmem_emu_base_address_map_to 0x1d500000
+ set _dmem_emu_ap_list 1
+
# Overrides for am62p
if { "$_soc" == "am62p" } {
set _K3_DAP_TAPID 0x0bb9d02f
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 417fdd1..b87d261 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -142,9 +142,9 @@ proc enable_apetap {} {
}
}
-tcl_port 5555
+tcl port 5555
telnet_port 4444
-gdb_port 3333
+gdb port 3333
if { [info exists CHIPNAME] } {
global _CHIPNAME
@@ -319,7 +319,7 @@ global _MAXSPEED
adapter speed $_MAXSPEED
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
set mem inaccessible-by-default-off
jtag_ntrst_delay 100
diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg
index 561131d..c277673 100644
--- a/tcl/target/xtensa.cfg
+++ b/tcl/target/xtensa.cfg
@@ -67,4 +67,4 @@ if { $_XTENSA_NUM_CORES == 1 } {
$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
}
-gdb_report_register_access_error enable
+gdb report_register_access_error enable
generated by cgit v1.1 at 2024-09-18 10:44:18 +0000