diff options
Diffstat (limited to 'tcl/target/esp32c2.cfg')
| -rw-r--r-- | tcl/target/esp32c2.cfg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcl/target/esp32c2.cfg b/tcl/target/esp32c2.cfg index 42aeb0a..51de1d1 100644 --- a/tcl/target/esp32c2.cfg +++ b/tcl/target/esp32c2.cfg @@ -5,7 +5,7 @@ source [find target/esp_common.cfg] # Target specific global variables -set _CHIPNAME "riscv" +set _CHIPNAME "esp32c2" set _CPUTAPID 0x0000cc25 set _ESP_ARCH "riscv" set _ONLYCPU 1 @@ -14,7 +14,7 @@ set _ESP_SMP_BREAK 0 set _ESP_EFUSE_MAC_ADDR_REG 0x60008840 # Target specific functions should be implemented for each riscv chips. -proc riscv_wdt_disable { } { +proc esp32c2_wdt_disable { } { # Halt event can occur during config phase (before "init" is done). # Ignore it since mww commands don't work at that time. if { [string compare [command mode] config] == 0 } { @@ -32,7 +32,7 @@ proc riscv_wdt_disable { } { mww 0x600080A0 0x84B00000 } -proc riscv_soc_reset { } { +proc esp32c2_soc_reset { } { global _RISCV_DMCONTROL # This procedure does "digital system reset", i.e. resets @@ -52,7 +52,7 @@ proc riscv_soc_reset { } { sleep 10 poll # Disable the watchdogs again - riscv_wdt_disable + esp32c2_wdt_disable # Here debugger reads allresumeack and allhalted bits as set (0x330a2) # We will clean allhalted state by resuming the core. @@ -62,7 +62,7 @@ proc riscv_soc_reset { } { riscv dmi_write $_RISCV_DMCONTROL 0x80000003 } -proc riscv_memprot_is_enabled { } { +proc esp32c2_memprot_is_enabled { } { global _RISCV_ABS_CMD _RISCV_ABS_DATA0 # PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region |