1 files changed, 44 insertions, 0 deletions
diff --git a/tcl/target/eos_s3.cfg b/tcl/target/eos_s3.cfg
new file mode 100644
index 0000000..f6016fb
--- /dev/null
+++ b/tcl/target/eos_s3.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3
+# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME eos_s3
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x80000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id _CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# For now we use SRAM only for software upload
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 4000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}