diff options
Diffstat (limited to 'src/target')
42 files changed, 605 insertions, 540 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 63174c2..ff68e3a 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -29,6 +29,7 @@ #include "armv8_opcodes.h" #include "armv8_cache.h" #include "arm_semihosting.h" +#include "smp.h" #include <helper/time_support.h> enum restart_mode { @@ -63,9 +64,6 @@ static int aarch64_virt2phys(struct target *target, static int aarch64_read_cpu_memory(struct target *target, uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer); -#define foreach_smp_target(pos, head) \ - for (pos = head; (pos != NULL); pos = pos->next) - static int aarch64_restore_system_control_reg(struct target *target) { enum arm_mode target_mode = ARM_MODE_ANY; @@ -601,8 +599,8 @@ static int aarch64_restore_one(struct target *target, int current, } LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc); buf_set_u64(arm->pc->value, 0, 64, resume_pc); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; /* called it now before restoring context because it uses cpu * register r0 for restoring system control register */ @@ -2388,7 +2386,8 @@ static int aarch64_init_arch_info(struct target *target, armv8->armv8_mmu.read_physical_memory = aarch64_read_phys_memory; armv8_init_arch_info(target, armv8); - target_register_timer_callback(aarch64_handle_target_request, 1, 1, target); + target_register_timer_callback(aarch64_handle_target_request, 1, + TARGET_TIMER_TYPE_PERIODIC, target); return ERROR_OK; } @@ -2396,11 +2395,17 @@ static int aarch64_init_arch_info(struct target *target, static int aarch64_target_create(struct target *target, Jim_Interp *interp) { struct aarch64_private_config *pc = target->private_config; - struct aarch64_common *aarch64 = calloc(1, sizeof(struct aarch64_common)); + struct aarch64_common *aarch64; if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK) return ERROR_FAIL; + aarch64 = calloc(1, sizeof(struct aarch64_common)); + if (aarch64 == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap); } @@ -2543,42 +2548,6 @@ COMMAND_HANDLER(aarch64_handle_dbginit_command) return aarch64_init_debug_access(target); } -COMMAND_HANDLER(aarch64_handle_smp_off_command) -{ - struct target *target = get_current_target(CMD_CTX); - /* check target is an smp target */ - struct target_list *head; - struct target *curr; - head = target->head; - target->smp = 0; - if (head != (struct target_list *)NULL) { - while (head != (struct target_list *)NULL) { - curr = head->target; - curr->smp = 0; - head = head->next; - } - /* fixes the target display to the debugger */ - target->gdb_service->target = target; - } - return ERROR_OK; -} - -COMMAND_HANDLER(aarch64_handle_smp_on_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct target_list *head; - struct target *curr; - head = target->head; - if (head != (struct target_list *)NULL) { - target->smp = 1; - while (head != (struct target_list *)NULL) { - curr = head->target; - curr->smp = 1; - head = head->next; - } - } - return ERROR_OK; -} COMMAND_HANDLER(aarch64_mask_interrupts_command) { @@ -2760,19 +2729,6 @@ static const struct command_registration aarch64_exec_command_handlers[] = { .help = "Initialize core debug", .usage = "", }, - { .name = "smp_off", - .handler = aarch64_handle_smp_off_command, - .mode = COMMAND_EXEC, - .help = "Stop smp handling", - .usage = "", - }, - { - .name = "smp_on", - .handler = aarch64_handle_smp_on_command, - .mode = COMMAND_EXEC, - .help = "Restart smp handling", - .usage = "", - }, { .name = "maskisr", .handler = aarch64_mask_interrupts_command, @@ -2794,6 +2750,9 @@ static const struct command_registration aarch64_exec_command_handlers[] = { .help = "read coprocessor register", .usage = "cpnum op1 CRn CRm op2", }, + { + .chain = smp_command_handlers, + }, COMMAND_REGISTRATION_DONE diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index eb181cb..d92e296 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -166,22 +166,26 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack) } /** Select the DP register bank matching bits 7:4 of reg. */ -static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg) +static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg) { /* Only register address 4 is banked. */ if ((reg & 0xf) != 4) - return; + return ERROR_OK; uint32_t select_dp_bank = (reg & 0x000000F0) >> 4; uint32_t sel = select_dp_bank | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK)); if (sel == dap->select) - return; + return ERROR_OK; dap->select = sel; - swd_queue_dp_write(dap, DP_SELECT, sel); + int retval = swd_queue_dp_write(dap, DP_SELECT, sel); + if (retval != ERROR_OK) + dap->select = DP_SELECT_INVALID; + + return retval; } static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, @@ -194,7 +198,10 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, if (retval != ERROR_OK) return retval; - swd_queue_dp_bankselect(dap, reg); + retval = swd_queue_dp_bankselect(dap, reg); + if (retval != ERROR_OK) + return retval; + swd->read_reg(swd_cmd(true, false, reg), data, 0); return check_sync(dap); @@ -211,14 +218,29 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg, return retval; swd_finish_read(dap); - swd_queue_dp_bankselect(dap, reg); + if (reg == DP_SELECT) { + dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK); + + swd->write_reg(swd_cmd(false, false, reg), data, 0); + + retval = check_sync(dap); + if (retval != ERROR_OK) + dap->select = DP_SELECT_INVALID; + + return retval; + } + + retval = swd_queue_dp_bankselect(dap, reg); + if (retval != ERROR_OK) + return retval; + swd->write_reg(swd_cmd(false, false, reg), data, 0); return check_sync(dap); } /** Select the AP register bank matching bits 7:4 of reg. */ -static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg) +static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg) { struct adiv5_dap *dap = ap->dap; uint32_t sel = ((uint32_t)ap->ap_num << 24) @@ -226,11 +248,15 @@ static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg) | (dap->select & DP_SELECT_DPBANK); if (sel == dap->select) - return; + return ERROR_OK; dap->select = sel; - swd_queue_dp_write(dap, DP_SELECT, sel); + int retval = swd_queue_dp_write(dap, DP_SELECT, sel); + if (retval != ERROR_OK) + dap->select = DP_SELECT_INVALID; + + return retval; } static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, @@ -244,7 +270,10 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, if (retval != ERROR_OK) return retval; - swd_queue_ap_bankselect(ap, reg); + retval = swd_queue_ap_bankselect(ap, reg); + if (retval != ERROR_OK) + return retval; + swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck); dap->last_read = data; @@ -263,7 +292,10 @@ static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg, return retval; swd_finish_read(dap); - swd_queue_ap_bankselect(ap, reg); + retval = swd_queue_ap_bankselect(ap, reg); + if (retval != ERROR_OK) + return retval; + swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck); return check_sync(dap); diff --git a/src/target/arm11.c b/src/target/arm11.c index 4438661..159c30a 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -442,8 +442,8 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t a } buf_set_u32(value, 0, 32, address); - arm11->arm.pc->dirty = 1; - arm11->arm.pc->valid = 1; + arm11->arm.pc->dirty = true; + arm11->arm.pc->valid = true; return address; } diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 3d12aba..b592ffc 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -365,12 +365,12 @@ static int arm720t_soft_reset_halt(struct target *target) cpsr &= ~0xff; cpsr |= 0xd3; arm_set_cpsr(arm, cpsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; /* start fetching from 0x0 */ buf_set_u32(arm->pc->value, 0, 32, 0x0); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; retval = arm720t_disable_mmu_caches(target, 1, 1, 1); if (retval != ERROR_OK) diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 7fd1ed9..c6a8a26 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1141,20 +1141,20 @@ int arm7_9_soft_reset_halt(struct target *target) cpsr &= ~0xff; cpsr |= 0xd3; arm_set_cpsr(arm, cpsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; /* start fetching from 0x0 */ buf_set_u32(arm->pc->value, 0, 32, 0x0); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; /* reset registers */ for (i = 0; i <= 14; i++) { struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, 0xffffffff); - r->dirty = 1; - r->valid = 1; + r->dirty = true; + r->valid = true; } retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1346,7 +1346,7 @@ static int arm7_9_debug_entry(struct target *target) buf_set_u32(r->value, 0, 32, context[i]); /* r0 and r15 (pc) have to be restored later */ r->dirty = (i == 0) || (i == 15); - r->valid = 1; + r->valid = true; } LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]); @@ -1359,8 +1359,8 @@ static int arm7_9_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; buf_set_u32(arm->spsr->value, 0, 32, spsr); - arm->spsr->dirty = 0; - arm->spsr->valid = 1; + arm->spsr->dirty = false; + arm->spsr->valid = true; } retval = jtag_execute_queue(); @@ -1411,13 +1411,13 @@ static int arm7_9_full_context(struct target *target) uint32_t mask = 0; uint32_t *reg_p[16]; int j; - int valid = 1; + bool valid = true; /* check if there are invalid registers in the current mode */ for (j = 0; j <= 16; j++) { - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) - valid = 0; + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid) + valid = false; } if (!valid) { @@ -1431,8 +1431,8 @@ static int arm7_9_full_context(struct target *target) arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); for (j = 0; j < 15; j++) { - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, - armv4_5_number_to_mode(i), j).valid == 0) { + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), j).valid) { reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE( arm->core_cache, armv4_5_number_to_mode(i), @@ -1440,10 +1440,10 @@ static int arm7_9_full_context(struct target *target) mask |= 1 << j; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - j).valid = 1; + j).valid = true; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - j).dirty = 0; + j).dirty = false; } } @@ -1452,15 +1452,15 @@ static int arm7_9_full_context(struct target *target) arm7_9->read_core_regs(target, mask, reg_p); /* check if the PSR has to be read */ - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - 16).valid == 0) { + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), + 16).valid) { arm7_9->read_xpsr(target, (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).value, 1); ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - 16).valid = 1; + 16).valid = true; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - 16).dirty = 0; + 16).dirty = false; } } } @@ -1494,7 +1494,7 @@ static int arm7_9_restore_context(struct target *target) struct reg *reg; enum arm_mode current_mode = arm->core_mode; int i, j; - int dirty; + bool dirty; int mode_change; LOG_DEBUG("-"); @@ -1518,15 +1518,15 @@ static int arm7_9_restore_context(struct target *target) for (i = 0; i < 6; i++) { LOG_DEBUG("examining %s mode", arm_mode_name(arm->core_mode)); - dirty = 0; + dirty = false; mode_change = 0; /* check if there are dirty registers in the current mode */ for (j = 0; j <= 16; j++) { reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); - if (reg->dirty == 1) { - if (reg->valid == 1) { - dirty = 1; + if (reg->dirty) { + if (reg->valid) { + dirty = true; LOG_DEBUG("examining dirty reg: %s", reg->name); struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; @@ -1567,12 +1567,12 @@ static int arm7_9_restore_context(struct target *target) armv4_5_number_to_mode(i), j); - if (reg->dirty == 1) { + if (reg->dirty) { regs[j] = buf_get_u32(reg->value, 0, 32); mask |= 1 << j; num_regs++; - reg->dirty = 0; - reg->valid = 1; + reg->dirty = false; + reg->valid = true; LOG_DEBUG("writing register %i mode %s " "with value 0x%8.8" PRIx32, j, arm_mode_name(arm->core_mode), @@ -1614,15 +1614,15 @@ static int arm7_9_restore_context(struct target *target) arm7_9->write_xpsr(target, buf_get_u32(arm->cpsr->value, 0, 32) & ~0x20, 0); - arm->cpsr->dirty = 0; - arm->cpsr->valid = 1; + arm->cpsr->dirty = false; + arm->cpsr->valid = true; } /* restore PC */ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(arm->pc->value, 0, 32)); arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32)); - arm->pc->dirty = 0; + arm->pc->dirty = false; return ERROR_OK; } @@ -2024,8 +2024,8 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, if (retval != ERROR_OK) return retval; - r->valid = 1; - r->dirty = 0; + r->valid = true; + r->dirty = false; buf_set_u32(r->value, 0, 32, value); if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) @@ -2081,8 +2081,8 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, arm7_9->write_xpsr(target, t, spsr); } - r->valid = 1; - r->dirty = 0; + r->valid = true; + r->dirty = false; if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { @@ -2859,7 +2859,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) return retval; return target_register_timer_callback(arm7_9_handle_target_request, - 1, 1, target); + 1, TARGET_TIMER_TYPE_PERIODIC, target); } static const struct command_registration arm7_9_any_command_handlers[] = { diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 39d7590..ed9d388 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -283,8 +283,8 @@ static int arm920t_read_cp15_interpreted(struct target *target, return ERROR_FAIL; } - r[0].dirty = 1; - r[1].dirty = 1; + r[0].dirty = true; + r[1].dirty = true; return ERROR_OK; } @@ -327,8 +327,8 @@ int arm920t_write_cp15_interpreted(struct target *target, return ERROR_FAIL; } - r[0].dirty = 1; - r[1].dirty = 1; + r[0].dirty = true; + r[1].dirty = true; return ERROR_OK; } @@ -781,12 +781,12 @@ int arm920t_soft_reset_halt(struct target *target) cpsr &= ~0xff; cpsr |= 0xd3; arm_set_cpsr(arm, cpsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; /* start fetching from 0x0 */ buf_set_u32(arm->pc->value, 0, 32, 0x0); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 07c519a..3f22a8a 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -576,12 +576,12 @@ int arm926ejs_soft_reset_halt(struct target *target) cpsr &= ~0xff; cpsr |= 0xd3; arm_set_cpsr(arm, cpsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; /* start fetching from 0x0 */ buf_set_u32(arm->pc->value, 0, 32, 0x0); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1); if (retval != ERROR_OK) diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c index 9117a74..61f1e78 100644 --- a/src/target/arm_semihosting.c +++ b/src/target/arm_semihosting.c @@ -94,12 +94,12 @@ static int post_result(struct target *target) /* return value in R0 */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result); - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].dirty = true; /* LR --> PC */ buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32, buf_get_u32(arm_reg_current(arm, 14)->value, 0, 32)); - arm->core_cache->reg_list[15].dirty = 1; + arm->core_cache->reg_list[15].dirty = true; /* saved PSR --> current PSR */ spsr = buf_get_u32(arm->spsr->value, 0, 32); @@ -109,7 +109,7 @@ static int post_result(struct target *target) */ buf_set_u32(arm->cpsr->value, 0, 32, spsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; arm->core_mode = spsr & 0x1f; if (spsr & 0x20) arm->core_state = ARM_STATE_THUMB; @@ -118,11 +118,11 @@ static int post_result(struct target *target) if (arm->core_state == ARM_STATE_AARCH64) { /* return value in R0 */ buf_set_u64(arm->core_cache->reg_list[0].value, 0, 64, target->semihosting->result); - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].dirty = true; uint64_t pc = buf_get_u64(arm->core_cache->reg_list[32].value, 0, 64); buf_set_u64(arm->pc->value, 0, 64, pc + 4); - arm->pc->dirty = 1; + arm->pc->dirty = true; } } else { /* resume execution, this will be pc+2 to skip over the @@ -130,7 +130,7 @@ static int post_result(struct target *target) /* return result in R0 */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, target->semihosting->result); - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].dirty = true; } return ERROR_OK; diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 30aeb43..e16a9ec 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -434,8 +434,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) */ if (arm->cpsr) { buf_set_u32(arm->cpsr->value, 0, 32, cpsr); - arm->cpsr->valid = 1; - arm->cpsr->dirty = 0; + arm->cpsr->valid = true; + arm->cpsr->dirty = false; } arm->core_mode = mode; @@ -526,7 +526,7 @@ static struct reg_feature arm_gdb_dummy_fp_features = { struct reg arm_gdb_dummy_fp_reg = { .name = "GDB dummy FPA register", .value = (uint8_t *) arm_gdb_dummy_fp_value, - .valid = 1, + .valid = true, .size = 96, .exist = false, .number = 16, @@ -543,7 +543,7 @@ static const uint8_t arm_gdb_dummy_fps_value[4]; struct reg arm_gdb_dummy_fps_reg = { .name = "GDB dummy FPA status register", .value = (uint8_t *) arm_gdb_dummy_fps_value, - .valid = 1, + .valid = true, .size = 32, .exist = false, .number = 24, @@ -573,8 +573,8 @@ static int armv4_5_get_core_reg(struct reg *reg) retval = reg_arch_info->arm->read_core_reg(target, reg, reg_arch_info->num, reg_arch_info->mode); if (retval == ERROR_OK) { - reg->valid = 1; - reg->dirty = 0; + reg->valid = true; + reg->dirty = false; } return retval; @@ -619,9 +619,9 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) value = buf_get_u32(buf + 4, 0, 32); buf_set_u32(reg->value + 4, 0, 32, value); } - reg->valid = 1; + reg->valid = true; } - reg->dirty = 1; + reg->dirty = true; return ERROR_OK; } @@ -1399,8 +1399,8 @@ int armv4_5_run_algorithm_inner(struct target *target, arm_algorithm_info->core_mode); buf_set_u32(arm->cpsr->value, 0, 5, arm_algorithm_info->core_mode); - arm->cpsr->dirty = 1; - arm->cpsr->valid = 1; + arm->cpsr->dirty = true; + arm->cpsr->valid = true; } /* terminate using a hardware or (ARMv5+) software breakpoint */ @@ -1470,14 +1470,14 @@ int armv4_5_run_algorithm_inner(struct target *target, buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]); ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, - i).valid = 1; + i).valid = true; ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, - i).dirty = 1; + i).dirty = true; } } arm_set_cpsr(arm, cpsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; arm->core_state = core_state; diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c index 23d201f..153bfcc 100644 --- a/src/target/armv7a_mmu.c +++ b/src/target/armv7a_mmu.c @@ -152,8 +152,6 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, if (retval != ERROR_OK) goto done; *val = (*val & ~0xfff) + (va & 0xfff); - if (*val == va) - LOG_WARNING("virt = phys : MMU disable !!"); if (meminfo) { LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured", va, *val, diff --git a/src/target/armv7m.c b/src/target/armv7m.c index ef00b94..3d73b29 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -205,8 +205,8 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_cpy(buf, reg->value, reg->size); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -244,8 +244,8 @@ static int armv7m_read_core_reg(struct target *target, struct reg *r, buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value); } - armv7m->arm.core_cache->reg_list[num].valid = 1; - armv7m->arm.core_cache->reg_list[num].dirty = 0; + armv7m->arm.core_cache->reg_list[num].valid = true; + armv7m->arm.core_cache->reg_list[num].dirty = false; return retval; } @@ -283,8 +283,8 @@ static int armv7m_write_core_reg(struct target *target, struct reg *r, goto out_error; } - armv7m->arm.core_cache->reg_list[num].valid = 1; - armv7m->arm.core_cache->reg_list[num].dirty = 0; + armv7m->arm.core_cache->reg_list[num].valid = true; + armv7m->arm.core_cache->reg_list[num].dirty = false; return ERROR_OK; @@ -424,8 +424,8 @@ int armv7m_start_algorithm(struct target *target, */ struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR]; buf_set_u32(reg->value, 0, 32, 0x01000000); - reg->valid = 1; - reg->dirty = 1; + reg->valid = true; + reg->dirty = true; } if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY && @@ -440,8 +440,8 @@ int armv7m_start_algorithm(struct target *target, LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true; } /* save previous core mode */ @@ -535,8 +535,8 @@ int armv7m_wait_algorithm(struct target *target, armv7m_algorithm_info->context[i]); buf_set_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32, armv7m_algorithm_info->context[i]); - armv7m->arm.core_cache->reg_list[i].valid = 1; - armv7m->arm.core_cache->reg_list[i].dirty = 1; + armv7m->arm.core_cache->reg_list[i].valid = true; + armv7m->arm.core_cache->reg_list[i].dirty = true; } } @@ -545,8 +545,8 @@ int armv7m_wait_algorithm(struct target *target, LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; - armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true; + armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true; } armv7m->arm.core_mode = armv7m_algorithm_info->core_mode; @@ -619,8 +619,8 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) if (storage_size < 4) storage_size = 4; reg_list[i].value = calloc(1, storage_size); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &armv7m_reg_type; reg_list[i].arch_info = &arch_info[i]; diff --git a/src/target/armv7m_trace.c b/src/target/armv7m_trace.c index 62f0f8e..6170119 100644 --- a/src/target/armv7m_trace.c +++ b/src/target/armv7m_trace.c @@ -116,7 +116,8 @@ int armv7m_trace_tpiu_config(struct target *target) return retval; if (trace_config->config_type == TRACE_CONFIG_TYPE_INTERNAL) - target_register_timer_callback(armv7m_poll_trace, 1, 1, target); + target_register_timer_callback(armv7m_poll_trace, 1, + TARGET_TIMER_TYPE_PERIODIC, target); target_call_event_callbacks(target, TARGET_EVENT_TRACE_CONFIG); diff --git a/src/target/armv8.c b/src/target/armv8.c index cee837f..c8cfcae 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -678,8 +678,8 @@ void armv8_set_cpsr(struct arm *arm, uint32_t cpsr) */ if (arm->cpsr) { buf_set_u32(arm->cpsr->value, 0, 32, cpsr); - arm->cpsr->valid = 1; - arm->cpsr->dirty = 0; + arm->cpsr->valid = true; + arm->cpsr->dirty = false; } /* Older ARMs won't have the J bit */ @@ -1013,6 +1013,72 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va, return retval; } +COMMAND_HANDLER(armv8_handle_exception_catch_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct armv8_common *armv8 = target_to_armv8(target); + uint32_t edeccr = 0; + unsigned int argp = 0; + int retval; + + static const Jim_Nvp nvp_ecatch_modes[] = { + { .name = "off", .value = 0 }, + { .name = "nsec_el1", .value = (1 << 5) }, + { .name = "nsec_el2", .value = (2 << 5) }, + { .name = "nsec_el12", .value = (3 << 5) }, + { .name = "sec_el1", .value = (1 << 1) }, + { .name = "sec_el3", .value = (4 << 1) }, + { .name = "sec_el13", .value = (5 << 1) }, + { .name = NULL, .value = -1 }, + }; + const Jim_Nvp *n; + + if (CMD_ARGC == 0) { + const char *sec = NULL, *nsec = NULL; + + retval = mem_ap_read_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_ECCR, &edeccr); + if (retval != ERROR_OK) + return retval; + + n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f); + if (n->name != NULL) + sec = n->name; + + n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0); + if (n->name != NULL) + nsec = n->name; + + if (sec == NULL || nsec == NULL) { + LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff); + return ERROR_FAIL; + } + + command_print(CMD_CTX, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec); + return ERROR_OK; + } + + while (CMD_ARGC > argp) { + n = Jim_Nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]); + if (n->name == NULL) { + LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]); + return ERROR_FAIL; + } + + LOG_DEBUG("found: %s", n->name); + + edeccr |= n->value; + argp++; + } + + retval = mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_ECCR, edeccr); + if (retval != ERROR_OK) + return retval; + + return ERROR_OK; +} + int armv8_handle_cache_info_command(struct command_context *cmd_ctx, struct armv8_cache_common *armv8_cache) { @@ -1452,17 +1518,17 @@ static int armv8_set_core_reg(struct reg *reg, uint8_t *buf) armv8_set_cpsr(arm, (uint32_t)value); else { buf_set_u64(reg->value, 0, reg->size, value); - reg->valid = 1; + reg->valid = true; } } else if (reg->size <= 128) { uint64_t hvalue = buf_get_u64(buf + 8, 0, reg->size - 64); buf_set_u64(reg->value, 0, 64, value); buf_set_u64(reg->value + 8, 0, reg->size - 64, hvalue); - reg->valid = 1; + reg->valid = true; } - reg->dirty = 1; + reg->dirty = true; return ERROR_OK; } @@ -1519,11 +1585,11 @@ static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf) uint64_t value64 = buf_get_u64(buf, 0, 64); buf_set_u64(reg->value, 0, 64, value64); } - reg->valid = 1; - reg64->valid = 1; + reg->valid = true; + reg64->valid = true; } - reg64->dirty = 1; + reg64->dirty = true; return ERROR_OK; } @@ -1675,6 +1741,13 @@ void armv8_free_reg_cache(struct target *target) } const struct command_registration armv8_command_handlers[] = { + { + .name = "catch_exc", + .handler = armv8_handle_exception_catch_command, + .mode = COMMAND_EXEC, + .help = "configure exception catch", + .usage = "[(nsec_el1,nsec_el2,sec_el1,sec_el3)+,off]", + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/armv8.h b/src/target/armv8.h index dfd54ed..af00e52 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -261,6 +261,7 @@ static inline bool is_armv8(struct armv8_common *armv8) #define CPUV8_DBG_WFAR1 0x34 #define CPUV8_DBG_DSCR 0x088 #define CPUV8_DBG_DRCR 0x090 +#define CPUV8_DBG_ECCR 0x098 #define CPUV8_DBG_PRCR 0x310 #define CPUV8_DBG_PRSR 0x314 diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index a5d7d11..081eed2 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -1381,13 +1381,15 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */ case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */ case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/ - case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/ target->debug_reason = DBG_REASON_BREAKPOINT; break; case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */ target->debug_reason = DBG_REASON_WATCHPOINT; break; + case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ + target->debug_reason = DBG_REASON_EXC_CATCH; + break; default: target->debug_reason = DBG_REASON_UNDEFINED; break; diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index f8da8d5..cf08e3a 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -110,8 +110,8 @@ static int avr32_read_core_reg(struct target *target, int num) reg_value = ap7k->core_regs[num]; buf_set_u32(ap7k->core_cache->reg_list[num].value, 0, 32, reg_value); - ap7k->core_cache->reg_list[num].valid = 1; - ap7k->core_cache->reg_list[num].dirty = 0; + ap7k->core_cache->reg_list[num].valid = true; + ap7k->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -129,8 +129,8 @@ static int avr32_write_core_reg(struct target *target, int num) reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32); ap7k->core_regs[num] = reg_value; LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value); - ap7k->core_cache->reg_list[num].valid = 1; - ap7k->core_cache->reg_list[num].dirty = 0; + ap7k->core_cache->reg_list[num].valid = true; + ap7k->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -159,8 +159,8 @@ static int avr32_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -196,8 +196,8 @@ static struct reg_cache *avr32_build_reg_cache(struct target *target) reg_list[i].name = avr32_core_reg_list[i]; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &avr32_reg_type; reg_list[i].arch_info = &arch_info[i]; } diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c index 58e4f61..b23b37f 100644 --- a/src/target/breakpoints.c +++ b/src/target/breakpoints.c @@ -41,7 +41,7 @@ static const char * const watchpoint_rw_strings[] = { /* monotonic counter/id-number for breakpoints and watch points */ static int bpwp_unique_id; -int breakpoint_add_internal(struct target *target, +static int breakpoint_add_internal(struct target *target, target_addr_t address, uint32_t length, enum breakpoint_type type) @@ -60,9 +60,9 @@ int breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_DEBUG("Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", + LOG_ERROR("Duplicate Breakpoint address: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", address, breakpoint->unique_id); - return ERROR_OK; + return ERROR_TARGET_DUPLICATE_BREAKPOINT; } breakpoint_p = &breakpoint->next; breakpoint = breakpoint->next; @@ -108,7 +108,7 @@ fail: return ERROR_OK; } -int context_breakpoint_add_internal(struct target *target, +static int context_breakpoint_add_internal(struct target *target, uint32_t asid, uint32_t length, enum breakpoint_type type) @@ -126,9 +126,9 @@ int context_breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_DEBUG("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", + LOG_ERROR("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", asid, breakpoint->unique_id); - return -1; + return ERROR_TARGET_DUPLICATE_BREAKPOINT; } breakpoint_p = &breakpoint->next; breakpoint = breakpoint->next; @@ -160,7 +160,7 @@ int context_breakpoint_add_internal(struct target *target, return ERROR_OK; } -int hybrid_breakpoint_add_internal(struct target *target, +static int hybrid_breakpoint_add_internal(struct target *target, target_addr_t address, uint32_t asid, uint32_t length, @@ -178,13 +178,13 @@ int hybrid_breakpoint_add_internal(struct target *target, * breakpoint" ... check all the parameters before * succeeding. */ - LOG_DEBUG("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", + LOG_ERROR("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %" PRIu32 ")", asid, breakpoint->unique_id); - return -1; + return ERROR_TARGET_DUPLICATE_BREAKPOINT; } else if ((breakpoint->address == address) && (breakpoint->asid == 0)) { - LOG_DEBUG("Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", + LOG_ERROR("Duplicate Breakpoint IVA: " TARGET_ADDR_FMT " (BP %" PRIu32 ")", address, breakpoint->unique_id); - return -1; + return ERROR_TARGET_DUPLICATE_BREAKPOINT; } breakpoint_p = &breakpoint->next; @@ -243,6 +243,7 @@ int breakpoint_add(struct target *target, } else return breakpoint_add_internal(target, address, length, type); } + int context_breakpoint_add(struct target *target, uint32_t asid, uint32_t length, @@ -264,6 +265,7 @@ int context_breakpoint_add(struct target *target, } else return context_breakpoint_add_internal(target, asid, length, type); } + int hybrid_breakpoint_add(struct target *target, target_addr_t address, uint32_t asid, @@ -312,7 +314,7 @@ static void breakpoint_free(struct target *target, struct breakpoint *breakpoint free(breakpoint); } -int breakpoint_remove_internal(struct target *target, target_addr_t address) +static int breakpoint_remove_internal(struct target *target, target_addr_t address) { struct breakpoint *breakpoint = target->breakpoints; diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 648317e..6eb6aa9 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -56,11 +56,9 @@ #include "arm_opcodes.h" #include "arm_semihosting.h" #include "transport/transport.h" +#include "smp.h" #include <helper/time_support.h> -#define foreach_smp_target(pos, head) \ - for (pos = head; (pos != NULL); pos = pos->next) - static int cortex_a_poll(struct target *target); static int cortex_a_debug_entry(struct target *target); static int cortex_a_restore_context(struct target *target, bool bpwp); @@ -806,15 +804,15 @@ static int cortex_a_internal_restore(struct target *target, int current, * C_MASKINTS in parallel with disabled interrupts can cause * local faults to not be taken. */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); - armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = true; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = true; /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); - armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; + armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = true; + armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = true; } #endif @@ -848,8 +846,8 @@ static int cortex_a_internal_restore(struct target *target, int current, } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); buf_set_u32(arm->pc->value, 0, 32, resume_pc); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; /* restore dpm_mode at system halt */ arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); @@ -2833,15 +2831,15 @@ static int cortex_a_init_arch_info(struct target *target, /* REVISIT v7a setup should be in a v7a-specific routine */ armv7a_init_arch_info(target, armv7a); - target_register_timer_callback(cortex_a_handle_target_request, 1, 1, target); + target_register_timer_callback(cortex_a_handle_target_request, 1, + TARGET_TIMER_TYPE_PERIODIC, target); return ERROR_OK; } static int cortex_a_target_create(struct target *target, Jim_Interp *interp) { - struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common)); - cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; + struct cortex_a_common *cortex_a; struct adiv5_private_config *pc; if (target->private_config == NULL) @@ -2849,8 +2847,13 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp) pc = (struct adiv5_private_config *)target->private_config; + cortex_a = calloc(1, sizeof(struct cortex_a_common)); + if (cortex_a == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; cortex_a->armv7a_common.is_armv7r = false; - cortex_a->armv7a_common.arm.arm_vfp_version = ARM_VFP_V3; return cortex_a_init_arch_info(target, cortex_a, pc->dap); @@ -2858,14 +2861,19 @@ static int cortex_a_target_create(struct target *target, Jim_Interp *interp) static int cortex_r4_target_create(struct target *target, Jim_Interp *interp) { - struct cortex_a_common *cortex_a = calloc(1, sizeof(struct cortex_a_common)); - cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; + struct cortex_a_common *cortex_a; struct adiv5_private_config *pc; pc = (struct adiv5_private_config *)target->private_config; if (adiv5_verify_config(pc) != ERROR_OK) return ERROR_FAIL; + cortex_a = calloc(1, sizeof(struct cortex_a_common)); + if (cortex_a == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + cortex_a->common_magic = CORTEX_A_COMMON_MAGIC; cortex_a->armv7a_common.is_armv7r = true; return cortex_a_init_arch_info(target, cortex_a, pc->dap); @@ -2959,63 +2967,6 @@ COMMAND_HANDLER(cortex_a_handle_dbginit_command) return cortex_a_init_debug_access(target); } -COMMAND_HANDLER(cortex_a_handle_smp_off_command) -{ - struct target *target = get_current_target(CMD_CTX); - /* check target is an smp target */ - struct target_list *head; - struct target *curr; - head = target->head; - target->smp = 0; - if (head != (struct target_list *)NULL) { - while (head != (struct target_list *)NULL) { - curr = head->target; - curr->smp = 0; - head = head->next; - } - /* fixes the target display to the debugger */ - target->gdb_service->target = target; - } - return ERROR_OK; -} - -COMMAND_HANDLER(cortex_a_handle_smp_on_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct target_list *head; - struct target *curr; - head = target->head; - if (head != (struct target_list *)NULL) { - target->smp = 1; - while (head != (struct target_list *)NULL) { - curr = head->target; - curr->smp = 1; - head = head->next; - } - } - return ERROR_OK; -} - -COMMAND_HANDLER(cortex_a_handle_smp_gdb_command) -{ - struct target *target = get_current_target(CMD_CTX); - int retval = ERROR_OK; - struct target_list *head; - head = target->head; - if (head != (struct target_list *)NULL) { - if (CMD_ARGC == 1) { - int coreid = 0; - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); - if (ERROR_OK != retval) - return retval; - target->gdb_service->core[1] = coreid; - - } - command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0] - , target->gdb_service->core[1]); - } - return ERROR_OK; -} COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command) { @@ -3086,25 +3037,6 @@ static const struct command_registration cortex_a_exec_command_handlers[] = { .help = "Initialize core debug", .usage = "", }, - { .name = "smp_off", - .handler = cortex_a_handle_smp_off_command, - .mode = COMMAND_EXEC, - .help = "Stop smp handling", - .usage = "",}, - { - .name = "smp_on", - .handler = cortex_a_handle_smp_on_command, - .mode = COMMAND_EXEC, - .help = "Restart smp handling", - .usage = "", - }, - { - .name = "smp_gdb", - .handler = cortex_a_handle_smp_gdb_command, - .mode = COMMAND_EXEC, - .help = "display/fix current core played to gdb", - .usage = "", - }, { .name = "maskisr", .handler = handle_cortex_a_mask_interrupts_command, @@ -3123,6 +3055,9 @@ static const struct command_registration cortex_a_exec_command_handlers[] = { { .chain = armv7a_mmu_command_handlers, }, + { + .chain = smp_command_handlers, + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 62d3760..d341d45 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -265,7 +265,7 @@ static int cortex_m_endreset_event(struct target *target) return retval; } - cortex_m->fpb_enabled = 1; + cortex_m->fpb_enabled = true; /* Restore FPB registers */ for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) { @@ -1164,7 +1164,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint fp_num++; if (fp_num >= cortex_m->fp_num_code) { LOG_ERROR("Can not find free FPB Comparator!"); - return ERROR_FAIL; + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } breakpoint->set = fp_num + 1; fpcr_value = breakpoint->address | 1; @@ -1180,7 +1180,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision"); return ERROR_FAIL; } - comparator_list[fp_num].used = 1; + comparator_list[fp_num].used = true; comparator_list[fp_num].fpcr_value = fpcr_value; target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); @@ -1195,7 +1195,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint return retval; } - cortex_m->fpb_enabled = 1; + cortex_m->fpb_enabled = true; } } else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; @@ -1254,23 +1254,17 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi LOG_DEBUG("Invalid FP Comparator number in breakpoint"); return ERROR_OK; } - comparator_list[fp_num].used = 0; + comparator_list[fp_num].used = false; comparator_list[fp_num].fpcr_value = 0; target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); } else { /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) { - retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, + retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, + breakpoint->length, 1, breakpoint->orig_instr); - if (retval != ERROR_OK) - return retval; - } else { - retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, - breakpoint->orig_instr); - if (retval != ERROR_OK) - return retval; - } + if (retval != ERROR_OK) + return retval; } breakpoint->set = false; @@ -1279,13 +1273,6 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - struct cortex_m_common *cortex_m = target_to_cm(target); - - if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) { - LOG_INFO("no flash patch comparator unit available for hardware breakpoint"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - if (breakpoint->length == 3) { LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request"); breakpoint->length = 2; @@ -1296,29 +1283,15 @@ int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if (breakpoint->type == BKPT_HARD) - cortex_m->fp_code_available--; - return cortex_m_set_breakpoint(target, breakpoint); } int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { - struct cortex_m_common *cortex_m = target_to_cm(target); - - /* REVISIT why check? FPB can be updated with core running ... */ - if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - if (breakpoint->set) - cortex_m_unset_breakpoint(target, breakpoint); - - if (breakpoint->type == BKPT_HARD) - cortex_m->fp_code_available++; + if (!breakpoint->set) + return ERROR_OK; - return ERROR_OK; + return cortex_m_unset_breakpoint(target, breakpoint); } int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint) @@ -1351,7 +1324,7 @@ int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint LOG_ERROR("Can not find free DWT Comparator"); return ERROR_FAIL; } - comparator->used = 1; + comparator->used = true; watchpoint->set = dwt_num + 1; comparator->comp = watchpoint->address; @@ -1408,7 +1381,7 @@ int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoi } comparator = cortex_m->dwt_comparator_list + dwt_num; - comparator->used = 0; + comparator->used = false; comparator->function = 0; target_write_u32(target, comparator->dwt_comparator_address + 8, comparator->function); @@ -2127,7 +2100,6 @@ int cortex_m_examine(struct target *target) /* bits [14:12] and [7:4] */ cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); cortex_m->fp_num_lit = (fpcr >> 8) & 0xF; - cortex_m->fp_code_available = cortex_m->fp_num_code; /* Detect flash patch revision, see RM DDI 0403E.b page C1-817. Revision is zero base, fp_rev == 1 means Rev.2 ! */ cortex_m->fp_rev = (fpcr >> 28) & 0xf; @@ -2269,7 +2241,8 @@ static int cortex_m_init_arch_info(struct target *target, armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32; armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32; - target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target); + target_register_timer_callback(cortex_m_handle_target_request, 1, + TARGET_TIMER_TYPE_PERIODIC, target); return ERROR_OK; } diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 22d9735..4b20746 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -136,14 +136,14 @@ #define FPCR_REPLACE_BKPT_BOTH (3 << 30) struct cortex_m_fp_comparator { - int used; + bool used; int type; uint32_t fpcr_value; uint32_t fpcr_address; }; struct cortex_m_dwt_comparator { - int used; + bool used; uint32_t comp; uint32_t mask; uint32_t function; @@ -172,9 +172,8 @@ struct cortex_m_common { /* Flash Patch and Breakpoint (FPB) */ int fp_num_lit; int fp_num_code; - int fp_code_available; int fp_rev; - int fpb_enabled; + bool fpb_enabled; struct cortex_m_fp_comparator *fp_comparator_list; /* Data Watchpoint and Trace (DWT) */ diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index 8991616..5f13384 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -384,8 +384,8 @@ static int dsp563xx_read_core_reg(struct target *target, int num) reg_value = dsp563xx->core_regs[num]; buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value); - dsp563xx->core_cache->reg_list[num].valid = 1; - dsp563xx->core_cache->reg_list[num].dirty = 0; + dsp563xx->core_cache->reg_list[num].valid = true; + dsp563xx->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -400,8 +400,8 @@ static int dsp563xx_write_core_reg(struct target *target, int num) reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32); dsp563xx->core_regs[num] = reg_value; - dsp563xx->core_cache->reg_list[num].valid = 1; - dsp563xx->core_cache->reg_list[num].dirty = 0; + dsp563xx->core_cache->reg_list[num].valid = true; + dsp563xx->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -432,8 +432,8 @@ static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, reg->size, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -473,8 +473,8 @@ static void dsp563xx_build_reg_cache(struct target *target) reg_list[i].name = dsp563xx_regs[i].name; reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */ reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &dsp563xx_reg_type; reg_list[i].arch_info = &arch_info[i]; } @@ -508,7 +508,7 @@ static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, if (err != ERROR_OK) return err; /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true; return ERROR_OK; } @@ -534,7 +534,7 @@ static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask return err; /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true; return ERROR_OK; } @@ -745,7 +745,7 @@ static int dsp563xx_read_register(struct target *target, int num, int force) struct dsp563xx_core_reg *arch_info; if (force) - dsp563xx->core_cache->reg_list[num].valid = 0; + dsp563xx->core_cache->reg_list[num].valid = false; if (!dsp563xx->core_cache->reg_list[num].valid) { arch_info = dsp563xx->core_cache->reg_list[num].arch_info; @@ -795,7 +795,7 @@ static int dsp563xx_write_register(struct target *target, int num, int force) struct dsp563xx_core_reg *arch_info; if (force) - dsp563xx->core_cache->reg_list[num].dirty = 1; + dsp563xx->core_cache->reg_list[num].dirty = true; if (dsp563xx->core_cache->reg_list[num].dirty) { arch_info = dsp563xx->core_cache->reg_list[num].arch_info; @@ -884,8 +884,8 @@ static void dsp563xx_invalidate_x_context(struct target *target, if ((arch_info->instr_mask >= addr_start) && (arch_info->instr_mask <= addr_end)) { - dsp563xx->core_cache->reg_list[i].valid = 0; - dsp563xx->core_cache->reg_list[i].dirty = 0; + dsp563xx->core_cache->reg_list[i].valid = false; + dsp563xx->core_cache->reg_list[i].dirty = false; } } } @@ -985,7 +985,7 @@ static int dsp563xx_debug_init(struct target *target) err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr); if (err != ERROR_OK) return err; - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = true; } err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0); @@ -1007,7 +1007,7 @@ static int dsp563xx_debug_init(struct target *target) if (err != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = true; if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info; @@ -1015,7 +1015,7 @@ static int dsp563xx_debug_init(struct target *target) if (err != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = true; if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info; @@ -1023,7 +1023,7 @@ static int dsp563xx_debug_init(struct target *target) if (err != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = true; if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info; @@ -1031,7 +1031,7 @@ static int dsp563xx_debug_init(struct target *target) if (err != ERROR_OK) return err; } - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = true; err = dsp563xx_save_context(target); if (err != ERROR_OK) @@ -1552,9 +1552,9 @@ static int dsp563xx_read_memory_core(struct target *target, dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1); /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true; /* r1 is no longer valid on target */ - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true; x = count; b = buffer; @@ -1734,9 +1734,9 @@ static int dsp563xx_write_memory_core(struct target *target, dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R1); /* r0 is no longer valid on target */ - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = true; /* r1 is no longer valid on target */ - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = 1; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R1].dirty = true; x = count; b = buffer; diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 7232ef1..61ee8bb 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -205,8 +205,8 @@ struct reg_cache *embeddedice_build_reg_cache(struct target *target, for (i = 0; i < num_regs; i++) { reg_list[i].name = eice_regs[i].name; reg_list[i].size = eice_regs[i].width; - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; reg_list[i].type = &eice_reg_type; @@ -470,8 +470,8 @@ void embeddedice_set_reg(struct reg *reg, uint32_t value) embeddedice_write_reg(reg, value); buf_set_u32(reg->value, 0, reg->size, value); - reg->valid = 1; - reg->dirty = 0; + reg->valid = true; + reg->dirty = false; } diff --git a/src/target/etb.c b/src/target/etb.c index dc25844..98a90a5 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -143,8 +143,8 @@ struct reg_cache *etb_build_reg_cache(struct etb *etb) for (i = 0; i < num_regs; i++) { reg_list[i].name = etb_reg_list[i]; reg_list[i].size = 32; - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; reg_list[i].type = &etb_reg_type; @@ -272,8 +272,8 @@ static int etb_set_reg(struct reg *reg, uint32_t value) } buf_set_u32(reg->value, 0, reg->size, value); - reg->valid = 1; - reg->dirty = 0; + reg->valid = true; + reg->dirty = false; return ERROR_OK; } diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 21963e5..4a6c6dc 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -532,8 +532,8 @@ static int feroceon_bulk_write_memory(struct target *target, /* set up target address in r0 */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address); - arm->core_cache->reg_list[0].valid = 1; - arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].valid = true; + arm->core_cache->reg_list[0].dirty = true; arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); @@ -575,12 +575,12 @@ static int feroceon_bulk_write_memory(struct target *target, /* restore target state */ for (i = 0; i <= 5; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); - arm->core_cache->reg_list[i].valid = 1; - arm->core_cache->reg_list[i].dirty = 1; + arm->core_cache->reg_list[i].valid = true; + arm->core_cache->reg_list[i].dirty = true; } buf_set_u32(arm->pc->value, 0, 32, save[i]); - arm->pc->valid = 1; - arm->pc->dirty = 1; + arm->pc->valid = true; + arm->pc->dirty = true; arm->core_state = core_state; return retval; diff --git a/src/target/hla_target.c b/src/target/hla_target.c index 4f97eb9..60ed7d6 100644 --- a/src/target/hla_target.c +++ b/src/target/hla_target.c @@ -346,7 +346,8 @@ static int adapter_init_arch_info(struct target *target, armv7m->examine_debug_reason = adapter_examine_debug_reason; armv7m->stlink = true; - target_register_timer_callback(hl_handle_target_request, 1, 1, target); + target_register_timer_callback(hl_handle_target_request, 1, + TARGET_TIMER_TYPE_PERIODIC, target); return ERROR_OK; } diff --git a/src/target/lakemont.c b/src/target/lakemont.c index b81213e..31882b8 100644 --- a/src/target/lakemont.c +++ b/src/target/lakemont.c @@ -322,8 +322,8 @@ static int restore_context(struct target *t) } for (i = 0; i < (x86_32->cache->num_regs); i++) { - x86_32->cache->reg_list[i].dirty = 0; - x86_32->cache->reg_list[i].valid = 0; + x86_32->cache->reg_list[i].dirty = false; + x86_32->cache->reg_list[i].valid = false; } return err; } @@ -357,8 +357,8 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf) if (check_not_halted(t)) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -405,8 +405,8 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t) reg_list[i].name = regs[i].name; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &lakemont_reg_type; reg_list[i].arch_info = &arch_info[i]; @@ -667,8 +667,8 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach *regval = buf_get_u32(scan.out, 0, 32); if (cache) { buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval); - x86_32->cache->reg_list[reg].valid = 1; - x86_32->cache->reg_list[reg].dirty = 0; + x86_32->cache->reg_list[reg].valid = true; + x86_32->cache->reg_list[reg].dirty = false; } LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32, x86_32->cache->reg_list[reg].name, @@ -709,8 +709,8 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach /* we are writing from the cache so ensure we reset flags */ if (cache) { - x86_32->cache->reg_list[reg].dirty = 0; - x86_32->cache->reg_list[reg].valid = 0; + x86_32->cache->reg_list[reg].dirty = false; + x86_32->cache->reg_list[reg].valid = false; } return ERROR_OK; } @@ -947,8 +947,8 @@ int lakemont_poll(struct target *t) * breakpoint instruction. This needs to be corrected. */ buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1); - x86_32->cache->reg_list[EIP].dirty = 1; - x86_32->cache->reg_list[EIP].valid = 1; + x86_32->cache->reg_list[EIP].dirty = true; + x86_32->cache->reg_list[EIP].valid = true; LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1); } else { /* it's not a hardware breakpoint (checked already in DR6 state) diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c index 3a2d4b7..584e19d 100644 --- a/src/target/mem_ap.c +++ b/src/target/mem_ap.c @@ -31,7 +31,7 @@ struct mem_ap { static int mem_ap_target_create(struct target *target, Jim_Interp *interp) { - struct mem_ap *mem_ap = calloc(1, sizeof(struct mem_ap)); + struct mem_ap *mem_ap; struct adiv5_private_config *pc; pc = (struct adiv5_private_config *)target->private_config; @@ -43,6 +43,12 @@ static int mem_ap_target_create(struct target *target, Jim_Interp *interp) return ERROR_FAIL; } + mem_ap = calloc(1, sizeof(struct mem_ap)); + if (mem_ap == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + mem_ap->ap_num = pc->ap_num; mem_ap->arm.common_magic = ARM_COMMON_MAGIC; mem_ap->arm.dap = pc->dap; diff --git a/src/target/mips32.c b/src/target/mips32.c index 9ac2507..d9d8ba9 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -190,8 +190,8 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -208,8 +208,8 @@ static int mips32_read_core_reg(struct target *target, unsigned int num) reg_value = mips32->core_regs[num]; buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value); - mips32->core_cache->reg_list[num].valid = 1; - mips32->core_cache->reg_list[num].dirty = 0; + mips32->core_cache->reg_list[num].valid = true; + mips32->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -227,8 +227,8 @@ static int mips32_write_core_reg(struct target *target, unsigned int num) reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32); mips32->core_regs[num] = reg_value; LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); - mips32->core_cache->reg_list[num].valid = 1; - mips32->core_cache->reg_list[num].dirty = 0; + mips32->core_cache->reg_list[num].valid = true; + mips32->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -336,12 +336,12 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) { reg_list[i].value = mips32_gdb_dummy_fp_value; - reg_list[i].valid = 1; + reg_list[i].valid = true; reg_list[i].arch_info = NULL; register_init_dummy(®_list[i]); } else { reg_list[i].value = calloc(1, 4); - reg_list[i].valid = 0; + reg_list[i].valid = false; reg_list[i].type = &mips32_reg_type; reg_list[i].arch_info = &arch_info[i]; @@ -352,7 +352,7 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) LOG_ERROR("unable to allocate reg type list"); } - reg_list[i].dirty = 0; + reg_list[i].dirty = false; reg_list[i].group = mips32_regs[i].group; reg_list[i].number = i; @@ -532,8 +532,8 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, mips32->core_cache->reg_list[i].name, context[i]); buf_set_u32(mips32->core_cache->reg_list[i].value, 0, 32, context[i]); - mips32->core_cache->reg_list[i].valid = 1; - mips32->core_cache->reg_list[i].dirty = 1; + mips32->core_cache->reg_list[i].valid = true; + mips32->core_cache->reg_list[i].dirty = true; } } diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index 888c847..e31ba63 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -30,7 +30,7 @@ #define MIPS32_PRACC_FASTDATA_AREA 0xFF200000 #define MIPS32_PRACC_FASTDATA_SIZE 16 #define MIPS32_PRACC_BASE_ADDR 0xFF200000 -#define MIPS32_PRACC_TEXT 0xFF200200 +#define MIPS32_PRACC_TEXT 0xFF200200 #define MIPS32_PRACC_PARAM_OUT 0xFF202000 #define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16) @@ -38,10 +38,10 @@ #define PRACC_MAX_INSTRUCTIONS (PRACC_MAX_CODE / 4) #define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR) -#define MIPS32_FASTDATA_HANDLER_SIZE 0x80 -#define UPPER16(uint32_t) (uint32_t >> 16) -#define LOWER16(uint32_t) (uint32_t & 0xFFFF) -#define NEG16(v) (((~(v)) + 1) & 0xFFFF) +#define MIPS32_FASTDATA_HANDLER_SIZE 0x80 +#define UPPER16(addr) ((addr) >> 16) +#define LOWER16(addr) ((addr) & 0xFFFF) +#define NEG16(v) (((~(v)) + 1) & 0xFFFF) #define SWAP16(v) ((LOWER16(v) << 16) | (UPPER16(v))) /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/ diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 20c707b..653d732 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -33,6 +33,7 @@ #include "mips32_dmaacc.h" #include "target_type.h" #include "register.h" +#include "smp.h" static void mips_m4k_enable_breakpoints(struct target *target); static void mips_m4k_enable_watchpoints(struct target *target); @@ -458,8 +459,8 @@ static int mips_m4k_internal_restore(struct target *target, int current, if (!current) { mips_m4k_isa_filter(mips32->isa_imp, &address); buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); - mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; - mips32->core_cache->reg_list[MIPS32_PC].valid = 1; + mips32->core_cache->reg_list[MIPS32_PC].dirty = true; + mips32->core_cache->reg_list[MIPS32_PC].valid = true; } if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */ @@ -552,8 +553,8 @@ static int mips_m4k_step(struct target *target, int current, if (!current) { mips_m4k_isa_filter(mips32->isa_imp, &address); buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); - mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; - mips32->core_cache->reg_list[MIPS32_PC].valid = 1; + mips32->core_cache->reg_list[MIPS32_PC].dirty = true; + mips32->core_cache->reg_list[MIPS32_PC].valid = true; } /* the front-end may request us not to handle breakpoints */ @@ -1333,64 +1334,6 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command) return ERROR_OK; } -COMMAND_HANDLER(mips_m4k_handle_smp_off_command) -{ - struct target *target = get_current_target(CMD_CTX); - /* check target is an smp target */ - struct target_list *head; - struct target *curr; - head = target->head; - target->smp = 0; - if (head != (struct target_list *)NULL) { - while (head != (struct target_list *)NULL) { - curr = head->target; - curr->smp = 0; - head = head->next; - } - /* fixes the target display to the debugger */ - target->gdb_service->target = target; - } - return ERROR_OK; -} - -COMMAND_HANDLER(mips_m4k_handle_smp_on_command) -{ - struct target *target = get_current_target(CMD_CTX); - struct target_list *head; - struct target *curr; - head = target->head; - if (head != (struct target_list *)NULL) { - target->smp = 1; - while (head != (struct target_list *)NULL) { - curr = head->target; - curr->smp = 1; - head = head->next; - } - } - return ERROR_OK; -} - -COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command) -{ - struct target *target = get_current_target(CMD_CTX); - int retval = ERROR_OK; - struct target_list *head; - head = target->head; - if (head != (struct target_list *)NULL) { - if (CMD_ARGC == 1) { - int coreid = 0; - COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); - if (ERROR_OK != retval) - return retval; - target->gdb_service->core[1] = coreid; - - } - command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0] - , target->gdb_service->core[1]); - } - return ERROR_OK; -} - COMMAND_HANDLER(mips_m4k_handle_scan_delay_command) { struct target *target = get_current_target(CMD_CTX); @@ -1423,33 +1366,15 @@ static const struct command_registration mips_m4k_exec_command_handlers[] = { .help = "display/modify cp0 register", }, { - .name = "smp_off", - .handler = mips_m4k_handle_smp_off_command, - .mode = COMMAND_EXEC, - .help = "Stop smp handling", - .usage = "",}, - - { - .name = "smp_on", - .handler = mips_m4k_handle_smp_on_command, - .mode = COMMAND_EXEC, - .help = "Restart smp handling", - .usage = "", - }, - { - .name = "smp_gdb", - .handler = mips_m4k_handle_smp_gdb_command, - .mode = COMMAND_EXEC, - .help = "display/fix current core played to gdb", - .usage = "", - }, - { .name = "scan_delay", .handler = mips_m4k_handle_scan_delay_command, .mode = COMMAND_ANY, .help = "display/set scan delay in nano seconds", .usage = "[value]", }, + { + .chain = smp_command_handlers, + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c index 6cd53f4..6fb764a 100644 --- a/src/target/openrisc/jsp_server.c +++ b/src/target/openrisc/jsp_server.c @@ -101,7 +101,8 @@ static int jsp_new_connection(struct connection *connection) jsp_service->connection = connection; - int retval = target_register_timer_callback(&jsp_poll_read, 1, 1, jsp_service); + int retval = target_register_timer_callback(&jsp_poll_read, 1, + TARGET_TIMER_TYPE_PERIODIC, jsp_service); if (ERROR_OK != retval) return retval; diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c index bcb648c..34b1b07 100644 --- a/src/target/openrisc/or1k.c +++ b/src/target/openrisc/or1k.c @@ -424,8 +424,8 @@ static int or1k_read_core_reg(struct target *target, int num) reg_value = or1k->core_regs[num]; buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value); LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value); - or1k->core_cache->reg_list[num].valid = 1; - or1k->core_cache->reg_list[num].dirty = 0; + or1k->core_cache->reg_list[num].valid = true; + or1k->core_cache->reg_list[num].dirty = false; } else { /* This is an spr, always read value from HW */ int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, @@ -453,8 +453,8 @@ static int or1k_write_core_reg(struct target *target, int num) uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32); or1k->core_regs[num] = reg_value; LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value); - or1k->core_cache->reg_list[num].valid = 1; - or1k->core_cache->reg_list[num].dirty = 0; + or1k->core_cache->reg_list[num].valid = true; + or1k->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -487,8 +487,8 @@ static int or1k_set_core_reg(struct reg *reg, uint8_t *buf) if (or1k_reg->list_num < OR1KNUMCOREREGS) { buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; } else { /* This is an spr, write it to the HW */ int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag, @@ -541,8 +541,8 @@ static struct reg_cache *or1k_build_reg_cache(struct target *target) reg_list[i].group = or1k_core_reg_list_arch_info[i].group; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &or1k_reg_type; reg_list[i].arch_info = &arch_info[i]; reg_list[i].number = i; diff --git a/src/target/register.c b/src/target/register.c index dee25b2..4ddda6e 100644 --- a/src/target/register.c +++ b/src/target/register.c @@ -111,8 +111,8 @@ void register_cache_invalidate(struct reg_cache *cache) for (unsigned n = cache->num_regs; n != 0; n--, reg++) { if (reg->exist == false) continue; - reg->valid = 0; - reg->dirty = 0; + reg->valid = false; + reg->dirty = false; } } @@ -123,8 +123,8 @@ static int register_get_dummy_core_reg(struct reg *reg) static int register_set_dummy_core_reg(struct reg *reg, uint8_t *buf) { - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 5cdcc01..2fc3757 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2004,6 +2004,11 @@ const struct command_registration riscv_command_handlers[] = { COMMAND_REGISTRATION_DONE }; +unsigned riscv_address_bits(struct target *target) +{ + return riscv_xlen(target); +} + struct target_type riscv_target = { .name = "riscv", @@ -2040,7 +2045,9 @@ struct target_type riscv_target = { .run_algorithm = riscv_run_algorithm, - .commands = riscv_command_handlers + .commands = riscv_command_handlers, + + .address_bits = riscv_address_bits }; /*** RISC-V Interface ***/ diff --git a/src/target/smp.c b/src/target/smp.c index bdf81a0..f42d8ab 100644 --- a/src/target/smp.c +++ b/src/target/smp.c @@ -96,3 +96,110 @@ int gdb_write_smp_packet(struct connection *connection, return retval; } + +COMMAND_HANDLER(default_handle_smp_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct target_list *head; + + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (!CMD_ARGC) { + command_print(CMD_CTX, "%s", target->smp ? "on" : "off"); + return ERROR_OK; + } + + if (!strcmp(CMD_ARGV[0], "on")) { + foreach_smp_target(head, target->head) + head->target->smp = 1; + + return ERROR_OK; + } + + if (!strcmp(CMD_ARGV[0], "off")) { + foreach_smp_target(head, target->head) + head->target->smp = 0; + + /* fixes the target display to the debugger */ + if (target->head) + target->gdb_service->target = target; + + return ERROR_OK; + } + + return ERROR_COMMAND_SYNTAX_ERROR; +} + +COMMAND_HANDLER(deprecated_handle_smp_on_command) +{ + const char *argv[] = {"on", NULL}; + + LOG_WARNING("\'smp_on\' is deprecated, please use \'smp on\' instead."); + CMD_ARGC = 1; + CMD_ARGV = argv; + return CALL_COMMAND_HANDLER(default_handle_smp_command); +} + +COMMAND_HANDLER(deprecated_handle_smp_off_command) +{ + const char *argv[] = {"off", NULL}; + + LOG_WARNING("\'smp_off\' is deprecated, please use \'smp off\' instead."); + CMD_ARGC = 1; + CMD_ARGV = argv; + return CALL_COMMAND_HANDLER(default_handle_smp_command); +} + +COMMAND_HANDLER(handle_smp_gdb_command) +{ + struct target *target = get_current_target(CMD_CTX); + int retval = ERROR_OK; + struct target_list *head; + head = target->head; + if (head != (struct target_list *)NULL) { + if (CMD_ARGC == 1) { + int coreid = 0; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); + if (ERROR_OK != retval) + return retval; + target->gdb_service->core[1] = coreid; + + } + command_print(CMD_CTX, "gdb coreid %" PRId32 " -> %" PRId32, target->gdb_service->core[0] + , target->gdb_service->core[1]); + } + return ERROR_OK; +} + +const struct command_registration smp_command_handlers[] = { + { + .name = "smp", + .handler = default_handle_smp_command, + .mode = COMMAND_EXEC, + .help = "smp handling", + .usage = "[on|off]", + }, + { + .name = "smp_on", + .handler = deprecated_handle_smp_on_command, + .mode = COMMAND_EXEC, + .help = "Restart smp handling", + .usage = "", + }, + { + .name = "smp_off", + .handler = deprecated_handle_smp_off_command, + .mode = COMMAND_EXEC, + .help = "Stop smp handling", + .usage = "", + }, + { + .name = "smp_gdb", + .handler = handle_smp_gdb_command, + .mode = COMMAND_EXEC, + .help = "display/fix current core played to gdb", + .usage = "", + }, + COMMAND_REGISTRATION_DONE +}; diff --git a/src/target/smp.h b/src/target/smp.h index c3e6c6c..f024b40 100644 --- a/src/target/smp.h +++ b/src/target/smp.h @@ -21,6 +21,11 @@ #include "server/server.h" +#define foreach_smp_target(pos, head) \ + for (pos = head; (pos != NULL); pos = pos->next) + +extern const struct command_registration smp_command_handlers[]; + int gdb_read_smp_packet(struct connection *connection, char const *packet, int packet_size); int gdb_write_smp_packet(struct connection *connection, diff --git a/src/target/startup.tcl b/src/target/startup.tcl index cf844e1..4d4426f 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -221,3 +221,9 @@ proc cortex_a8 args { echo "DEPRECATED! use 'cortex_a' not 'cortex_a8'" eval cortex_a $args } + +# deprecated ftdi cmds +proc ftdi_location args { + echo "DEPRECATED! use 'adapter usb location' not 'ftdi_location'" + eval adapter usb location $args +} diff --git a/src/target/target.c b/src/target/target.c index 036c065..a99e981 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -251,6 +251,7 @@ static const Jim_Nvp nvp_target_debug_reason[] = { { .name = "single-step" , .value = DBG_REASON_SINGLESTEP }, { .name = "target-not-halted" , .value = DBG_REASON_NOTHALTED }, { .name = "program-exit" , .value = DBG_REASON_EXIT }, + { .name = "exception-catch" , .value = DBG_REASON_EXC_CATCH }, { .name = "undefined" , .value = DBG_REASON_UNDEFINED }, { .name = NULL, .value = -1 }, }; @@ -1267,6 +1268,22 @@ int target_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, return target->type->gdb_fileio_end(target, retcode, fileio_errno, ctrl_c); } +target_addr_t target_address_max(struct target *target) +{ + unsigned bits = target_address_bits(target); + if (sizeof(target_addr_t) * 8 == bits) + return (target_addr_t) -1; + else + return (((target_addr_t) 1) << bits) - 1; +} + +unsigned target_address_bits(struct target *target) +{ + if (target->type->address_bits) + return target->type->address_bits(target); + return 32; +} + int target_profiling(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds) { @@ -1368,7 +1385,7 @@ static int target_init(struct command_context *cmd_ctx) return retval; retval = target_register_timer_callback(&handle_target, - polling_interval, 1, cmd_ctx->interp); + polling_interval, TARGET_TIMER_TYPE_PERIODIC, cmd_ctx->interp); if (ERROR_OK != retval) return retval; @@ -1471,7 +1488,8 @@ int target_register_trace_callback(int (*callback)(struct target *target, return ERROR_OK; } -int target_register_timer_callback(int (*callback)(void *priv), int time_ms, int periodic, void *priv) +int target_register_timer_callback(int (*callback)(void *priv), + unsigned int time_ms, enum target_timer_type type, void *priv) { struct target_timer_callback **callbacks_p = &target_timer_callbacks; @@ -1486,7 +1504,7 @@ int target_register_timer_callback(int (*callback)(void *priv), int time_ms, int (*callbacks_p) = malloc(sizeof(struct target_timer_callback)); (*callbacks_p)->callback = callback; - (*callbacks_p)->periodic = periodic; + (*callbacks_p)->type = type; (*callbacks_p)->time_ms = time_ms; (*callbacks_p)->removed = false; @@ -1637,7 +1655,7 @@ static int target_call_timer_callback(struct target_timer_callback *cb, { cb->callback(cb->priv); - if (cb->periodic) + if (cb->type == TARGET_TIMER_TYPE_PERIODIC) return target_timer_callback_periodic_restart(cb, now); return target_unregister_timer_callback(cb->callback, cb->priv); @@ -1671,7 +1689,7 @@ static int target_call_timer_callbacks_check_time(int checktime) } bool call_it = (*callback)->callback && - ((!checktime && (*callback)->periodic) || + ((!checktime && (*callback)->type == TARGET_TIMER_TYPE_PERIODIC) || timeval_compare(&now, &(*callback)->when) >= 0); if (call_it) @@ -3744,38 +3762,31 @@ static int handle_bp_command_set(struct command_context *cmd_ctx, if (asid == 0) { retval = breakpoint_add(target, addr, length, hw); + /* error is always logged in breakpoint_add(), do not print it again */ if (ERROR_OK == retval) command_print(cmd_ctx, "breakpoint set at " TARGET_ADDR_FMT "", addr); - else { - LOG_ERROR("Failure setting breakpoint, the same address(IVA) is already used"); - return retval; - } + } else if (addr == 0) { if (target->type->add_context_breakpoint == NULL) { - LOG_WARNING("Context breakpoint not available"); - return ERROR_OK; + LOG_ERROR("Context breakpoint not available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } retval = context_breakpoint_add(target, asid, length, hw); + /* error is always logged in context_breakpoint_add(), do not print it again */ if (ERROR_OK == retval) command_print(cmd_ctx, "Context breakpoint set at 0x%8.8" PRIx32 "", asid); - else { - LOG_ERROR("Failure setting breakpoint, the same address(CONTEXTID) is already used"); - return retval; - } + } else { if (target->type->add_hybrid_breakpoint == NULL) { - LOG_WARNING("Hybrid breakpoint not available"); - return ERROR_OK; + LOG_ERROR("Hybrid breakpoint not available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } retval = hybrid_breakpoint_add(target, addr, asid, length, hw); + /* error is always logged in hybrid_breakpoint_add(), do not print it again */ if (ERROR_OK == retval) command_print(cmd_ctx, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid); - else { - LOG_ERROR("Failure setting breakpoint, the same address is already used"); - return retval; - } } - return ERROR_OK; + return retval; } COMMAND_HANDLER(handle_bp_command) diff --git a/src/target/target.h b/src/target/target.h index 7c9db30..8dde03d 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -84,7 +84,8 @@ enum target_debug_reason { DBG_REASON_SINGLESTEP = 4, DBG_REASON_NOTHALTED = 5, DBG_REASON_EXIT = 6, - DBG_REASON_UNDEFINED = 7, + DBG_REASON_EXC_CATCH = 7, + DBG_REASON_UNDEFINED = 8, }; enum target_endianness { @@ -290,7 +291,6 @@ struct target_event_action { enum target_event event; struct Jim_Interp *interp; struct Jim_Obj *body; - int has_percent; struct target_event_action *next; }; @@ -314,10 +314,15 @@ struct target_trace_callback { int (*callback)(struct target *target, size_t len, uint8_t *data, void *priv); }; +enum target_timer_type { + TARGET_TIMER_TYPE_ONESHOT, + TARGET_TIMER_TYPE_PERIODIC +}; + struct target_timer_callback { int (*callback)(void *priv); - int time_ms; - int periodic; + unsigned int time_ms; + enum target_timer_type type; bool removed; struct timeval when; void *priv; @@ -385,7 +390,7 @@ int target_call_trace_callbacks(struct target *target, size_t len, uint8_t *data * or much more rarely than specified */ int target_register_timer_callback(int (*callback)(void *priv), - int time_ms, int periodic, void *priv); + unsigned int time_ms, enum target_timer_type type, void *priv); int target_unregister_timer_callback(int (*callback)(void *priv), void *priv); int target_call_timer_callbacks(void); /** @@ -646,7 +651,17 @@ int target_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fi */ int target_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c); +/** + * Return the highest accessible address for this target. + */ +target_addr_t target_address_max(struct target *target); +/** + * Return the number of address bits this target supports. + * + * This routine is a wrapper for target->type->address_bits. + */ +unsigned target_address_bits(struct target *target); /** Return the *name* of this targets current state */ const char *target_state_name(struct target *target); @@ -735,6 +750,7 @@ void target_handle_event(struct target *t, enum target_event e); #define ERROR_TARGET_TRANSLATION_FAULT (-309) #define ERROR_TARGET_NOT_RUNNING (-310) #define ERROR_TARGET_NOT_EXAMINED (-311) +#define ERROR_TARGET_DUPLICATE_BREAKPOINT (-312) extern bool get_target_reset_nag(void); diff --git a/src/target/target_type.h b/src/target/target_type.h index b825c7b..4bdea72 100644 --- a/src/target/target_type.h +++ b/src/target/target_type.h @@ -291,6 +291,11 @@ struct target_type { */ int (*profiling)(struct target *target, uint32_t *samples, uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds); + + /* Return the number of address bits this target supports. This will + * typically be 32 for 32-bit targets, and 64 for 64-bit targets. If not + * implemented, it's assumed to be 32. */ + unsigned (*address_bits)(struct target *target); }; #endif /* OPENOCD_TARGET_TARGET_TYPE_H */ diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c index ef4f806..011e7d8 100644 --- a/src/target/x86_32_common.c +++ b/src/target/x86_32_common.c @@ -939,14 +939,14 @@ static int set_debug_regs(struct target *t, uint32_t address, * when we exit PM */ buf_set_u32(x86_32->cache->reg_list[bp_num+DR0].value, 0, 32, address); - x86_32->cache->reg_list[bp_num+DR0].dirty = 1; - x86_32->cache->reg_list[bp_num+DR0].valid = 1; + x86_32->cache->reg_list[bp_num+DR0].dirty = true; + x86_32->cache->reg_list[bp_num+DR0].valid = true; buf_set_u32(x86_32->cache->reg_list[DR6].value, 0, 32, PM_DR6); - x86_32->cache->reg_list[DR6].dirty = 1; - x86_32->cache->reg_list[DR6].valid = 1; + x86_32->cache->reg_list[DR6].dirty = true; + x86_32->cache->reg_list[DR6].valid = true; buf_set_u32(x86_32->cache->reg_list[DR7].value, 0, 32, dr7); - x86_32->cache->reg_list[DR7].dirty = 1; - x86_32->cache->reg_list[DR7].valid = 1; + x86_32->cache->reg_list[DR7].dirty = true; + x86_32->cache->reg_list[DR7].valid = true; return ERROR_OK; } @@ -970,14 +970,14 @@ static int unset_debug_regs(struct target *t, uint8_t bp_num) * when we exit PM */ buf_set_u32(x86_32->cache->reg_list[bp_num+DR0].value, 0, 32, 0); - x86_32->cache->reg_list[bp_num+DR0].dirty = 1; - x86_32->cache->reg_list[bp_num+DR0].valid = 1; + x86_32->cache->reg_list[bp_num+DR0].dirty = true; + x86_32->cache->reg_list[bp_num+DR0].valid = true; buf_set_u32(x86_32->cache->reg_list[DR6].value, 0, 32, PM_DR6); - x86_32->cache->reg_list[DR6].dirty = 1; - x86_32->cache->reg_list[DR6].valid = 1; + x86_32->cache->reg_list[DR6].dirty = true; + x86_32->cache->reg_list[DR6].valid = true; buf_set_u32(x86_32->cache->reg_list[DR7].value, 0, 32, dr7); - x86_32->cache->reg_list[DR7].dirty = 1; - x86_32->cache->reg_list[DR7].valid = 1; + x86_32->cache->reg_list[DR7].dirty = true; + x86_32->cache->reg_list[DR7].valid = true; return ERROR_OK; } diff --git a/src/target/xscale.c b/src/target/xscale.c index 3ac4553..09abd9e 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -212,8 +212,8 @@ static int xscale_read_dcsr(struct target *target) return retval; } - xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0; - xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1; + xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false; + xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true; /* write the register with the value we just read * on this second pass, only the first bit of field0 is guaranteed to be 0) @@ -624,8 +624,8 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br return retval; } - xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0; - xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1; + xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false; + xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true; return ERROR_OK; } @@ -868,21 +868,21 @@ static int xscale_debug_entry(struct target *target) /* move r0 from buffer to register cache */ buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]); - arm->core_cache->reg_list[0].dirty = 1; - arm->core_cache->reg_list[0].valid = 1; + arm->core_cache->reg_list[0].dirty = true; + arm->core_cache->reg_list[0].valid = true; LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ buf_set_u32(arm->pc->value, 0, 32, buffer[1]); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); - arm->core_cache->reg_list[i].dirty = 1; - arm->core_cache->reg_list[i].valid = 1; + arm->core_cache->reg_list[i].dirty = true; + arm->core_cache->reg_list[i].valid = true; LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } @@ -920,7 +920,7 @@ static int xscale_debug_entry(struct target *target) /* mark xscale regs invalid to ensure they are retrieved from the * debug handler if requested */ for (i = 0; i < xscale->reg_cache->num_regs; i++) - xscale->reg_cache->reg_list[i].valid = 0; + xscale->reg_cache->reg_list[i].valid = false; /* examine debug reason */ xscale_read_dcsr(target); @@ -2423,8 +2423,8 @@ static int xscale_get_reg(struct reg *reg) xscale_read_tx(target, 1); buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32); - reg->dirty = 0; - reg->valid = 1; + reg->dirty = false; + reg->valid = true; } return ERROR_OK; @@ -2890,8 +2890,8 @@ static void xscale_build_reg_cache(struct target *target) for (i = 0; i < num_regs; i++) { (*cache_p)->reg_list[i].name = xscale_reg_list[i]; (*cache_p)->reg_list[i].value = calloc(4, 1); - (*cache_p)->reg_list[i].dirty = 0; - (*cache_p)->reg_list[i].valid = 0; + (*cache_p)->reg_list[i].dirty = false; + (*cache_p)->reg_list[i].valid = false; (*cache_p)->reg_list[i].size = 32; (*cache_p)->reg_list[i].arch_info = &arch_info[i]; (*cache_p)->reg_list[i].type = &xscale_reg_type; |