1 files changed, 31 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013_reg.h b/src/target/riscv/riscv-013_reg.h
new file mode 100644
index 0000000..2bdaaa0
--- /dev/null
+++ b/src/target/riscv/riscv-013_reg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef OPENOCD_TARGET_RISCV_RISCV_REG_013_H
+#define OPENOCD_TARGET_RISCV_RISCV_REG_013_H
+
+#include "target/target.h"
+#include "gdb_regs.h"
+#include "riscv.h"
+
+/**
+ * This file describes additional register cache interface available to the
+ * RISC-V Debug Specification v0.13+ targets.
+ */
+
+/**
+ * Init initialize register cache. After this function all registers can be
+ * safely accessed via functions described here and in `riscv_reg.h`.
+ */
+int riscv013_reg_init_all(struct target *target);
+
+/**
+ * This function is used to save the value of a register in cache. The register
+ * is marked as dirty, and writeback is delayed for as long as possible.
+ * Generally used to save registers before program buffer execution.
+ *
+ * TODO: The interface should be restricted in such a way that only GPRs can be
+ * saved.
+ */
+int riscv013_reg_save(struct target *target, enum gdb_regno regid);
+
+#endif /*OPENOCD_TARGET_RISCV_RISCV_REG_013_H*/