diff options
Diffstat (limited to 'src/target/cortex_a.c')
| -rwxr-xr-x | src/target/cortex_a.c | 1041 |
1 files changed, 449 insertions, 592 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 862fd55..e1c4c9c 100755 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -36,6 +36,7 @@ * Cortex-A9(tm) TRM, ARM DDI 0407F * * * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -52,20 +53,20 @@ static int cortex_a8_poll(struct target *target); static int cortex_a8_debug_entry(struct target *target); static int cortex_a8_restore_context(struct target *target, bool bpwp); static int cortex_a8_set_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode); + struct breakpoint *breakpoint, uint8_t matchmode); static int cortex_a8_set_context_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode); + struct breakpoint *breakpoint, uint8_t matchmode); static int cortex_a8_set_hybrid_breakpoint(struct target *target, - struct breakpoint *breakpoint); + struct breakpoint *breakpoint); static int cortex_a8_unset_breakpoint(struct target *target, - struct breakpoint *breakpoint); + struct breakpoint *breakpoint); static int cortex_a8_dap_read_coreregister_u32(struct target *target, - uint32_t *value, int regnum); + uint32_t *value, int regnum); static int cortex_a8_dap_write_coreregister_u32(struct target *target, - uint32_t value, int regnum); + uint32_t value, int regnum); static int cortex_a8_mmu(struct target *target, int *enabled); static int cortex_a8_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys); + uint32_t virt, uint32_t *phys); /* * FIXME do topology discovery using the ROM; don't @@ -77,19 +78,18 @@ static int cortex_a8_virt2phys(struct target *target, #define swjdp_debugap 1 /* restore cp15_control_reg at resume */ -static int cortex_a8_restore_cp15_control_reg(struct target* target) +static int cortex_a8_restore_cp15_control_reg(struct target *target) { int retval = ERROR_OK; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); - if (cortex_a8->cp15_control_reg !=cortex_a8->cp15_control_reg_curr) - { + if (cortex_a8->cp15_control_reg != cortex_a8->cp15_control_reg_curr) { cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; - //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); + /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); */ retval = armv7a->arm.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg); } return retval; @@ -103,20 +103,20 @@ static int cortex_a8_check_address(struct target *target, uint32_t address) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); uint32_t os_border = armv7a->armv7a_mmu.os_border; if ((address < os_border) && - (armv7a->arm.core_mode == ARM_MODE_SVC)) { - LOG_ERROR("%x access in userspace and target in supervisor",address); + (armv7a->arm.core_mode == ARM_MODE_SVC)) { + LOG_ERROR("%x access in userspace and target in supervisor", address); return ERROR_FAIL; } if ((address >= os_border) && - (cortex_a8->curr_mode != ARM_MODE_SVC)) { + (cortex_a8->curr_mode != ARM_MODE_SVC)) { dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); cortex_a8->curr_mode = ARM_MODE_SVC; LOG_INFO("%x access in kernel space and target not in supervisor", - address); + address); return ERROR_OK; } if ((address < os_border) && - (cortex_a8->curr_mode == ARM_MODE_SVC)) { + (cortex_a8->curr_mode == ARM_MODE_SVC)) { dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); cortex_a8->curr_mode = ARM_MODE_ANY; } @@ -130,39 +130,32 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); int retval = ERROR_OK; - if (enable) - { + if (enable) { /* if mmu enabled at target stop and mmu not enable */ - if (!(cortex_a8->cp15_control_reg & 0x1U)) - { + if (!(cortex_a8->cp15_control_reg & 0x1U)) { LOG_ERROR("trying to enable mmu on target stopped with mmu disable"); return ERROR_FAIL; } - if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) - { + if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr |= 0x1U; retval = armv7a->arm.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); } - } - else - { - if (cortex_a8->cp15_control_reg_curr & 0x4U) - { - /* data cache is active */ + } else { + if (cortex_a8->cp15_control_reg_curr & 0x4U) { + /* data cache is active */ cortex_a8->cp15_control_reg_curr &= ~0x4U; /* flush data cache armv7 function to be called */ if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) - armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target); + armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target); } - if ( (cortex_a8->cp15_control_reg_curr & 0x1U)) - { + if ((cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr &= ~0x1U; retval = armv7a->arm.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); } } @@ -181,26 +174,24 @@ static int cortex_a8_init_debug_access(struct target *target) LOG_DEBUG(" "); - /* Unlocking the debug registers for modification */ - /* The debugport might be uninitialised so try twice */ + /* Unlocking the debug registers for modification + * The debugport might be uninitialised so try twice */ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { /* try again */ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); if (retval == ERROR_OK) - { - LOG_USER("Locking debug access failed on first, but succeeded on second try."); - } + LOG_USER( + "Locking debug access failed on first, but succeeded on second try."); } if (retval != ERROR_OK) return retval; /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_PRSR, &dummy); + armv7a->debug_base + CPUDBG_PRSR, &dummy); if (retval != ERROR_OK) return retval; @@ -218,7 +209,7 @@ static int cortex_a8_init_debug_access(struct target *target) * happen to know that no instruction is pending. */ static int cortex_a8_exec_opcode(struct target *target, - uint32_t opcode, uint32_t *dscr_p) + uint32_t opcode, uint32_t *dscr_p) { uint32_t dscr; int retval; @@ -231,44 +222,37 @@ static int cortex_a8_exec_opcode(struct target *target, /* Wait for InstrCompl bit to be set */ long long then = timeval_ms(); - while ((dscr & DSCR_INSTR_COMP) == 0) - { + while ((dscr & DSCR_INSTR_COMP) == 0) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); return retval; } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } } retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_ITR, opcode); + armv7a->debug_base + CPUDBG_ITR, opcode); if (retval != ERROR_OK) return retval; then = timeval_ms(); - do - { + do { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register"); return retval; } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } - } - while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ + } while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ if (dscr_p) *dscr_p = dscr; @@ -281,7 +265,7 @@ Read core register with very few exec_opcode, fast but needs work_area. This can cause problems with MMU active. **************************************************************************/ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address, - uint32_t * regfile) + uint32_t *regfile) { int retval = ERROR_OK; struct armv7a_common *armv7a = target_to_armv7a(target); @@ -304,7 +288,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre } static int cortex_a8_dap_read_coreregister_u32(struct target *target, - uint32_t *value, int regnum) + uint32_t *value, int regnum) { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; @@ -315,17 +299,14 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, if (reg > 17) return retval; - if (reg < 15) - { + if (reg < 15) { /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0), &dscr); if (retval != ERROR_OK) return retval; - } - else if (reg == 15) - { + } else if (reg == 15) { /* "MOV r0, r15"; then move r0 to DCCTX */ retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr); if (retval != ERROR_OK) @@ -335,9 +316,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, &dscr); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* "MRS r0, CPSR" or "MRS r0, SPSR" * then move r0 to DCCTX */ @@ -353,14 +332,12 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, /* Wait for DTRRXfull then read DTRRTX */ long long then = timeval_ms(); - while ((dscr & DSCR_DTR_TX_FULL) == 0) - { + while ((dscr & DSCR_DTR_TX_FULL) == 0) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } @@ -374,7 +351,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, } static int cortex_a8_dap_write_coreregister_u32(struct target *target, - uint32_t value, int regnum) + uint32_t value, int regnum) { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; @@ -386,11 +363,10 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* Check that DCCRX is not full */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - if (dscr & DSCR_DTR_RX_FULL) - { + if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), @@ -409,17 +385,14 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, if (retval != ERROR_OK) return retval; - if (Rd < 15) - { + if (Rd < 15) { /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); - + if (retval != ERROR_OK) return retval; - } - else if (Rd == 15) - { + } else if (Rd == 15) { /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "mov r15, r0" */ @@ -430,9 +403,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) */ @@ -446,8 +417,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, return retval; /* "Prefetch flush" after modifying execution status in CPSR */ - if (Rd == 16) - { + if (Rd == 16) { retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4), &dscr); @@ -460,7 +430,9 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, } /* Write to memory mapped registers directly with no cache or mmu handling */ -static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value) +static int cortex_a8_dap_write_memap_register_u32(struct target *target, + uint32_t address, + uint32_t value) { int retval; struct armv7a_common *armv7a = target_to_armv7a(target); @@ -491,11 +463,11 @@ static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap, - swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); + swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, - uint32_t *dscr_p) + uint32_t *dscr_p) { struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr = DSCR_INSTR_COMP; @@ -512,8 +484,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, &dscr); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for read dcc"); return ERROR_FAIL; } @@ -523,7 +494,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); if (retval != ERROR_OK) return retval; - //LOG_DEBUG("read DCC 0x%08" PRIx32, *data); + /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */ if (dscr_p) *dscr_p = dscr; @@ -540,8 +511,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) /* set up invariant: INSTR_COMP is set after ever DPM operation */ long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); @@ -549,8 +519,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) return retval; if ((dscr & DSCR_INSTR_COMP) != 0) break; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for dpm prepare"); return ERROR_FAIL; } @@ -578,7 +547,7 @@ static int cortex_a8_dpm_finish(struct arm_dpm *dpm) } static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; @@ -595,7 +564,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, } static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t dscr = DSCR_INSTR_COMP; @@ -634,7 +603,7 @@ static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm) } static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; @@ -653,7 +622,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t dscr = DSCR_INSTR_COMP; @@ -679,7 +648,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, } static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, - uint32_t addr, uint32_t control) + uint32_t addr, uint32_t control) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t vr = a8->armv7a_common.debug_base; @@ -687,23 +656,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, int retval; switch (index_t) { - case 0 ... 15: /* breakpoints */ - vr += CPUDBG_BVR_BASE; - cr += CPUDBG_BCR_BASE; - break; - case 16 ... 31: /* watchpoints */ - vr += CPUDBG_WVR_BASE; - cr += CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: /* breakpoints */ + vr += CPUDBG_BVR_BASE; + cr += CPUDBG_BCR_BASE; + break; + case 16 ... 31: /* watchpoints */ + vr += CPUDBG_WVR_BASE; + cr += CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } vr += 4 * index_t; cr += 4 * index_t; LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x", - (unsigned) vr, (unsigned) cr); + (unsigned) vr, (unsigned) cr); retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target, vr, addr); @@ -720,15 +689,15 @@ static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) uint32_t cr; switch (index_t) { - case 0 ... 15: - cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; - break; - case 16 ... 31: - cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; + break; + case 16 ... 31: + cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } cr += 4 * index_t; @@ -767,20 +736,17 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) } static struct target *get_cortex_a8(struct target *target, int32_t coreid) { -struct target_list *head; -struct target *curr; + struct target_list *head; + struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED)) - { - return curr; - } + return curr; head = head->next; } - return target; + return target; } static int cortex_a8_halt(struct target *target); @@ -790,13 +756,10 @@ static int cortex_a8_halt_smp(struct target *target) struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - if ((curr != target) && (curr->state!= TARGET_HALTED)) - { + if ((curr != target) && (curr->state != TARGET_HALTED)) retval += cortex_a8_halt(curr); - } head = head->next; } return retval; @@ -805,8 +768,7 @@ static int cortex_a8_halt_smp(struct target *target) static int update_halt_gdb(struct target *target) { int retval = 0; - if (target->gdb_service->core[0]==-1) - { + if (target->gdb_service->core[0] == -1) { target->gdb_service->target = target; target->gdb_service->core[0] = target->coreid; retval += cortex_a8_halt_smp(target); @@ -826,75 +788,61 @@ static int cortex_a8_poll(struct target *target) struct armv7a_common *armv7a = &cortex_a8->armv7a_common; struct adiv5_dap *swjdp = armv7a->arm.dap; enum target_state prev_target_state = target->state; - // toggle to another core is done by gdb as follow - // maint packet J core_id - // continue - // the next polling trigger an halt event sent to gdb + /* toggle to another core is done by gdb as follow */ + /* maint packet J core_id */ + /* continue */ + /* the next polling trigger an halt event sent to gdb */ if ((target->state == TARGET_HALTED) && (target->smp) && - (target->gdb_service) && - (target->gdb_service->target==NULL) ) - { + (target->gdb_service) && + (target->gdb_service->target == NULL)) { target->gdb_service->target = get_cortex_a8(target, target->gdb_service->core[1]); - target_call_event_callbacks(target, - TARGET_EVENT_HALTED); + target_call_event_callbacks(target, TARGET_EVENT_HALTED); return retval; } retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) - { return retval; - } cortex_a8->cpudbg_dscr = dscr; - if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) - { - if (prev_target_state != TARGET_HALTED) - { + if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) { + if (prev_target_state != TARGET_HALTED) { /* We have a halting debug event */ LOG_DEBUG("Target halted"); target->state = TARGET_HALTED; if ((prev_target_state == TARGET_RUNNING) - || (prev_target_state == TARGET_RESET)) - { + || (prev_target_state == TARGET_RESET)) { retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; - if (target->smp) - { + if (target->smp) { retval = update_halt_gdb(target); if (retval != ERROR_OK) return retval; } target_call_event_callbacks(target, - TARGET_EVENT_HALTED); + TARGET_EVENT_HALTED); } - if (prev_target_state == TARGET_DEBUG_RUNNING) - { + if (prev_target_state == TARGET_DEBUG_RUNNING) { LOG_DEBUG(" "); retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; - if (target->smp) - { + if (target->smp) { retval = update_halt_gdb(target); if (retval != ERROR_OK) return retval; } target_call_event_callbacks(target, - TARGET_EVENT_DEBUG_HALTED); + TARGET_EVENT_DEBUG_HALTED); } } - } - else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED) - { + } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED) target->state = TARGET_RUNNING; - } - else - { + else { LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr); target->state = TARGET_UNKNOWN; } @@ -922,28 +870,24 @@ static int cortex_a8_halt(struct target *target) * enter halting debug mode */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); + armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); if (retval != ERROR_OK) return retval; long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; if ((dscr & DSCR_CORE_HALTED) != 0) - { break; - } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for halt"); return ERROR_FAIL; } @@ -955,7 +899,7 @@ static int cortex_a8_halt(struct target *target) } static int cortex_a8_internal_restore(struct target *target, int current, - uint32_t *address, int handle_breakpoints, int debug_execution) + uint32_t *address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *arm = &armv7a->arm; @@ -966,8 +910,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, target_free_all_working_areas(target); #if 0 - if (debug_execution) - { + if (debug_execution) { /* Disable interrupts */ /* We disable interrupts in the PRIMASK register instead of * masking with C_MASKINTS, @@ -980,7 +923,8 @@ static int cortex_a8_internal_restore(struct target *target, int current, /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, + 32) | (1 << 24)); armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } @@ -996,29 +940,28 @@ static int cortex_a8_internal_restore(struct target *target, int current, /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - switch (arm->core_state) - { - case ARM_STATE_ARM: - resume_pc &= 0xFFFFFFFC; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - resume_pc |= 0x1; - break; - case ARM_STATE_JAZELLE: - LOG_ERROR("How do I resume into Jazelle state??"); - return ERROR_FAIL; + switch (arm->core_state) { + case ARM_STATE_ARM: + resume_pc &= 0xFFFFFFFC; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + resume_pc |= 0x1; + break; + case ARM_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); buf_set_u32(arm->pc->value, 0, 32, resume_pc); arm->pc->dirty = 1; arm->pc->valid = 1; /* restore dpm_mode at system halt */ - dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); - /* called it now before restoring context because it uses cpu + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + /* called it now before restoring context because it uses cpu * register r0 for restoring cp15 control register */ retval = cortex_a8_restore_cp15_control_reg(target); if (retval != ERROR_OK) @@ -1026,7 +969,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, retval = cortex_a8_restore_context(target, handle_breakpoints); if (retval != ERROR_OK) return retval; - target->debug_reason = DBG_REASON_NOTHALTED; + target->debug_reason = DBG_REASON_NOTHALTED; target->state = TARGET_RUNNING; /* registers are now invalid */ @@ -1034,11 +977,10 @@ static int cortex_a8_internal_restore(struct target *target, int current, #if 0 /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); @@ -1057,9 +999,9 @@ static int cortex_a8_internal_restart(struct target *target) struct adiv5_dap *swjdp = arm->dap; int retval; uint32_t dscr; -/* - * Restart core and wait for it to be started. Clear ITRen and sticky - * exception flags: see ARMv7 ARM, C5.9. + /* + * * Restart core and wait for it to be started. Clear ITRen and sticky + * * exception flags: see ARMv7 ARM, C5.9. * * REVISIT: for single stepping, we probably want to * disable IRQs by default, with optional override... @@ -1074,7 +1016,7 @@ static int cortex_a8_internal_restart(struct target *target) LOG_ERROR("DSCR InstrCompl must be set before leaving debug!"); retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); + armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); if (retval != ERROR_OK) return retval; @@ -1085,16 +1027,14 @@ static int cortex_a8_internal_restart(struct target *target) return retval; long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; if ((dscr & DSCR_CORE_RESTARTED) != 0) break; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for resume"); return ERROR_FAIL; } @@ -1109,22 +1049,20 @@ static int cortex_a8_internal_restart(struct target *target) return ERROR_OK; } -static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints) +static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints) { int retval = 0; struct target_list *head; struct target *curr; - uint32_t address; + uint32_t address; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - if ((curr != target) && (curr->state != TARGET_RUNNING)) - { - /* resume current address , not in step mode */ - retval += cortex_a8_internal_restore(curr, 1, &address, - handle_breakpoints, 0); - retval += cortex_a8_internal_restart(curr); + if ((curr != target) && (curr->state != TARGET_RUNNING)) { + /* resume current address , not in step mode */ + retval += cortex_a8_internal_restore(curr, 1, &address, + handle_breakpoints, 0); + retval += cortex_a8_internal_restart(curr); } head = head->next; @@ -1133,12 +1071,11 @@ static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints) } static int cortex_a8_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) + uint32_t address, int handle_breakpoints, int debug_execution) { int retval = 0; - /* dummy resume for smp toggle in order to reduce gdb impact */ - if ((target->smp) && (target->gdb_service->core[1]!=-1)) - { + /* dummy resume for smp toggle in order to reduce gdb impact */ + if ((target->smp) && (target->gdb_service->core[1] != -1)) { /* simulate a start and halt of target */ target->gdb_service->target = NULL; target->gdb_service->core[0] = target->gdb_service->core[1]; @@ -1147,22 +1084,19 @@ static int cortex_a8_resume(struct target *target, int current, return 0; } cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution); - if (target->smp) - { target->gdb_service->core[0] = -1; + if (target->smp) { + target->gdb_service->core[0] = -1; retval = cortex_a8_restore_smp(target, handle_breakpoints); if (retval != ERROR_OK) return retval; } cortex_a8_internal_restart(target); - if (!debug_execution) - { + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); LOG_DEBUG("target resumed at 0x%" PRIx32, address); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%" PRIx32, address); @@ -1187,7 +1121,7 @@ static int cortex_a8_debug_entry(struct target *target) /* REVISIT surely we should not re-read DSCR !! */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -1226,19 +1160,14 @@ static int cortex_a8_debug_entry(struct target *target) /* First load register acessible through core debug port*/ if (!regfile_working_area) - { retval = arm_dpm_read_current_registers(&armv7a->dpm); - } - else - { + else { retval = cortex_a8_read_regs_through_mem(target, regfile_working_area->address, regfile); target_free_working_area(target, regfile_working_area); if (retval != ERROR_OK) - { return retval; - } /* read Current PSR */ retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); @@ -1251,8 +1180,7 @@ static int cortex_a8_debug_entry(struct target *target) arm_set_cpsr(arm, cpsr); /* update cache */ - for (i = 0; i <= ARM_PC; i++) - { + for (i = 0; i <= ARM_PC; i++) { reg = arm_reg_current(arm, i); buf_set_u32(reg->value, 0, 32, regfile[i]); @@ -1261,14 +1189,11 @@ static int cortex_a8_debug_entry(struct target *target) } /* Fixup PC Resume Address */ - if (cpsr & (1 << 5)) - { - // T bit set for Thumb or ThumbEE state + if (cpsr & (1 << 5)) { + /* T bit set for Thumb or ThumbEE state */ regfile[ARM_PC] -= 4; - } - else - { - // ARM state + } else { + /* ARM state */ regfile[ARM_PC] -= 8; } @@ -1291,9 +1216,8 @@ static int cortex_a8_debug_entry(struct target *target) #endif /* Are we in an exception handler */ -// armv4_5->exception_number = 0; - if (armv7a->post_debug_entry) - { +/* armv4_5->exception_number = 0; */ + if (armv7a->post_debug_entry) { retval = armv7a->post_debug_entry(target); if (retval != ERROR_OK) return retval; @@ -1316,26 +1240,24 @@ static int cortex_a8_post_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); - cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; + cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) - { armv7a_identify_cache(target); - } armv7a->armv7a_mmu.mmu_enabled = - (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; + (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = - (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; + (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = - (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; + (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; cortex_a8->curr_mode = armv7a->arm.core_mode; return ERROR_OK; } static int cortex_a8_step(struct target *target, int current, uint32_t address, - int handle_breakpoints) + int handle_breakpoints) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *arm = &armv7a->arm; @@ -1344,8 +1266,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, struct reg *r; int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1353,13 +1274,9 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* current = 1: continue on current pc, otherwise continue at <address> */ r = arm->pc; if (!current) - { buf_set_u32(r->value, 0, 32, address); - } else - { address = buf_get_u32(r->value, 0, 32); - } /* The front-end may request us not to handle breakpoints. * But since Cortex-A8 uses breakpoint for single step, @@ -1375,7 +1292,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* Setup single step breakpoint */ stepbreakpoint.address = address; stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB) - ? 2 : 4; + ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -1389,13 +1306,11 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, return retval; long long then = timeval_ms(); - while (target->state != TARGET_HALTED) - { + while (target->state != TARGET_HALTED) { retval = cortex_a8_poll(target); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("timeout waiting for target halt"); return ERROR_FAIL; } @@ -1426,46 +1341,40 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp) return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp); } - /* * Cortex-A8 Breakpoint and watchpoint functions */ /* Setup hardware Breakpoint Register Pair */ static int cortex_a8_set_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode) + struct breakpoint *breakpoint, uint8_t matchmode) { int retval; - int brp_i=0; + int brp_i = 0; uint32_t control; uint8_t byte_addr_select = 0x0F; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num)) - brp_i++ ; - if (brp_i >= cortex_a8->brp_num) - { + brp_i++; + if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } breakpoint->set = brp_i + 1; if (breakpoint->length == 2) - { byte_addr_select = (3 << (breakpoint->address & 0x02)); - } control = ((matchmode & 0x7) << 20) - | (byte_addr_select << 5) - | (3 << 1) | 1; + | (byte_addr_select << 5) + | (3 << 1) | 1; brp_list[brp_i].used = 1; brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_i].control = control; @@ -1480,20 +1389,14 @@ static int cortex_a8_set_breakpoint(struct target *target, if (retval != ERROR_OK) return retval; LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, - brp_list[brp_i].value); - } - else if (breakpoint->type == BKPT_SOFT) - { + brp_list[brp_i].control, + brp_list[brp_i].value); + } else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; if (breakpoint->length == 2) - { buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); - } else - { buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11)); - } retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, @@ -1505,67 +1408,66 @@ static int cortex_a8_set_breakpoint(struct target *target, breakpoint->length, 1, code); if (retval != ERROR_OK) return retval; - breakpoint->set = 0x11; /* Any nice value but 0 */ + breakpoint->set = 0x11; /* Any nice value but 0 */ } return ERROR_OK; } static int cortex_a8_set_context_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode) + struct breakpoint *breakpoint, uint8_t matchmode) { int retval = ERROR_FAIL; - int brp_i=0; + int brp_i = 0; uint32_t control; uint8_t byte_addr_select = 0x0F; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; - - if (breakpoint->set) - { + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; + + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); - return retval ; + return retval; } /*check available context BRPs*/ - while ((brp_list[brp_i].used || (brp_list[brp_i].type!=BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num)) - brp_i++ ; - - if (brp_i >= cortex_a8->brp_num) - { + while ((brp_list[brp_i].used || + (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num)) + brp_i++; + + if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; } breakpoint->set = brp_i + 1; control = ((matchmode & 0x7) << 20) - | (byte_addr_select << 5) - | (3 << 1) | 1; + | (byte_addr_select << 5) + | (3 << 1) | 1; brp_list[brp_i].used = 1; brp_list[brp_i].value = (breakpoint->asid); brp_list[brp_i].control = control; retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].value); - if(retval != ERROR_OK) + if (retval != ERROR_OK) return retval; retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].control); - if(retval != ERROR_OK) + if (retval != ERROR_OK) return retval; LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, - brp_list[brp_i].value); + brp_list[brp_i].control, + brp_list[brp_i].value); return ERROR_OK; - + } static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_FAIL; - int brp_1=0; //holds the contextID pair - int brp_2=0; // holds the IVA pair + int brp_1 = 0; /* holds the contextID pair */ + int brp_2 = 0; /* holds the IVA pair */ uint32_t control_CTX, control_IVA; uint8_t CTX_byte_addr_select = 0x0F; uint8_t IVA_byte_addr_select = 0x0F; @@ -1573,105 +1475,97 @@ static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpo uint8_t IVA_machmode = 0x01; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; - - - - if (breakpoint->set) - { + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; + + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); - return retval ; + return retval; } /*check available context BRPs*/ - while ((brp_list[brp_1].used || (brp_list[brp_1].type!=BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num)) - brp_1++ ; - - printf("brp(CTX) found num: %d \n",brp_1); - if (brp_1 >= cortex_a8->brp_num) - { + while ((brp_list[brp_1].used || + (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num)) + brp_1++; + + printf("brp(CTX) found num: %d\n", brp_1); + if (brp_1 >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; } - while ((brp_list[brp_2].used || (brp_list[brp_2].type!=BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num)) - brp_2++ ; - - printf("brp(IVA) found num: %d \n",brp_2); - if (brp_2 >= cortex_a8->brp_num) - { + while ((brp_list[brp_2].used || + (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num)) + brp_2++; + + printf("brp(IVA) found num: %d\n", brp_2); + if (brp_2 >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; } breakpoint->set = brp_1 + 1; - breakpoint->linked_BRP= brp_2; + breakpoint->linked_BRP = brp_2; control_CTX = ((CTX_machmode & 0x7) << 20) - | (brp_2 << 16) - | (0 << 14) - | (CTX_byte_addr_select << 5) - | (3 << 1) | 1; - brp_list[brp_1].used = 1; - brp_list[brp_1].value = (breakpoint->asid); - brp_list[brp_1].control = control_CTX; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn, - brp_list[brp_1].value); - if (retval != ERROR_OK) - return retval; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn, - brp_list[brp_1].control); - if( retval != ERROR_OK ) - return retval; + | (brp_2 << 16) + | (0 << 14) + | (CTX_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_1].used = 1; + brp_list[brp_1].value = (breakpoint->asid); + brp_list[brp_1].control = control_CTX; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].control); + if (retval != ERROR_OK) + return retval; - control_IVA = ((IVA_machmode & 0x7) << 20) - | (brp_1 << 16) - | (IVA_byte_addr_select << 5) - | (3 << 1) | 1; - brp_list[brp_2].used = 1; - brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); - brp_list[brp_2].control = control_IVA; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn, - brp_list[brp_2].value); - if (retval != ERROR_OK) - return retval; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn, - brp_list[brp_2].control); - if (retval != ERROR_OK ) - return retval; + control_IVA = ((IVA_machmode & 0x7) << 20) + | (brp_1 << 16) + | (IVA_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_2].used = 1; + brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); + brp_list[brp_2].control = control_IVA; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].control); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } - static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { - if ((breakpoint->address != 0) && (breakpoint->asid != 0)) - { + if (breakpoint->type == BKPT_HARD) { + if ((breakpoint->address != 0) && (breakpoint->asid != 0)) { int brp_i = breakpoint->set - 1; int brp_j = breakpoint->linked_BRP; - if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) - { + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) { LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].control, brp_list[brp_i].value); brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; @@ -1684,14 +1578,13 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].value); if (retval != ERROR_OK) - return retval; - if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) - { + return retval; + if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) { LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j, - brp_list[brp_j].control, brp_list[brp_j].value); + brp_list[brp_j].control, brp_list[brp_j].value); brp_list[brp_j].used = 0; brp_list[brp_j].value = 0; brp_list[brp_j].control = 0; @@ -1708,18 +1601,15 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * breakpoint->linked_BRP = 0; breakpoint->set = 0; return ERROR_OK; - - } - else - { + + } else { int brp_i = breakpoint->set - 1; - if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) - { + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) { LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].control, brp_list[brp_i].value); brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; @@ -1735,21 +1625,16 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * return retval; breakpoint->set = 0; return ERROR_OK; - } - } - else - { + } + } else { /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) - { + if (breakpoint->length == 4) { retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; - } - else - { + } else { retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr); @@ -1763,12 +1648,11 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * } static int cortex_a8_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1776,16 +1660,15 @@ static int cortex_a8_add_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) cortex_a8->brp_num_available--; - return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ + return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ } static int cortex_a8_add_context_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1793,16 +1676,15 @@ static int cortex_a8_add_context_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) cortex_a8->brp_num_available--; - return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */ + return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */ } static int cortex_a8_add_hybrid_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1810,7 +1692,7 @@ static int cortex_a8_add_hybrid_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) cortex_a8->brp_num_available--; - return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */ + return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */ } @@ -1820,26 +1702,22 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint #if 0 /* It is perfectly possible to remove breakpoints while the target is running */ - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } #endif - if (breakpoint->set) - { + if (breakpoint->set) { cortex_a8_unset_breakpoint(target, breakpoint); if (breakpoint->type == BKPT_HARD) - cortex_a8->brp_num_available++ ; + cortex_a8->brp_num_available++; } return ERROR_OK; } - - /* * Cortex-A8 Reset functions */ @@ -1853,9 +1731,9 @@ static int cortex_a8_assert_reset(struct target *target) /* FIXME when halt is requested, make it work somehow... */ /* Issue some kind of warm reset. */ - if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - } else if (jtag_get_reset_config() & RESET_HAS_SRST) { + else if (jtag_get_reset_config() & RESET_HAS_SRST) { /* REVISIT handle "pulls" cases, if there's * hardware that needs them to work. */ @@ -1889,8 +1767,9 @@ static int cortex_a8_deassert_reset(struct target *target) if (target->reset_halt) { if (target->state != TARGET_HALTED) { LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - if ((retval = target_halt(target)) != ERROR_OK) + target_name(target)); + retval = target_halt(target); + if (retval != ERROR_OK) return retval; } } @@ -1898,12 +1777,10 @@ static int cortex_a8_deassert_reset(struct target *target) return ERROR_OK; } - static int cortex_a8_write_apb_ab_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { - /* write memory through APB-AP */ int retval = ERROR_COMMAND_SYNTAX_ERROR; @@ -1917,8 +1794,7 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, uint32_t ui; } data; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1938,10 +1814,10 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, nbytes_to_write = 4 - start_byte; if (total_bytes < nbytes_to_write) - nbytes_to_write = total_bytes; - - if ( nbytes_to_write != 4 ) { - + nbytes_to_write = total_bytes; + + if (nbytes_to_write != 4) { + /* execute instruction LDR r1, [r0] */ retval = cortex_a8_exec_opcode(target, ARMV4_5_LDR(1, 0), NULL); if (retval != ERROR_OK) @@ -1951,7 +1827,7 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, if (retval != ERROR_OK) return retval; } - + for (i = 0; i < nbytes_to_write; ++i) data.uc_a[i + start_byte] = *buffer++; @@ -1960,9 +1836,9 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, return retval; /* execute instruction STRW r1, [r0], 1 (0xe4801004) */ - retval = cortex_a8_exec_opcode(target, ARMV4_5_STRW_IP(1, 0) , NULL); + retval = cortex_a8_exec_opcode(target, ARMV4_5_STRW_IP(1, 0), NULL); if (retval != ERROR_OK) - return retval; + return retval; total_bytes -= nbytes_to_write; start_byte = 0; @@ -1973,8 +1849,8 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, static int cortex_a8_read_apb_ab_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { /* read memory through APB-AP */ @@ -1990,8 +1866,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, uint32_t ui; } data; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2020,11 +1895,11 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, nbytes_to_read = 4 - start_byte; if (total_bytes < nbytes_to_read) - nbytes_to_read = total_bytes; - + nbytes_to_read = total_bytes; + for (i = 0; i < nbytes_to_read; ++i) *buffer++ = data.uc_a[i + start_byte]; - + total_bytes -= nbytes_to_read; start_byte = 0; } @@ -2042,50 +1917,51 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, */ static int cortex_a8_read_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", - address, size, count); + address, size, count); if (count && buffer) { - if ( apsel == swjdp_memoryap ) { + if (apsel == swjdp_memoryap) { /* read memory through AHB-AP */ switch (size) { - case 4: - retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, + case 4: + retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, + break; + case 2: + retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, + break; + case 1: + retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, buffer, count, address); - break; + break; } } else { - /* read memory through APB-AP */ - /* disable mmu */ + /* read memory through APB-AP + * disable mmu */ retval = cortex_a8_mmu_modify(target, 0); - if (retval != ERROR_OK) return retval; - retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } } return retval; } static int cortex_a8_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { int enabled = 0; uint32_t virt, phys; @@ -2096,39 +1972,40 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, /* cortex_a8 handles unaligned memory access */ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, - size, count); + size, count); if (apsel == swjdp_memoryap) { retval = cortex_a8_mmu(target, &enabled); if (retval != ERROR_OK) return retval; - if(enabled) - { + if (enabled) { virt = address; retval = cortex_a8_virt2phys(target, virt, &phys); if (retval != ERROR_OK) return retval; LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", - virt, phys); + virt, phys); address = phys; } retval = cortex_a8_read_phys_memory(target, address, size, count, buffer); } else { retval = cortex_a8_check_address(target, address); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; /* enable mmu */ retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } return retval; } static int cortex_a8_write_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; @@ -2136,26 +2013,26 @@ static int cortex_a8_write_phys_memory(struct target *target, uint8_t apsel = swjdp->apsel; LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, - size, count); + size, count); if (count && buffer) { - if ( apsel == swjdp_memoryap ) { + if (apsel == swjdp_memoryap) { /* write memory through AHB-AP */ switch (size) { case 4: retval = mem_ap_sel_write_buf_u32(swjdp, swjdp_memoryap, - buffer, 4 * count, address); + buffer, 4 * count, address); break; case 2: retval = mem_ap_sel_write_buf_u16(swjdp, swjdp_memoryap, - buffer, 2 * count, address); + buffer, 2 * count, address); break; case 1: retval = mem_ap_sel_write_buf_u8(swjdp, swjdp_memoryap, - buffer, count, address); + buffer, count, address); break; } @@ -2165,14 +2042,13 @@ static int cortex_a8_write_phys_memory(struct target *target, retval = cortex_a8_mmu_modify(target, 0); if (retval != ERROR_OK) return retval; - return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); + return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } } /* REVISIT this op is generic ARMv7-A/R stuff */ - if (retval == ERROR_OK && target->state == TARGET_HALTED) - { + if (retval == ERROR_OK && target->state == TARGET_HALTED) { struct arm_dpm *dpm = armv7a->arm.dpm; retval = dpm->prepare(dpm); @@ -2189,15 +2065,14 @@ static int cortex_a8_write_phys_memory(struct target *target, */ /* invalidate I-Cache */ - if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) - { + if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) { /* ICIMVAU - Invalidate Cache single entry * with MVA to PoU * MCR p15, 0, r0, c7, c5, 1 */ for (uint32_t cacheline = address; - cacheline < address + size * count; - cacheline += 64) { + cacheline < address + size * count; + cacheline += 64) { retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 5, 1), cacheline); @@ -2207,15 +2082,14 @@ static int cortex_a8_write_phys_memory(struct target *target, } /* invalidate D-Cache */ - if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) - { + if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { /* DCIMVAC - Invalidate data Cache line * with MVA to PoC * MCR p15, 0, r0, c7, c6, 1 */ for (uint32_t cacheline = address; - cacheline < address + size * count; - cacheline += 64) { + cacheline < address + size * count; + cacheline += 64) { retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 6, 1), cacheline); @@ -2231,7 +2105,7 @@ static int cortex_a8_write_phys_memory(struct target *target, } static int cortex_a8_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { int enabled = 0; uint32_t virt, phys; @@ -2241,45 +2115,47 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, - size, count); + size, count); if (apsel == swjdp_memoryap) { - LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); + LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, + count); retval = cortex_a8_mmu(target, &enabled); if (retval != ERROR_OK) return retval; - if(enabled) - { + if (enabled) { virt = address; retval = cortex_a8_virt2phys(target, virt, &phys); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys); + LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", + virt, + phys); address = phys; } - retval = cortex_a8_write_phys_memory(target, address, size, + retval = cortex_a8_write_phys_memory(target, address, size, count, buffer); - } - else { + } else { retval = cortex_a8_check_address(target, address); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; /* enable mmu */ retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } - return retval; + return retval; } static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { return cortex_a8_write_memory(target, address, 4, count, buffer); } - static int cortex_a8_handle_target_request(void *priv) { struct target *target = priv; @@ -2292,23 +2168,20 @@ static int cortex_a8_handle_target_request(void *priv) if (!target->dbg_msg_enabled) return ERROR_OK; - if (target->state == TARGET_RUNNING) - { + if (target->state == TARGET_RUNNING) { uint32_t request; uint32_t dscr; retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); /* check if we have data */ - while ((dscr & DSCR_DTR_TX_FULL) && (retval==ERROR_OK)) - { + while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base+ CPUDBG_DTRTX, &request); - if (retval == ERROR_OK) - { + armv7a->debug_base + CPUDBG_DTRTX, &request); + if (retval == ERROR_OK) { target_request(target, request); retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base+ CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); } } } @@ -2336,8 +2209,7 @@ static int cortex_a8_examine_first(struct target *target) if (retval != ERROR_OK) return retval; - if (!target->dbgbase_set) - { + if (!target->dbgbase_set) { uint32_t dbgbase; /* Get ROM Table base */ uint32_t apid; @@ -2349,41 +2221,38 @@ static int cortex_a8_examine_first(struct target *target) &armv7a->debug_base); if (retval != ERROR_OK) return retval; - } - else - { + } else armv7a->debug_base = target->dbgbase; - } retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_CPUID, &cpuid); if (retval != ERROR_OK) return retval; - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_CPUID, &cpuid); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CPUID"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_CTYPR, &ctypr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CTYPR"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_TTYPR, &ttypr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "TTYPR"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_DIDR, &didr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "DIDR"); return retval; } @@ -2403,9 +2272,8 @@ static int cortex_a8_examine_first(struct target *target) cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1; cortex_a8->brp_num_available = cortex_a8->brp_num; cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp)); -// cortex_a8->brb_enabled = ????; - for (i = 0; i < cortex_a8->brp_num; i++) - { +/* cortex_a8->brb_enabled = ????; */ + for (i = 0; i < cortex_a8->brp_num; i++) { cortex_a8->brp_list[i].used = 0; if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context)) cortex_a8->brp_list[i].type = BRP_NORMAL; @@ -2442,14 +2310,14 @@ static int cortex_a8_examine(struct target *target) */ static int cortex_a8_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { /* examine_first() does a bunch of this */ return ERROR_OK; } static int cortex_a8_init_arch_info(struct target *target, - struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) + struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { struct armv7a_common *armv7a = &cortex_a8->armv7a_common; struct adiv5_dap *dap = &armv7a->dap; @@ -2459,25 +2327,23 @@ static int cortex_a8_init_arch_info(struct target *target, /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; /* tap has no dap initialized */ - if (!tap->dap) - { - armv7a->arm.dap = dap; - /* Setup struct cortex_a8_common */ + if (!tap->dap) { + armv7a->arm.dap = dap; + /* Setup struct cortex_a8_common */ - /* prepare JTAG information for the new target */ - cortex_a8->jtag_info.tap = tap; - cortex_a8->jtag_info.scann_size = 4; + /* prepare JTAG information for the new target */ + cortex_a8->jtag_info.tap = tap; + cortex_a8->jtag_info.scann_size = 4; - /* Leave (only) generic DAP stuff for debugport_init() */ - dap->jtag_info = &cortex_a8->jtag_info; + /* Leave (only) generic DAP stuff for debugport_init() */ + dap->jtag_info = &cortex_a8->jtag_info; - /* Number of bits for tar autoincrement, impl. dep. at least 10 */ - dap->tar_autoincr_block = (1 << 10); - dap->memaccess_tck = 80; - tap->dap = dap; - } - else - armv7a->arm.dap = tap->dap; + /* Number of bits for tar autoincrement, impl. dep. at least 10 */ + dap->tar_autoincr_block = (1 << 10); + dap->memaccess_tck = 80; + tap->dap = dap; + } else + armv7a->arm.dap = tap->dap; cortex_a8->fast_reg_read = 0; @@ -2490,8 +2356,8 @@ static int cortex_a8_init_arch_info(struct target *target, armv7a->armv7a_mmu.read_physical_memory = cortex_a8_read_phys_memory; - -// arm7_9->handle_target_request = cortex_a8_handle_target_request; + +/* arm7_9->handle_target_request = cortex_a8_handle_target_request; */ /* REVISIT v7a setup should be in a v7a-specific routine */ armv7a_init_arch_info(target, armv7a); @@ -2521,26 +2387,24 @@ static int cortex_a8_mmu(struct target *target, int *enabled) } static int cortex_a8_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys) + uint32_t virt, uint32_t *phys) { int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; - if (apsel == swjdp_memoryap) - { + if (apsel == swjdp_memoryap) { uint32_t ret; retval = armv7a_mmu_translate_va(target, - virt, &ret); + virt, &ret); if (retval != ERROR_OK) goto done; *phys = ret; - } - else - { /* use this method if swjdp_memoryap not selected */ - /* mmu must be enable in order to get a correct translation */ + } else {/* use this method if swjdp_memoryap not selected + * mmu must be enable in order to get a correct translation */ retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; retval = armv7a_mmu_translate_va_pa(target, virt, phys, 1); } done: @@ -2560,8 +2424,7 @@ COMMAND_HANDLER(cortex_a8_handle_cache_info_command) COMMAND_HANDLER(cortex_a8_handle_dbginit_command) { struct target *target = get_current_target(CMD_CTX); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("target not examined yet"); return ERROR_FAIL; } @@ -2571,15 +2434,13 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command) COMMAND_HANDLER(cortex_a8_handle_smp_off_command) { struct target *target = get_current_target(CMD_CTX); - /* check target is an smp target */ - struct target_list *head; + /* check target is an smp target */ + struct target_list *head; struct target *curr; head = target->head; target->smp = 0; - if (head != (struct target_list*)NULL) - { - while (head != (struct target_list*)NULL) - { + if (head != (struct target_list *)NULL) { + while (head != (struct target_list *)NULL) { curr = head->target; curr->smp = 0; head = head->next; @@ -2596,10 +2457,9 @@ COMMAND_HANDLER(cortex_a8_handle_smp_on_command) struct target_list *head; struct target *curr; head = target->head; - if (head != (struct target_list*)NULL) - { target->smp=1; - while (head != (struct target_list*)NULL) - { + if (head != (struct target_list *)NULL) { + target->smp = 1; + while (head != (struct target_list *)NULL) { curr = head->target; curr->smp = 1; head = head->next; @@ -2614,19 +2474,17 @@ COMMAND_HANDLER(cortex_a8_handle_smp_gdb_command) int retval = ERROR_OK; struct target_list *head; head = target->head; - if (head != (struct target_list*)NULL) - { - if (CMD_ARGC == 1) - { + if (head != (struct target_list *)NULL) { + if (CMD_ARGC == 1) { int coreid = 0; COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); if (ERROR_OK != retval) return retval; - target->gdb_service->core[1]=coreid; + target->gdb_service->core[1] = coreid; } command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0] - , target->gdb_service->core[1]); + , target->gdb_service->core[1]); } return ERROR_OK; } @@ -2646,22 +2504,21 @@ static const struct command_registration cortex_a8_exec_command_handlers[] = { .help = "Initialize core debug", .usage = "", }, - { .name ="smp_off", + { .name = "smp_off", .handler = cortex_a8_handle_smp_off_command, - .mode = COMMAND_EXEC, - .help = "Stop smp handling", - .usage = "", - }, + .mode = COMMAND_EXEC, + .help = "Stop smp handling", + .usage = "",}, { - .name ="smp_on", - .handler = cortex_a8_handle_smp_on_command, + .name = "smp_on", + .handler = cortex_a8_handle_smp_on_command, .mode = COMMAND_EXEC, .help = "Restart smp handling", .usage = "", }, { - .name ="smp_gdb", - .handler = cortex_a8_handle_smp_gdb_command, + .name = "smp_gdb", + .handler = cortex_a8_handle_smp_gdb_command, .mode = COMMAND_EXEC, .help = "display/fix current core played to gdb", .usage = "", |