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-rw-r--r--src/target/aarch64.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3510db2..41bea2e 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -698,6 +698,8 @@ static int aarch64_post_debug_entry(struct target *target)
switch (armv8->arm.core_mode) {
case ARMV8_64_EL0T:
+ dpmv8_modeswitch(&armv8->dpm, ARMV8_64_EL1T);
+ /* fall through */
case ARMV8_64_EL1T:
case ARMV8_64_EL1H:
retval = armv8->arm.mrs(target, 3, /*op 0*/
@@ -725,13 +727,20 @@ static int aarch64_post_debug_entry(struct target *target)
if (retval != ERROR_OK)
return retval;
break;
- default:
+
+ case ARM_MODE_SVC:
retval = armv8->arm.mrc(target, 15, 0, 0, 1, 0, &aarch64->system_control_reg);
if (retval != ERROR_OK)
return retval;
break;
+
+ default:
+ LOG_INFO("cannot read system control register in this mode");
+ break;
}
+ dpmv8_modeswitch(&armv8->dpm, ARM_MODE_ANY);
+
LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
aarch64->system_control_reg_curr = aarch64->system_control_reg;