diff options
| -rw-r--r-- | doc/openocd.texi | 9 | ||||
| -rw-r--r-- | src/target/xtensa/xtensa.c | 18 |
2 files changed, 17 insertions, 10 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 53730ea..e4d4dc5 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -11600,13 +11600,14 @@ This feature is not well implemented and tested yet. @end deffn @deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes> -Execute arbitrary instruction(s) provided as an ascii string. The string represents an integer -number of instruction bytes, thus its length must be even. +Execute one arbitrary instruction provided as an ascii string. The string represents an integer +number of instruction bytes, thus its length must be even. The instruction can be of any width +that is valid for the Xtensa core configuration. @end deffn @deffn {Command} {xtensa dm} (address) [value] -Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads -and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified +Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads +and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified only for write accesses. @end deffn diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index d2ca32c..ab3bfbb 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -3483,15 +3483,21 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target) LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]); xtensa_queue_exec_ins_wide(xtensa, ops, oplen); /* Handles endian-swap */ status = xtensa_dm_queue_execute(&xtensa->dbg_mod); - if (status != ERROR_OK) - LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status); - status = xtensa_core_status_check(target); - if (status != ERROR_OK) - LOG_TARGET_ERROR(target, "TIE instr execute: %d\n", status); + if (status != ERROR_OK) { + LOG_TARGET_ERROR(target, "exec: queue error %d", status); + } else { + status = xtensa_core_status_check(target); + if (status != ERROR_OK) + LOG_TARGET_ERROR(target, "exec: status error %d", status); + } /* Reread register cache and restore saved regs after instruction execution */ if (xtensa_fetch_all_regs(target) != ERROR_OK) - LOG_TARGET_ERROR(target, "%s: Failed to fetch register cache (post-exec).", target_name(target)); + LOG_TARGET_ERROR(target, "post-exec: register fetch error"); + if (status != ERROR_OK) { + LOG_TARGET_ERROR(target, "post-exec: EXCCAUSE 0x%02" PRIx32, + xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE)); + } xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause); xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable); return status; |