diff options
| -rw-r--r-- | doc/openocd.texi | 4 | ||||
| -rw-r--r-- | src/jtag/jtag.h | 1 | ||||
| -rw-r--r-- | src/jtag/tcl.c | 8 | ||||
| -rw-r--r-- | src/target/arm7_9_common.c | 13 |
4 files changed, 25 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 0b6ecf0..9f7314b 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -2018,6 +2018,10 @@ haven't seen hardware with such a bug, and can be worked around). @option{combined} implies both @option{srst_pulls_trst} and @option{trst_pulls_srst}. +@option{srst_gates_jtag} indicates that asserting SRST gates the +JTAG clock. This means that no communication can happen on JTAG +while SRST is asserted. + The optional @var{trst_type} and @var{srst_type} parameters allow the driver mode of each reset line to be specified. These values only affect JTAG interfaces with support for different driver modes, like the Amontec diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h index b7bfd4c..f716806 100644 --- a/src/jtag/jtag.h +++ b/src/jtag/jtag.h @@ -277,6 +277,7 @@ enum reset_types { RESET_TRST_PULLS_SRST = 0x8, RESET_TRST_OPEN_DRAIN = 0x10, RESET_SRST_PUSH_PULL = 0x20, + RESET_SRST_GATES_JTAG = 0x40, }; enum reset_types jtag_get_reset_config(void); diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index e6928a2..1658f76 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -845,6 +845,14 @@ static int handle_reset_config_command(struct command_context_s *cmd_ctx, char * int tmp = 0; int m; + m = RESET_SRST_GATES_JTAG; + tmp = 0; + if (strcmp(*args, "srst_gates_jtag") == 0) + { + tmp = RESET_SRST_GATES_JTAG; + goto next; + } + /* signals */ m = RESET_HAS_TRST | RESET_HAS_SRST; if (strcmp(*args, "none") == 0) diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 9f05d77..e2eb0d5 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1021,6 +1021,17 @@ int arm7_9_assert_reset(target_t *target) return ERROR_FAIL; } + /* at this point trst has been asserted/deasserted once. We want to + * program embedded ice while SRST is asserted, but some CPUs gate + * the JTAG clock while SRST is asserted + */ + bool srst_asserted = false; + if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0)) + { + jtag_add_reset(0, 1); + srst_asserted = true; + } + if (target->reset_halt) { /* @@ -1053,7 +1064,7 @@ int arm7_9_assert_reset(target_t *target) if (jtag_reset_config & RESET_SRST_PULLS_TRST) { jtag_add_reset(1, 1); - } else + } else if (!srst_asserted) { jtag_add_reset(0, 1); } |