diff options
107 files changed, 9596 insertions, 11936 deletions
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index 75461c3..b6473b0 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -40,7 +40,6 @@ #include "arm_adi_v5.h" #include <helper/time_support.h> - /* JTAG instructions/registers for JTAG-DP and SWJ-DP */ #define JTAG_DP_ABORT 0x8 #define JTAG_DP_DPACC 0xA @@ -223,22 +222,19 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; dap->ack = dap->ack & 0x7; /* common code path avoids calling timeval_ms() */ - if (dap->ack != JTAG_ACK_OK_FAULT) - { + if (dap->ack != JTAG_ACK_OK_FAULT) { long long then = timeval_ms(); - while (dap->ack != JTAG_ACK_OK_FAULT) - { - if (dap->ack == JTAG_ACK_WAIT) - { - if ((timeval_ms()-then) > 1000) - { + while (dap->ack != JTAG_ACK_OK_FAULT) { + if (dap->ack == JTAG_ACK_WAIT) { + if ((timeval_ms()-then) > 1000) { /* NOTE: this would be a good spot * to use JTAG_DP_ABORT. */ @@ -247,9 +243,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) "in JTAG-DP transaction"); return ERROR_JTAG_DEVICE_ERROR; } - } - else - { + } else { LOG_WARNING("Invalid ACK %#x " "in JTAG-DP transaction", dap->ack); @@ -260,7 +254,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; dap->ack = dap->ack & 0x7; } @@ -269,18 +264,14 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */ /* Check for STICKYERR and STICKYORUN */ - if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) - { + if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) { LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat); /* Check power to debug regions */ - if ((ctrlstat & 0xf0000000) != 0xf0000000) - { + if ((ctrlstat & 0xf0000000) != 0xf0000000) { retval = ahbap_debugport_init(dap); if (retval != ERROR_OK) return retval; - } - else - { + } else { uint32_t mem_ap_csw, mem_ap_tar; /* Maybe print information about last intended @@ -314,7 +305,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat); @@ -329,13 +321,15 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32, mem_ap_csw, mem_ap_tar); } - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; return ERROR_JTAG_DEVICE_ERROR; } diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index 5a3570d..6af7748 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -55,12 +55,10 @@ #include <jtag/swd.h> - - static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, uint32_t *data) { - // REVISIT status return vs ack ... + /* REVISIT status return vs ack ... */ return swd->read_reg(swd_cmd(true, false, reg), data); } @@ -71,14 +69,14 @@ static int swd_queue_idcode_read(struct adiv5_dap *dap, if (status < 0) return status; *ack = status; - // ?? + /* ?? */ return ERROR_OK; } static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data) { - // REVISIT status return vs ack ... + /* REVISIT status return vs ack ... */ return swd->write_reg(swd_cmd(false, false, reg), data); } @@ -86,16 +84,16 @@ static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg, static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data) { - // REVISIT APSEL ... - // REVISIT status return ... + /* REVISIT APSEL ... */ + /* REVISIT status return ... */ return swd->read_reg(swd_cmd(true, true, reg), data); } static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data) { - // REVISIT APSEL ... - // REVISIT status return ... + /* REVISIT APSEL ... */ + /* REVISIT status return ... */ return swd->write_reg(swd_cmd(false, true, reg), data); } @@ -194,15 +192,14 @@ COMMAND_HANDLER(handle_swd_wcr) int retval; struct target *target = get_current_target(CMD_CTX); struct arm *arm = target_to_arm(target); -struct adiv5_dap *dap = arm->dap; + struct adiv5_dap *dap = arm->dap; uint32_t wcr; unsigned trn, scale = 0; - switch (CMD_ARGC) { /* no-args: just dump state */ case 0: - //retval = swd_queue_dp_read(dap, DP_WCR, &wcr); + /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */ retval = dap_queue_dp_read(dap, DP_WCR, &wcr); if (retval == ERROR_OK) dap->ops->run(dap); @@ -315,11 +312,10 @@ static int swd_init(struct command_context *ctx) { struct target *target = get_current_target(ctx); struct arm *arm = target_to_arm(target); -struct adiv5_dap *dap = arm->dap; + struct adiv5_dap *dap = arm->dap; uint32_t idcode; int status; - /* FIXME validate transport config ... is the * configured DAP present (check IDCODE)? * Is *only* one DAP configured? diff --git a/src/target/algorithm.c b/src/target/algorithm.c index 57383ae..0714144 100644 --- a/src/target/algorithm.c +++ b/src/target/algorithm.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -24,7 +25,6 @@ #include "algorithm.h" #include <helper/binarybuffer.h> - void init_mem_param(struct mem_param *param, uint32_t address, uint32_t size, enum param_direction direction) { param->address = address; diff --git a/src/target/algorithm.h b/src/target/algorithm.h index af1fd91..ecd1177 100644 --- a/src/target/algorithm.h +++ b/src/target/algorithm.h @@ -17,26 +17,24 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ALGORITHM_H #define ALGORITHM_H -enum param_direction -{ +enum param_direction { PARAM_IN, PARAM_OUT, PARAM_IN_OUT }; -struct mem_param -{ +struct mem_param { uint32_t address; uint32_t size; uint8_t *value; enum param_direction direction; }; -struct reg_param -{ +struct reg_param { const char *reg_name; uint32_t size; uint8_t *value; diff --git a/src/target/arm.h b/src/target/arm.h index 86cf447..ab7d85c 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + #ifndef ARM_H #define ARM_H diff --git a/src/target/arm11.c b/src/target/arm11.c index da084b1..bb7b9c6 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -38,7 +38,6 @@ #include "register.h" #include "arm_opcodes.h" - #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif @@ -56,8 +55,7 @@ static int arm11_check_init(struct arm11_common *arm11) { CHECK_RETVAL(arm11_read_DSCR(arm11)); - if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) - { + if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) { LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); LOG_DEBUG("Bringing target into debug mode"); @@ -68,8 +66,7 @@ static int arm11_check_init(struct arm11_common *arm11) arm11->simulate_reset_on_next_halt = true; - if (arm11->dscr & DSCR_CORE_HALTED) - { + if (arm11->dscr & DSCR_CORE_HALTED) { /** \todo TODO: this needs further scrutiny because * arm11_debug_entry() never gets called. (WHY NOT?) * As a result we don't read the actual register states from @@ -78,9 +75,7 @@ static int arm11_check_init(struct arm11_common *arm11) arm11->arm.target->state = TARGET_HALTED; arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); - } - else - { + } else { arm11->arm.target->state = TARGET_RUNNING; arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED; } @@ -110,20 +105,20 @@ static int arm11_debug_entry(struct arm11_common *arm11) /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */ arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL); - if (arm11->is_wdtr_saved) - { + if (arm11->is_wdtr_saved) { arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - struct scan_field chain5_fields[3]; + struct scan_field chain5_fields[3]; arm11_setup_field(arm11, 32, NULL, - &arm11->saved_wdtr, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); + &arm11->saved_wdtr, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain5_fields), chain5_fields, TAP_DRPAUSE); } @@ -143,10 +138,9 @@ static int arm11_debug_entry(struct arm11_common *arm11) /** \todo TODO: Test drain write buffer. */ #if 0 - while (1) - { + while (1) { /* MRC p14,0,R0,c5,c10,0 */ - // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000); + /* arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */ /* mcr 15, 0, r0, cr7, cr10, {4} */ arm11_run_instr_no_data1(arm11, 0xee070f9a); @@ -155,8 +149,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) LOG_DEBUG("DRAIN, DSCR %08x", dscr); - if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) - { + if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) { arm11_run_instr_no_data1(arm11, 0xe320f000); dscr = arm11_read_DSCR(arm11); @@ -183,8 +176,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */ arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL); - if (arm11->is_rdtr_saved) - { + if (arm11->is_rdtr_saved) { /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &arm11->saved_rdtr); @@ -196,8 +188,7 @@ static int arm11_debug_entry(struct arm11_common *arm11) * be MMU and cache state to care about ... */ - if (arm11->simulate_reset_on_next_halt) - { + if (arm11->simulate_reset_on_next_halt) { arm11->simulate_reset_on_next_halt = false; LOG_DEBUG("Reset c1 Control Register"); @@ -255,8 +246,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) { CHECK_RETVAL(arm11_read_DSCR(arm11)); - if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) - { + if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) { /* The wDTR/rDTR two registers that are used to send/receive data to/from the core in tandem with corresponding instruction codes that are @@ -265,14 +255,13 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) read out by the other side. */ LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", - (unsigned) arm11->dscr); + (unsigned) arm11->dscr); return ERROR_FAIL; } } /* maybe restore original wDTR */ - if (arm11->is_wdtr_saved) - { + if (arm11->is_wdtr_saved) { retval = arm11_run_instr_data_prepare(arm11); if (retval != ERROR_OK) return retval; @@ -301,23 +290,23 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr)); /* maybe restore rDTR */ - if (arm11->is_rdtr_saved) - { + if (arm11->is_rdtr_saved) { arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - struct scan_field chain5_fields[3]; + struct scan_field chain5_fields[3]; - uint8_t Ready = 0; /* ignored */ - uint8_t Valid = 0; /* ignored */ + uint8_t Ready = 0; /* ignored */ + uint8_t Valid = 0; /* ignored */ arm11_setup_field(arm11, 32, &arm11->saved_rdtr, - NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); - arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); + NULL, chain5_fields + 0); + arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); + arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain5_fields), chain5_fields, TAP_DRPAUSE); } /* now processor is ready to RESTART */ @@ -333,10 +322,8 @@ static int arm11_poll(struct target *target) CHECK_RETVAL(arm11_check_init(arm11)); - if (arm11->dscr & DSCR_CORE_HALTED) - { - if (target->state != TARGET_HALTED) - { + if (arm11->dscr & DSCR_CORE_HALTED) { + if (target->state != TARGET_HALTED) { enum target_state old_state = target->state; LOG_DEBUG("enter TARGET_HALTED"); @@ -346,17 +333,14 @@ static int arm11_poll(struct target *target) target_call_event_callbacks(target, (old_state == TARGET_DEBUG_RUNNING) - ? TARGET_EVENT_DEBUG_HALTED - : TARGET_EVENT_HALTED); + ? TARGET_EVENT_DEBUG_HALTED + : TARGET_EVENT_HALTED); } - } - else - { - if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) - { + } else { + if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) { LOG_DEBUG("enter TARGET_RUNNING"); - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; + target->state = TARGET_RUNNING; + target->debug_reason = DBG_REASON_NOTHALTED; } } @@ -374,14 +358,14 @@ static int arm11_arch_state(struct target *target) if (target->debug_reason == DBG_REASON_WATCHPOINT) LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) arm11->dpm.wp_pc); + (unsigned) arm11->dpm.wp_pc); return retval; } /* target request support */ static int arm11_target_request_data(struct target *target, - uint32_t size, uint8_t *buffer) + uint32_t size, uint8_t *buffer) { LOG_WARNING("Not implemented: %s", __func__); @@ -397,12 +381,9 @@ static int arm11_halt(struct target *target) target_state_name(target)); if (target->state == TARGET_UNKNOWN) - { arm11->simulate_reset_on_next_halt = true; - } - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } @@ -413,8 +394,7 @@ static int arm11_halt(struct target *target) int i = 0; - while (1) - { + while (1) { CHECK_RETVAL(arm11_read_DSCR(arm11)); if (arm11->dscr & DSCR_CORE_HALTED) @@ -423,13 +403,9 @@ static int arm11_halt(struct target *target) long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } @@ -437,19 +413,19 @@ static int arm11_halt(struct target *target) i++; } - enum target_state old_state = target->state; + enum target_state old_state = target->state; CHECK_RETVAL(arm11_debug_entry(arm11)); CHECK_RETVAL( target_call_event_callbacks(target, - old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)); + old_state == + TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)); return ERROR_OK; } -static uint32_t -arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) +static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) { void *value = arm11->arm.pc->value; @@ -462,10 +438,10 @@ arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) } static int arm11_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) + uint32_t address, int handle_breakpoints, int debug_execution) { - // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", - // current, address, handle_breakpoints, debug_execution); + /* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */ + /* current, address, handle_breakpoints, debug_execution); */ struct arm11_common *arm11 = target_to_arm11(target); @@ -473,8 +449,7 @@ static int arm11_resume(struct target *target, int current, target_state_name(target)); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -493,10 +468,8 @@ static int arm11_resume(struct target *target, int current, if (handle_breakpoints) { struct breakpoint *bp; - for (bp = target->breakpoints; bp; bp = bp->next) - { - if (bp->address == address) - { + for (bp = target->breakpoints; bp; bp = bp->next) { + if (bp->address == address) { LOG_DEBUG("must step over %08" PRIx32 "", bp->address); arm11_step(target, 1, 0, 0); break; @@ -509,21 +482,22 @@ static int arm11_resume(struct target *target, int current, struct breakpoint *bp; unsigned brp_num = 0; - for (bp = target->breakpoints; bp; bp = bp->next) - { - struct arm11_sc7_action brp[2]; + for (bp = target->breakpoints; bp; bp = bp->next) { + struct arm11_sc7_action brp[2]; - brp[0].write = 1; - brp[0].address = ARM11_SC7_BVR0 + brp_num; - brp[0].value = bp->address; - brp[1].write = 1; - brp[1].address = ARM11_SC7_BCR0 + brp_num; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); + brp[0].write = 1; + brp[0].address = ARM11_SC7_BVR0 + brp_num; + brp[0].value = bp->address; + brp[1].write = 1; + brp[1].address = ARM11_SC7_BCR0 + brp_num; + brp[1].value = 0x1 | + (3 << + 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num, - bp->address); + bp->address); brp_num++; } @@ -540,8 +514,7 @@ static int arm11_resume(struct target *target, int current, CHECK_RETVAL(jtag_execute_queue()); int i = 0; - while (1) - { + while (1) { CHECK_RETVAL(arm11_read_DSCR(arm11)); LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); @@ -552,13 +525,9 @@ static int arm11_resume(struct target *target, int current, long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } @@ -577,13 +546,12 @@ static int arm11_resume(struct target *target, int current, } static int arm11_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + uint32_t address, int handle_breakpoints) { LOG_DEBUG("target->state: %s", target_state_name(target)); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -597,30 +565,25 @@ static int arm11_step(struct target *target, int current, /** \todo TODO: Thumb not supported here */ - uint32_t next_instruction; + uint32_t next_instruction; CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction)); /* skip over BKPT */ - if ((next_instruction & 0xFFF00070) == 0xe1200070) - { + if ((next_instruction & 0xFFF00070) == 0xe1200070) { address = arm11_nextpc(arm11, 0, address + 4); LOG_DEBUG("Skipping BKPT %08" PRIx32, address); } - /* skip over Wait for interrupt / Standby */ - /* mcr 15, 0, r?, cr7, cr0, {4} */ - else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) - { + /* skip over Wait for interrupt / Standby + * mcr 15, 0, r?, cr7, cr0, {4} */ + else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) { address = arm11_nextpc(arm11, 0, address + 4); LOG_DEBUG("Skipping WFI %08" PRIx32, address); } /* ignore B to self */ else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe) - { LOG_DEBUG("Not stepping jump to self"); - } - else - { + else { /** \todo TODO: check if break-/watchpoints make any sense at all in combination * with this. */ @@ -630,15 +593,14 @@ static int arm11_step(struct target *target, int current, /* Set up breakpoint for stepping */ - struct arm11_sc7_action brp[2]; + struct arm11_sc7_action brp[2]; - brp[0].write = 1; - brp[0].address = ARM11_SC7_BVR0; - brp[1].write = 1; - brp[1].address = ARM11_SC7_BCR0; + brp[0].write = 1; + brp[0].address = ARM11_SC7_BVR0; + brp[1].write = 1; + brp[1].address = ARM11_SC7_BCR0; - if (arm11->hardware_step) - { + if (arm11->hardware_step) { /* Hardware single stepping ("instruction address * mismatch") is used if enabled. It's not quite * exactly "run one instruction"; "branch to here" @@ -651,12 +613,11 @@ static int arm11_step(struct target *target, int current, * FIXME Thumb stepping likely needs to use 0x03 * or 0xc0 byte masks, not 0x0f. */ - brp[0].value = address; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) - | (0 << 14) | (0 << 16) | (0 << 20) - | (2 << 21); - } else - { + brp[0].value = address; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (2 << 21); + } else { /* Sets a breakpoint on the next PC, as calculated * by instruction set simulation. * @@ -670,10 +631,10 @@ static int arm11_step(struct target *target, int current, if (retval != ERROR_OK) return retval; - brp[0].value = next_pc; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) - | (0 << 14) | (0 << 16) | (0 << 20) - | (0 << 21); + brp[0].value = next_pc; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (0 << 21); } CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); @@ -697,10 +658,9 @@ static int arm11_step(struct target *target, int current, /* wait for halt */ int i = 0; - while (1) - { + while (1) { const uint32_t mask = DSCR_CORE_RESTARTED - | DSCR_CORE_HALTED; + | DSCR_CORE_HALTED; CHECK_RETVAL(arm11_read_DSCR(arm11)); LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr); @@ -710,14 +670,11 @@ static int arm11_step(struct target *target, int current, long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { + LOG_WARNING( + "Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } } @@ -751,9 +708,9 @@ static int arm11_assert_reset(struct target *target) CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1)); /* Issue some kind of warm reset. */ - if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - } else if (jtag_get_reset_config() & RESET_HAS_SRST) { + else if (jtag_get_reset_config() & RESET_HAS_SRST) { /* REVISIT handle "pulls" cases, if there's * hardware that needs them to work. */ @@ -800,8 +757,9 @@ static int arm11_deassert_reset(struct target *target) if (target->reset_halt) { if (target->state != TARGET_HALTED) { LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - if ((retval = target_halt(target)) != ERROR_OK) + target_name(target)); + retval = target_halt(target); + if (retval != ERROR_OK) return retval; } } @@ -829,19 +787,22 @@ static int arm11_soft_reset_halt(struct target *target) * read memory address for some peripheral. */ static int arm11_read_memory_inner(struct target *target, - uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, - bool arm11_config_memrw_no_increment) + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, + bool arm11_config_memrw_no_increment) { - /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ + /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment + *problems */ int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } - LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); + LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", + address, + size, + count); struct arm11_common *arm11 = target_to_arm11(target); @@ -854,36 +815,33 @@ static int arm11_read_memory_inner(struct target *target, if (retval != ERROR_OK) return retval; - switch (size) - { - case 1: - arm11->arm.core_cache->reg_list[1].dirty = true; + switch (size) { + case 1: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) - { - /* ldrb r1, [r0], #1 */ - /* ldrb r1, [r0] */ - CHECK_RETVAL(arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); + for (size_t i = 0; i < count; i++) { + /* ldrb r1, [r0], #1 */ + /* ldrb r1, [r0] */ + CHECK_RETVAL(arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); - uint32_t res; - /* MCR p14,0,R1,c0,c5,0 */ - CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); + uint32_t res; + /* MCR p14,0,R1,c0,c5,0 */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); - *buffer++ = res; - } + *buffer++ = res; + } - break; + break; - case 2: + case 2: { arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) - { + for (size_t i = 0; i < count; i++) { /* ldrh r1, [r0], #2 */ CHECK_RETVAL(arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); + !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); uint32_t res; @@ -897,23 +855,27 @@ static int arm11_read_memory_inner(struct target *target, break; } - case 4: + case 4: { - uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; - /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ - uint32_t *words = (uint32_t *)(void *)buffer; - - /* LDC p14,c5,[R0],#4 */ - /* LDC p14,c5,[R0] */ - CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count)); - break; + uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; + /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ + uint32_t *words = (uint32_t *)(void *)buffer; + + /* LDC p14,c5,[R0],#4 */ + /* LDC p14,c5,[R0] */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count)); + break; } } return arm11_run_instr_data_finish(arm11); } -static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm11_read_memory(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + uint8_t *buffer) { return arm11_read_memory_inner(target, address, size, count, buffer, false); } @@ -924,19 +886,21 @@ static int arm11_read_memory(struct target *target, uint32_t address, uint32_t s * read memory address for some peripheral. */ static int arm11_write_memory_inner(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer, - bool no_increment) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer, + bool no_increment) { int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } - LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); + LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", + address, + size, + count); struct arm11_common *arm11 = target_to_arm11(target); @@ -944,8 +908,8 @@ static int arm11_write_memory_inner(struct target *target, if (retval != ERROR_OK) return retval; - /* load r0 with buffer address */ - /* MRC p14,0,r0,c0,c5,0 */ + /* load r0 with buffer address + * MRC p14,0,r0,c0,c5,0 */ retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); if (retval != ERROR_OK) return retval; @@ -959,14 +923,12 @@ static int arm11_write_memory_inner(struct target *target, */ bool burst = arm11->memwrite_burst && (count > 1); - switch (size) - { - case 1: + switch (size) { + case 1: { arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) - { + for (size_t i = 0; i < count; i++) { /* load r1 from DCC with byte data */ /* MRC p14,0,r1,c0,c5,0 */ retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); @@ -977,9 +939,7 @@ static int arm11_write_memory_inner(struct target *target, /* strb r1, [r0], #1 */ /* strb r1, [r0] */ retval = arm11_run_instr_no_data1(arm11, - !no_increment - ? 0xe4c01001 - : 0xe5c01000); + !no_increment ? 0xe4c01001 : 0xe5c01000); if (retval != ERROR_OK) return retval; } @@ -987,12 +947,11 @@ static int arm11_write_memory_inner(struct target *target, break; } - case 2: + case 2: { arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) - { + for (size_t i = 0; i < count; i++) { uint16_t value; memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); @@ -1006,9 +965,7 @@ static int arm11_write_memory_inner(struct target *target, /* strh r1, [r0], #2 */ /* strh r1, [r0] */ retval = arm11_run_instr_no_data1(arm11, - !no_increment - ? 0xe0c010b2 - : 0xe1c010b0); + !no_increment ? 0xe0c010b2 : 0xe1c010b0); if (retval != ERROR_OK) return retval; } @@ -1016,35 +973,34 @@ static int arm11_write_memory_inner(struct target *target, break; } - case 4: { - /* stream word data through DCC directly to memory */ - /* increment: STC p14,c5,[R0],#4 */ - /* no increment: STC p14,c5,[R0]*/ - uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00; + case 4: { + /* stream word data through DCC directly to memory */ + /* increment: STC p14,c5,[R0],#4 */ + /* no increment: STC p14,c5,[R0]*/ + uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00; - /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ - uint32_t *words = (uint32_t*)(void *)buffer; + /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ + uint32_t *words = (uint32_t *)(void *)buffer; - /* "burst" here just means trusting each instruction executes - * fully before we run the next one: per-word roundtrips, to - * check the Ready flag, are not used. - */ - if (!burst) - retval = arm11_run_instr_data_to_core(arm11, - instr, words, count); - else - retval = arm11_run_instr_data_to_core_noack(arm11, - instr, words, count); - if (retval != ERROR_OK) - return retval; + /* "burst" here just means trusting each instruction executes + * fully before we run the next one: per-word roundtrips, to + * check the Ready flag, are not used. + */ + if (!burst) + retval = arm11_run_instr_data_to_core(arm11, + instr, words, count); + else + retval = arm11_run_instr_data_to_core_noack(arm11, + instr, words, count); + if (retval != ERROR_OK) + return retval; - break; - } + break; + } } /* r0 verification */ - if (!no_increment) - { + if (!no_increment) { uint32_t r0; /* MCR p14,0,R0,c0,c5,0 */ @@ -1052,15 +1008,16 @@ static int arm11_write_memory_inner(struct target *target, if (retval != ERROR_OK) return retval; - if (address + size * count != r0) - { + if (address + size * count != r0) { LOG_ERROR("Data transfer failed. Expected end " - "address 0x%08x, got 0x%08x", - (unsigned) (address + size * count), - (unsigned) r0); + "address 0x%08x, got 0x%08x", + (unsigned) (address + size * count), + (unsigned) r0); if (burst) - LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); + LOG_ERROR( + "use 'arm11 memwrite burst disable' to disable fast burst mode"); + if (arm11->memwrite_error_fatal) return ERROR_FAIL; @@ -1071,22 +1028,21 @@ static int arm11_write_memory_inner(struct target *target, } static int arm11_write_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { /* pointer increment matters only for multi-unit writes ... * not e.g. to a "reset the chip" controller. */ return arm11_write_memory_inner(target, address, size, - count, buffer, count == 1); + count, buffer, count == 1); } /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ static int arm11_bulk_write_memory(struct target *target, - uint32_t address, uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t count, const uint8_t *buffer) { - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1098,26 +1054,23 @@ static int arm11_bulk_write_memory(struct target *target, * rw: 0 = write, 1 = read, 2 = access */ static int arm11_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct arm11_common *arm11 = target_to_arm11(target); #if 0 - if (breakpoint->type == BKPT_SOFT) - { + if (breakpoint->type == BKPT_SOFT) { LOG_INFO("sw breakpoint requested, but software breakpoints not enabled"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } #endif - if (!arm11->free_brps) - { + if (!arm11->free_brps) { LOG_DEBUG("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if (breakpoint->length != 4) - { + if (breakpoint->length != 4) { LOG_DEBUG("only breakpoints of four bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1128,7 +1081,7 @@ static int arm11_add_breakpoint(struct target *target, } static int arm11_remove_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct arm11_common *arm11 = target_to_arm11(target); @@ -1144,8 +1097,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp) if (target->tap == NULL) return ERROR_FAIL; - if (target->tap->ir_length != 5) - { + if (target->tap->ir_length != 5) { LOG_ERROR("'target arm11' expects IR LENGTH = 5"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1169,7 +1121,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp) } static int arm11_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { /* Initialize anything we can set up without talking to the target */ return ERROR_OK; @@ -1190,7 +1142,7 @@ static int arm11_examine(struct target *target) arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); - struct scan_field idcode_field; + struct scan_field idcode_field; arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field); @@ -1202,46 +1154,46 @@ static int arm11_examine(struct target *target) arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - struct scan_field chain0_fields[2]; + struct scan_field chain0_fields[2]; arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0); arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1); - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE); + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain0_fields), chain0_fields, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); /* assume the manufacturer id is ok; check the part # */ - switch ((device_id >> 12) & 0xFFFF) - { - case 0x7B36: - type = "ARM1136"; - break; - case 0x7B37: - type = "ARM11 MPCore"; - break; - case 0x7B56: - type = "ARM1156"; - break; - case 0x7B76: - arm11->arm.core_type = ARM_MODE_MON; - /* NOTE: could default arm11->hardware_step to true */ - type = "ARM1176"; - break; - default: - LOG_ERROR("unexpected ARM11 ID code"); - return ERROR_FAIL; + switch ((device_id >> 12) & 0xFFFF) { + case 0x7B36: + type = "ARM1136"; + break; + case 0x7B37: + type = "ARM11 MPCore"; + break; + case 0x7B56: + type = "ARM1156"; + break; + case 0x7B76: + arm11->arm.core_type = ARM_MODE_MON; + /* NOTE: could default arm11->hardware_step to true */ + type = "ARM1176"; + break; + default: + LOG_ERROR("unexpected ARM11 ID code"); + return ERROR_FAIL; } LOG_INFO("found %s", type); /* unlikely this could ever fail, but ... */ switch ((didr >> 16) & 0x0F) { - case ARM11_DEBUG_V6: - case ARM11_DEBUG_V61: /* supports security extensions */ - break; - default: - LOG_ERROR("Only ARM v6 and v6.1 debug supported."); - return ERROR_FAIL; + case ARM11_DEBUG_V6: + case ARM11_DEBUG_V61: /* supports security extensions */ + break; + default: + LOG_ERROR("Only ARM v6 and v6.1 debug supported."); + return ERROR_FAIL; } arm11->brp = ((didr >> 24) & 0x0F) + 1; @@ -1250,7 +1202,7 @@ static int arm11_examine(struct target *target) arm11->free_brps = arm11->brp; LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32, - device_id, implementor, didr); + device_id, implementor, didr); /* as a side-effect this reads DSCR and thus * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag @@ -1271,7 +1223,7 @@ static int arm11_examine(struct target *target) if (arm11->arm.etm && !target_was_examined(target)) { *register_get_last_cache_p(&target->reg_cache) = etm_build_reg_cache(target, &arm11->jtag_info, - arm11->arm.etm); + arm11->arm.etm); CHECK_RETVAL(etm_setup(target)); } @@ -1280,15 +1232,14 @@ static int arm11_examine(struct target *target) return ERROR_OK; } - #define ARM11_BOOL_WRAPPER(name, print_name) \ - COMMAND_HANDLER(arm11_handle_bool_##name) \ + COMMAND_HANDLER(arm11_handle_bool_ ## name) \ { \ struct target *target = get_current_target(CMD_CTX); \ struct arm11_common *arm11 = target_to_arm11(target); \ \ return CALL_COMMAND_HANDLER(handle_command_parse_bool, \ - &arm11->name, print_name); \ + &arm11->name, print_name); \ } ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode") @@ -1306,13 +1257,13 @@ COMMAND_HANDLER(arm11_handle_vcr) struct arm11_common *arm11 = target_to_arm11(target); switch (CMD_ARGC) { - case 0: - break; - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr); @@ -1395,38 +1346,38 @@ static const struct command_registration arm11_command_handlers[] = { /** Holds methods for ARM11xx targets. */ struct target_type arm11_target = { - .name = "arm11", + .name = "arm11", - .poll = arm11_poll, - .arch_state = arm11_arch_state, + .poll = arm11_poll, + .arch_state = arm11_arch_state, - .target_request_data = arm11_target_request_data, + .target_request_data = arm11_target_request_data, - .halt = arm11_halt, - .resume = arm11_resume, - .step = arm11_step, + .halt = arm11_halt, + .resume = arm11_resume, + .step = arm11_step, - .assert_reset = arm11_assert_reset, - .deassert_reset = arm11_deassert_reset, - .soft_reset_halt = arm11_soft_reset_halt, + .assert_reset = arm11_assert_reset, + .deassert_reset = arm11_deassert_reset, + .soft_reset_halt = arm11_soft_reset_halt, - .get_gdb_reg_list = arm_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, - .read_memory = arm11_read_memory, - .write_memory = arm11_write_memory, + .read_memory = arm11_read_memory, + .write_memory = arm11_write_memory, - .bulk_write_memory = arm11_bulk_write_memory, + .bulk_write_memory = arm11_bulk_write_memory, - .checksum_memory = arm_checksum_memory, - .blank_check_memory = arm_blank_check_memory, + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, - .add_breakpoint = arm11_add_breakpoint, - .remove_breakpoint = arm11_remove_breakpoint, + .add_breakpoint = arm11_add_breakpoint, + .remove_breakpoint = arm11_remove_breakpoint, - .run_algorithm = armv4_5_run_algorithm, + .run_algorithm = armv4_5_run_algorithm, - .commands = arm11_command_handlers, - .target_create = arm11_target_create, - .init_target = arm11_init_target, - .examine = arm11_examine, + .commands = arm11_command_handlers, + .target_create = arm11_target_create, + .init_target = arm11_init_target, + .examine = arm11_examine, }; diff --git a/src/target/arm11.h b/src/target/arm11.h index 9edadee..fd7af15 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -26,38 +26,36 @@ #include "arm.h" #include "arm_dpm.h" -#define ARM11_TAP_DEFAULT TAP_INVALID +#define ARM11_TAP_DEFAULT TAP_INVALID #define CHECK_RETVAL(action) \ do { \ int __retval = (action); \ if (__retval != ERROR_OK) { \ LOG_DEBUG("error while calling \"%s\"", \ - # action ); \ + # action); \ return __retval; \ } \ } while (0) /* bits from ARMv7 DIDR */ -enum arm11_debug_version -{ - ARM11_DEBUG_V6 = 0x01, - ARM11_DEBUG_V61 = 0x02, - ARM11_DEBUG_V7 = 0x03, - ARM11_DEBUG_V7_CP14 = 0x04, +enum arm11_debug_version { + ARM11_DEBUG_V6 = 0x01, + ARM11_DEBUG_V61 = 0x02, + ARM11_DEBUG_V7 = 0x03, + ARM11_DEBUG_V7_CP14 = 0x04, }; -struct arm11_common -{ - struct arm arm; +struct arm11_common { + struct arm arm; /** Debug module state. */ struct arm_dpm dpm; struct arm11_sc7_action *bpwp_actions; unsigned bpwp_n; - size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ - size_t free_brps; /**< Number of breakpoints allocated */ + size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ + size_t free_brps; /**< Number of breakpoints allocated */ uint32_t dscr; /**< Last retrieved DSCR value. */ @@ -67,7 +65,7 @@ struct arm11_common bool is_rdtr_saved; bool is_wdtr_saved; - bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ + bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt **/ /* Per-core configurable options. * NOTE that several of these boolean options should not exist @@ -86,8 +84,7 @@ struct arm11_common static inline struct arm11_common *target_to_arm11(struct target *target) { - return container_of(target->arch_info, struct arm11_common, - arm); + return container_of(target->arch_info, struct arm11_common, arm); } /** @@ -95,27 +92,25 @@ static inline struct arm11_common *target_to_arm11(struct target *target) * * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html */ -enum arm11_instructions -{ +enum arm11_instructions { ARM11_EXTEST = 0x00, ARM11_SCAN_N = 0x02, ARM11_RESTART = 0x04, - ARM11_HALT = 0x08, + ARM11_HALT = 0x08, ARM11_INTEST = 0x0C, ARM11_ITRSEL = 0x1D, ARM11_IDCODE = 0x1E, ARM11_BYPASS = 0x1F, }; -enum arm11_sc7 -{ - ARM11_SC7_NULL = 0, - ARM11_SC7_VCR = 7, - ARM11_SC7_PC = 8, - ARM11_SC7_BVR0 = 64, - ARM11_SC7_BCR0 = 80, - ARM11_SC7_WVR0 = 96, - ARM11_SC7_WCR0 = 112, +enum arm11_sc7 { + ARM11_SC7_NULL = 0, + ARM11_SC7_VCR = 7, + ARM11_SC7_PC = 8, + ARM11_SC7_BVR0 = 64, + ARM11_SC7_BCR0 = 80, + ARM11_SC7_WVR0 = 96, + ARM11_SC7_WCR0 = 112, }; -#endif /* ARM11_H */ +#endif /* ARM11_H */ diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index a5dc376..e190e29 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -30,9 +30,11 @@ #include <helper/time_support.h> #if 0 -#define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0) +#define JTAG_DEBUG(expr ...) do { if (1) \ + LOG_DEBUG(expr); } while (0) #else -#define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0) +#define JTAG_DEBUG(expr ...) do { if (0) \ + LOG_DEBUG(expr); } while (0) #endif /* @@ -42,33 +44,32 @@ behavior of the FTDI driver IIRC was to go via RTI. Conversely there may be other places in this code where the ARM11 code relies on the driver to hit through RTI when coming from Update-?R. */ -static const tap_state_t arm11_move_pi_to_si_via_ci[] = -{ - TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT +static const tap_state_t arm11_move_pi_to_si_via_ci[] = { + TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; - /* REVISIT no error handling here! */ static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields, - tap_state_t state) + tap_state_t state) { if (cmd_queue_cur_state == TAP_IRPAUSE) - jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), + arm11_move_pi_to_si_via_ci); jtag_add_ir_scan(tap, fields, state); } -static const tap_state_t arm11_move_pd_to_sd_via_cd[] = -{ +static const tap_state_t arm11_move_pd_to_sd_via_cd[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; /* REVISIT no error handling here! */ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields, - tap_state_t state) + tap_state_t state) { if (cmd_queue_cur_state == TAP_DRPAUSE) - jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), + arm11_move_pd_to_sd_via_cd); jtag_add_dr_scan(tap, num_fields, fields, state); } @@ -85,11 +86,11 @@ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_fiel * \param field target data structure that will be initialized */ void arm11_setup_field(struct arm11_common *arm11, int num_bits, - void *out_data, void *in_data, struct scan_field *field) + void *out_data, void *in_data, struct scan_field *field) { - field->num_bits = num_bits; - field->out_value = out_data; - field->in_value = in_data; + field->num_bits = num_bits; + field->out_value = out_data; + field->in_value = in_data; } static const char *arm11_ir_to_string(uint8_t ir) @@ -97,30 +98,30 @@ static const char *arm11_ir_to_string(uint8_t ir) const char *s = "unknown"; switch (ir) { - case ARM11_EXTEST: - s = "EXTEST"; - break; - case ARM11_SCAN_N: - s = "SCAN_N"; - break; - case ARM11_RESTART: - s = "RESTART"; - break; - case ARM11_HALT: - s = "HALT"; - break; - case ARM11_INTEST: - s = "INTEST"; - break; - case ARM11_ITRSEL: - s = "ITRSEL"; - break; - case ARM11_IDCODE: - s = "IDCODE"; - break; - case ARM11_BYPASS: - s = "BYPASS"; - break; + case ARM11_EXTEST: + s = "EXTEST"; + break; + case ARM11_SCAN_N: + s = "SCAN_N"; + break; + case ARM11_RESTART: + s = "RESTART"; + break; + case ARM11_HALT: + s = "HALT"; + break; + case ARM11_INTEST: + s = "INTEST"; + break; + case ARM11_ITRSEL: + s = "ITRSEL"; + break; + case ARM11_IDCODE: + s = "IDCODE"; + break; + case ARM11_BYPASS: + s = "BYPASS"; + break; } return s; } @@ -133,12 +134,11 @@ static const char *arm11_ir_to_string(uint8_t ir) * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) +void arm11_add_IR(struct arm11_common *arm11, uint8_t instr, tap_state_t state) { struct jtag_tap *tap = arm11->arm.target->tap; - if (buf_get_u32(tap->cur_instr, 0, 5) == instr) - { + if (buf_get_u32(tap->cur_instr, 0, 5) == instr) { JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr); return; } @@ -149,7 +149,9 @@ void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) arm11_setup_field(arm11, 5, &instr, NULL, &field); - arm11_add_ir_scan_vc(arm11->arm.target->tap, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state); + arm11_add_ir_scan_vc(arm11->arm.target->tap, + &field, + state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state); } /** Verify data shifted out from Scan Chain Register (SCREG). */ @@ -158,8 +160,7 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value) /* Don't expect JTAG layer to modify bits we didn't ask it to read */ uint8_t v = *in_value & 0x1F; - if (v != 0x10) - { + if (v != 0x10) { LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v); jtag_set_error(ERROR_FAIL); } @@ -193,33 +194,36 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value) */ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, - uint8_t chain, tap_state_t state) + uint8_t chain, tap_state_t state) { /* Don't needlessly switch the scan chain. * NOTE: the ITRSEL instruction fakes SCREG changing; * but leaves its actual value unchanged. */ #if 0 - // FIX!!! the optimization below is broken because we do not - // invalidate the cur_scan_chain upon a TRST/TMS. See arm_jtag.c - // for example on how to invalidate cur_scan_chain. Tested patches gladly - // accepted! + /* FIX!!! the optimization below is broken because we do not */ + /* invalidate the cur_scan_chain upon a TRST/TMS. See arm_jtag.c */ + /* for example on how to invalidate cur_scan_chain. Tested patches gladly */ + /* accepted! */ if (arm11->jtag_info.cur_scan_chain == chain) { JTAG_DEBUG("SCREG <= %d SKIPPED", chain); return jtag_add_statemove((state == ARM11_TAP_DEFAULT) - ? TAP_DRPAUSE : state); + ? TAP_DRPAUSE : state); } #endif JTAG_DEBUG("SCREG <= %d", chain); arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); - struct scan_field field; + struct scan_field field; uint8_t tmp[1]; arm11_setup_field(arm11, 5, &chain, &tmp, &field); - arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); + arm11_add_dr_scan_vc(arm11->arm.target->tap, + 1, + &field, + state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); jtag_execute_queue_noclear(); @@ -248,15 +252,15 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, * is properly set up. Depending on the instruction, you may also need * to ensure that the rDTR is ready before that Run-Test/Idle state. */ -static void arm11_add_debug_INST(struct arm11_common * arm11, - uint32_t inst, uint8_t * flag, tap_state_t state) +static void arm11_add_debug_INST(struct arm11_common *arm11, + uint32_t inst, uint8_t *flag, tap_state_t state) { JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst); - struct scan_field itr[2]; + struct scan_field itr[2]; - arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); - arm11_setup_field(arm11, 1, NULL, flag, itr + 1); + arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); + arm11_setup_field(arm11, 1, NULL, flag, itr + 1); arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(itr), itr, state); } @@ -281,8 +285,8 @@ int arm11_read_DSCR(struct arm11_common *arm11) arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - uint32_t dscr; - struct scan_field chain1_field; + uint32_t dscr; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); @@ -292,8 +296,8 @@ int arm11_read_DSCR(struct arm11_common *arm11) if (arm11->dscr != dscr) JTAG_DEBUG("DSCR = %08x (OLD %08x)", - (unsigned) dscr, - (unsigned) arm11->dscr); + (unsigned) dscr, + (unsigned) arm11->dscr); arm11->dscr = dscr; @@ -309,7 +313,7 @@ int arm11_read_DSCR(struct arm11_common *arm11) * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) +int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr) { int retval; retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); @@ -318,7 +322,7 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - struct scan_field chain1_field; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); @@ -327,8 +331,8 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DSCR <= %08x (OLD %08x)", - (unsigned) dscr, - (unsigned) arm11->dscr); + (unsigned) dscr, + (unsigned) arm11->dscr); arm11->dscr = dscr; @@ -349,7 +353,7 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) * \param arm11 Target state variable. * */ -int arm11_run_instr_data_prepare(struct arm11_common * arm11) +int arm11_run_instr_data_prepare(struct arm11_common *arm11) { return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); } @@ -368,13 +372,11 @@ int arm11_run_instr_data_prepare(struct arm11_common * arm11) * \param arm11 Target state variable. * */ -int arm11_run_instr_data_finish(struct arm11_common * arm11) +int arm11_run_instr_data_finish(struct arm11_common *arm11) { return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); } - - /** * Execute one or more instructions via ITR. * Caller guarantees that processor is in debug state, that DSCR_ITR_EN @@ -389,18 +391,16 @@ int arm11_run_instr_data_finish(struct arm11_common * arm11) * */ static -int arm11_run_instr_no_data(struct arm11_common * arm11, - uint32_t * opcode, size_t count) +int arm11_run_instr_no_data(struct arm11_common *arm11, + uint32_t *opcode, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - while (count--) - { + while (count--) { arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE); int i = 0; - while (1) - { + while (1) { uint8_t flag; arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); @@ -413,14 +413,11 @@ int arm11_run_instr_no_data(struct arm11_common * arm11, long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { + LOG_WARNING( + "Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } } @@ -440,7 +437,7 @@ int arm11_run_instr_no_data(struct arm11_common * arm11, * \param opcode ARM opcode * */ -int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) +int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode) { return arm11_run_instr_no_data(arm11, &opcode, 1); } @@ -463,7 +460,10 @@ int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) * \param count Number of data words and instruction repetitions * */ -int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_to_core(struct arm11_common *arm11, + uint32_t opcode, + uint32_t *data, + size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -471,24 +471,23 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - struct scan_field chain5_fields[3]; + struct scan_field chain5_fields[3]; - uint32_t Data; - uint8_t Ready; - uint8_t nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; - arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); + arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); - while (count--) - { + while (count--) { int i = 0; - do - { - Data = *data; + do { + Data = *data; - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE); + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain5_fields), chain5_fields, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); @@ -497,21 +496,17 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { + LOG_WARNING( + "Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } } i++; - } - while (!Ready); + } while (!Ready); data++; } @@ -519,35 +514,30 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); int i = 0; - do - { - Data = 0; + do { + Data = 0; - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain5_fields), chain5_fields, TAP_DRPAUSE); CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", - (unsigned) Data, Ready, nRetry); + (unsigned) Data, Ready, nRetry); long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } } i++; - } - while (!Ready); + } while (!Ready); return ERROR_OK; } @@ -569,74 +559,68 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = -{ - TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT +static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { + TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, + TAP_DRSHIFT }; /* This inner loop can be implemented by the minidriver, oftentimes in hardware... The * minidriver can call the default implementation as a fallback or implement it * from scratch. */ -int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *tap, + uint32_t opcode, + uint32_t *data, + size_t count) { - struct scan_field chain5_fields[3]; + struct scan_field chain5_fields[3]; - chain5_fields[0].num_bits = 32; - chain5_fields[0].out_value = NULL; /*&Data*/ - chain5_fields[0].in_value = NULL; + chain5_fields[0].num_bits = 32; + chain5_fields[0].out_value = NULL; /*&Data*/ + chain5_fields[0].in_value = NULL; - chain5_fields[1].num_bits = 1; - chain5_fields[1].out_value = NULL; - chain5_fields[1].in_value = NULL; /*&Ready*/ + chain5_fields[1].num_bits = 1; + chain5_fields[1].out_value = NULL; + chain5_fields[1].in_value = NULL; /*&Ready*/ - chain5_fields[2].num_bits = 1; - chain5_fields[2].out_value = NULL; - chain5_fields[2].in_value = NULL; + chain5_fields[2].num_bits = 1; + chain5_fields[2].out_value = NULL; + chain5_fields[2].in_value = NULL; - uint8_t *Readies; + uint8_t *Readies; unsigned readiesNum = count; unsigned bytes = sizeof(*Readies)*readiesNum; Readies = (uint8_t *) malloc(bytes); - if (Readies == NULL) - { + if (Readies == NULL) { LOG_ERROR("Out of memory allocating %u bytes", bytes); return ERROR_FAIL; } - uint8_t * ReadyPos = Readies; - while (count--) - { - chain5_fields[0].out_value = (void *)(data++); - chain5_fields[1].in_value = ReadyPos++; + uint8_t *ReadyPos = Readies; + while (count--) { + chain5_fields[0].out_value = (void *)(data++); + chain5_fields[1].in_value = ReadyPos++; - if (count > 0) - { - jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + if (count > 0) { + jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, + TAP_DRPAUSE); jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); } else - { jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE); - } } int retval = jtag_execute_queue(); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { unsigned error_count = 0; - for (size_t i = 0; i < readiesNum; i++) - { + for (size_t i = 0; i < readiesNum; i++) { if (Readies[i] != 1) - { error_count++; - } } - if (error_count > 0 ) - { + if (error_count > 0) { LOG_ERROR("%u words out of %u not transferred", error_count, readiesNum); retval = ERROR_FAIL; @@ -647,10 +631,16 @@ int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint return retval; } -int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count); +int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, + uint32_t opcode, + uint32_t *data, + size_t count); #ifndef HAVE_JTAG_MINIDRIVER_H -int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap, + uint32_t opcode, + uint32_t *data, + size_t count) { return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count); } @@ -675,7 +665,10 @@ int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opc * \param count Number of data words and instruction repetitions * */ -int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11, + uint32_t opcode, + uint32_t *data, + size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -683,29 +676,43 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opc arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap, opcode, data, count); + int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap, + opcode, + data, + count); if (retval != ERROR_OK) return retval; arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - struct scan_field chain5_fields[3]; - - arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); + struct scan_field chain5_fields[3]; + + arm11_setup_field(arm11, + 32, + NULL /*&Data*/, + NULL, + chain5_fields + 0); + arm11_setup_field(arm11, + 1, + NULL, + NULL /*&Ready*/, + chain5_fields + 1); + arm11_setup_field(arm11, + 1, + NULL, + NULL, + chain5_fields + 2); uint8_t ready_flag; chain5_fields[1].in_value = &ready_flag; - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain5_fields), chain5_fields, TAP_DRPAUSE); retval = jtag_execute_queue(); - if (retval == ERROR_OK) - { - if (ready_flag != 1) - { + if (retval == ERROR_OK) { + if (ready_flag != 1) { LOG_ERROR("last word not transferred"); retval = ERROR_FAIL; } @@ -726,7 +733,7 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opc * \param data Data word to be passed to the core via DTR * */ -int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data) +int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data) { return arm11_run_instr_data_to_core(arm11, opcode, &data, 1); } @@ -749,7 +756,10 @@ int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, * \param count Number of data words and instruction repetitions * */ -int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_from_core(struct arm11_common *arm11, + uint32_t opcode, + uint32_t *data, + size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -757,46 +767,42 @@ int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - struct scan_field chain5_fields[3]; + struct scan_field chain5_fields[3]; - uint32_t Data; - uint8_t Ready; - uint8_t nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; - arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); + arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); - while (count--) - { + while (count--) { int i = 0; - do - { - arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); + do { + arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE( + chain5_fields), chain5_fields, + count ? TAP_IDLE : TAP_DRPAUSE); CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", - (unsigned) Data, Ready, nRetry); + (unsigned) Data, Ready, nRetry); long long then = 0; if (i == 1000) - { then = timeval_ms(); - } - if (i >= 1000) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + if (i >= 1000) { + if ((timeval_ms()-then) > 1000) { + LOG_WARNING( + "Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } } i++; - } - while (!Ready); + } while (!Ready); *data++ = Data; } @@ -816,7 +822,9 @@ int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed. * */ -int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data) +int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11, + uint32_t opcode, + uint32_t *data) { int retval; retval = arm11_run_instr_no_data1(arm11, opcode); @@ -841,7 +849,7 @@ int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t * \param data Data word that will be written to r0 before \p opcode is executed * */ -int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data) +int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data) { int retval; /* MRC p14,0,r0,c0,c5,0 */ @@ -865,7 +873,7 @@ int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t op * \param count Number of instructions in the list. * */ -int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions, size_t count) +int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count) { int retval; @@ -875,45 +883,40 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - struct scan_field chain7_fields[3]; - - uint8_t nRW; - uint32_t DataOut; - uint8_t AddressOut; - uint8_t Ready; - uint32_t DataIn; - uint8_t AddressIn; - - arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); - arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); - arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); - - for (size_t i = 0; i < count + 1; i++) - { - if (i < count) - { - nRW = actions[i].write ? 1 : 0; - DataOut = actions[i].value; - AddressOut = actions[i].address; - } - else - { - nRW = 1; - DataOut = 0; - AddressOut = 0; + struct scan_field chain7_fields[3]; + + uint8_t nRW; + uint32_t DataOut; + uint8_t AddressOut; + uint8_t Ready; + uint32_t DataIn; + uint8_t AddressIn; + + arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); + arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); + arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); + + for (size_t i = 0; i < count + 1; i++) { + if (i < count) { + nRW = actions[i].write ? 1 : 0; + DataOut = actions[i].value; + AddressOut = actions[i].address; + } else { + nRW = 1; + DataOut = 0; + AddressOut = 0; } /* Timeout here so we don't get stuck. */ int i_n = 0; - while (1) - { + while (1) { JTAG_DEBUG("SC7 <= c%-3d Data %08x %s", - (unsigned) AddressOut, - (unsigned) DataOut, - nRW ? "write" : "read"); + (unsigned) AddressOut, + (unsigned) DataOut, + nRW ? "write" : "read"); arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields), - chain7_fields, TAP_DRPAUSE); + chain7_fields, TAP_DRPAUSE); CHECK_RETVAL(jtag_execute_queue()); @@ -924,14 +927,11 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions long long then = 0; if (i_n == 1000) - { then = timeval_ms(); - } - if (i_n >= 1000) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + if (i_n >= 1000) { + if ((timeval_ms()-then) > 1000) { + LOG_WARNING( + "Timeout (1000ms) waiting for instructions to complete"); return ERROR_FAIL; } } @@ -942,23 +942,15 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions if (!nRW) JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn); - if (i > 0) - { + if (i > 0) { if (actions[i - 1].address != AddressIn) - { LOG_WARNING("Scan chain 7 shifted out unexpected address"); - } if (!actions[i - 1].write) - { actions[i - 1].value = DataIn; - } - else - { + else { if (actions[i - 1].value != DataIn) - { LOG_WARNING("Scan chain 7 shifted out unexpected data"); - } } } } @@ -970,16 +962,15 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions * \param arm11 Target state variable. * */ -int arm11_sc7_clear_vbw(struct arm11_common * arm11) +int arm11_sc7_clear_vbw(struct arm11_common *arm11) { size_t clear_bw_size = arm11->brp + 1; - struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size); - struct arm11_sc7_action * pos = clear_bw; + struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size); + struct arm11_sc7_action *pos = clear_bw; - for (size_t i = 0; i < clear_bw_size; i++) - { - clear_bw[i].write = true; - clear_bw[i].value = 0; + for (size_t i = 0; i < clear_bw_size; i++) { + clear_bw[i].write = true; + clear_bw[i].value = 0; } for (size_t i = 0; i < arm11->brp; i++) @@ -990,7 +981,7 @@ int arm11_sc7_clear_vbw(struct arm11_common * arm11) int retval; retval = arm11_sc7_run(arm11, clear_bw, clear_bw_size); - free (clear_bw); + free(clear_bw); return retval; } @@ -1000,19 +991,17 @@ int arm11_sc7_clear_vbw(struct arm11_common * arm11) * \param arm11 Target state variable. * \param value Value to be written */ -int arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value) +int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value) { - struct arm11_sc7_action set_vcr; + struct arm11_sc7_action set_vcr; - set_vcr.write = true; - set_vcr.address = ARM11_SC7_VCR; - set_vcr.value = value; + set_vcr.write = true; + set_vcr.address = ARM11_SC7_VCR; + set_vcr.value = value; return arm11_sc7_run(arm11, &set_vcr, 1); } - - /** Read word from address * * \param arm11 Target state variable. @@ -1020,7 +1009,7 @@ int arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value) * \param result Pointer where to store result * */ -int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result) +int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result) { int retval; retval = arm11_run_instr_data_prepare(arm11); @@ -1036,7 +1025,6 @@ int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32 return arm11_run_instr_data_finish(arm11); } - /************************************************************************/ /* @@ -1060,31 +1048,31 @@ static int arm11_dpm_finish(struct arm_dpm *dpm) } static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { return arm11_run_instr_data_to_core(dpm_to_arm11(dpm), - opcode, &data, 1); + opcode, &data, 1); } static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm), - opcode, data); + opcode, data); } static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { return arm11_run_instr_data_from_core(dpm_to_arm11(dpm), - opcode, data, 1); + opcode, data, 1); } static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm), - opcode, data); + opcode, data); } /* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint @@ -1092,7 +1080,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm, * pre-allocated our vector, we don't need to worry about space. */ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, - uint32_t addr, uint32_t control) + uint32_t addr, uint32_t control) { struct arm11_common *arm11 = dpm_to_arm11(dpm); struct arm11_sc7_action *action; @@ -1110,17 +1098,17 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, action[1].value = control; switch (index_t) { - case 0 ... 15: - action[0].address = ARM11_SC7_BVR0 + index_t; - action[1].address = ARM11_SC7_BCR0 + index_t; - break; - case 16 ... 32: - index_t -= 16; - action[0].address = ARM11_SC7_WVR0 + index_t; - action[1].address = ARM11_SC7_WCR0 + index_t; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + action[0].address = ARM11_SC7_BVR0 + index_t; + action[1].address = ARM11_SC7_BCR0 + index_t; + break; + case 16 ... 32: + index_t -= 16; + action[0].address = ARM11_SC7_WVR0 + index_t; + action[1].address = ARM11_SC7_WCR0 + index_t; + break; + default: + return ERROR_FAIL; } arm11->bpwp_n += 2; @@ -1139,15 +1127,15 @@ static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) action[0].value = 0; switch (index_t) { - case 0 ... 15: - action[0].address = ARM11_SC7_BCR0 + index_t; - break; - case 16 ... 32: - index_t -= 16; - action[0].address = ARM11_SC7_WCR0 + index_t; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + action[0].address = ARM11_SC7_BCR0 + index_t; + break; + case 16 ... 32: + index_t -= 16; + action[0].address = ARM11_SC7_WCR0 + index_t; + break; + default: + return ERROR_FAIL; } arm11->bpwp_n += 1; diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h index e45bdc2..22d9dec 100644 --- a/src/target/arm11_dbgtap.h +++ b/src/target/arm11_dbgtap.h @@ -1,3 +1,25 @@ +/*************************************************************************** + * Copyright (C) 2008 digenius technology GmbH. * + * Michael Bruck * + * * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ + #ifndef ARM11_DBGTAP_H #define ARM11_DBGTAP_H @@ -37,10 +59,9 @@ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_fiel * Used with arm11_sc7_run to make a list of read/write commands for * scan chain 7 */ -struct arm11_sc7_action -{ - bool write; /**< Access mode: true for write, false for read. */ - uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */ +struct arm11_sc7_action { + bool write; /**< Access mode: true for write, false for read. */ + uint8_t address;/**< Register address mode. Use enum #arm11_sc7 */ /** * If write then set this to value to be written. In read mode * this receives the read value when the function returns. @@ -61,4 +82,4 @@ int arm11_read_memory_word(struct arm11_common *arm11, int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr); int arm11_bpwp_flush(struct arm11_common *arm11); -#endif // ARM11_DBGTAP_H +#endif /* ARM11_DBGTAP_H */ diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 94af0f7..a061a11 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -54,14 +55,12 @@ static int arm720t_scan_cp15(struct target *target, buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; @@ -71,24 +70,20 @@ static int arm720t_scan_cp15(struct target *target, fields[1].out_value = out_buf; fields[1].in_value = NULL; - if (in) - { + if (in) { fields[1].in_value = (uint8_t *)in; jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); } else - { jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); - } if (clock_arg) jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); @@ -254,8 +249,7 @@ static int arm720t_arch_state(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); - static const char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; @@ -300,16 +294,14 @@ static int arm720t_read_memory(struct target *target, struct arm720t_common *arm720t = target_to_arm720(target); /* disable cache, but leave MMU enabled */ - if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { retval = arm720t_disable_mmu_caches(target, 0, 1, 0); if (retval != ERROR_OK) return retval; } retval = arm7_9_read_memory(target, address, size, count, buffer); - if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { retval = arm720t_enable_mmu_caches(target, 0, 1, 0); if (retval != ERROR_OK) return retval; @@ -342,36 +334,26 @@ static int arm720t_soft_reset_halt(struct target *target) .eice_cache->reg_list[EICE_DBG_STAT]; struct arm *arm = &arm720t->arm7_9_common.arm; - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } long long then = timeval_ms(); int timeout; - while (!(timeout = ((timeval_ms()-then) > 1000))) - { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } } else - { break; - } if (debug_level >= 3) - { alive_sleep(100); - } else - { + else keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -399,10 +381,9 @@ static int arm720t_soft_reset_halt(struct target *target) arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -467,42 +448,35 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) if (retval != ERROR_OK) return retval; - - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { uint32_t opcode; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) - { + retval = arm720t_read_cp15(target, opcode, &value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); - } - else if (CMD_ARGC == 2) - { + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); - if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) - { + retval = arm720t_write_cp15(target, opcode, value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } @@ -518,8 +492,7 @@ static int arm720t_mrc(struct target *target, int cpnum, uint32_t CRn, uint32_t CRm, uint32_t *value) { - if (cpnum!=15) - { + if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } @@ -536,8 +509,7 @@ static int arm720t_mcr(struct target *target, int cpnum, uint32_t CRn, uint32_t CRm, uint32_t value) { - if (cpnum!=15) - { + if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } @@ -576,8 +548,7 @@ static const struct command_registration arm720t_command_handlers[] = { }; /** Holds methods for ARM720 targets. */ -struct target_type arm720t_target = -{ +struct target_type arm720t_target = { .name = "arm720t", .poll = arm7_9_poll, diff --git a/src/target/arm720t.h b/src/target/arm720t.h index e96f270..a3a6883 100644 --- a/src/target/arm720t.h +++ b/src/target/arm720t.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM720T_H #define ARM720T_H @@ -25,8 +26,7 @@ #define ARM720T_COMMON_MAGIC 0xa720a720 -struct arm720t_common -{ +struct arm720t_common { struct arm7_9_common arm7_9_common; uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; @@ -35,11 +35,9 @@ struct arm720t_common uint32_t far_reg; }; -static inline struct arm720t_common * -target_to_arm720(struct target *target) +static inline struct arm720t_common *target_to_arm720(struct target *target) { - return container_of(target->arch_info, struct arm720t_common, - arm7_9_common.arm); + return container_of(target->arch_info, struct arm720t_common, arm7_9_common.arm); } #endif /* ARM720T_H */ diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index a77004e..bf08194 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -28,6 +28,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -43,7 +44,6 @@ #include "register.h" #include "armv4_5.h" - /** * @file * Hold common code supporting the ARM7 and ARM9 core generations. @@ -93,26 +93,20 @@ static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9) */ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint) { - if (!arm7_9->wp0_used) - { + if (!arm7_9->wp0_used) { arm7_9->wp0_used = 1; breakpoint->set = 1; arm7_9->wp_available--; - } - else if (!arm7_9->wp1_used) - { + } else if (!arm7_9->wp1_used) { arm7_9->wp1_used = 1; breakpoint->set = 2; arm7_9->wp_available--; - } - else - { + } else LOG_ERROR("BUG: no hardware comparator available"); - } LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", - breakpoint->unique_id, - breakpoint->address, - breakpoint->set ); + breakpoint->unique_id, + breakpoint->address, + breakpoint->set); } /** @@ -120,60 +114,48 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br * * @param arm7_9 Pointer to common struct for ARM7/9 targets * @return Error codes if there is a problem finding a watchpoint or the result - * of executing the JTAG queue + * of executing the JTAG queue */ static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) { if (arm7_9->sw_breakpoints_added) - { return ERROR_OK; - } - if (arm7_9->wp_available < 1) - { + if (arm7_9->wp_available < 1) { LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } arm7_9->wp_available--; /* pick a breakpoint unit */ - if (!arm7_9->wp0_used) - { + if (!arm7_9->wp0_used) { arm7_9->sw_breakpoints_added = 1; arm7_9->wp0_used = 3; - } else if (!arm7_9->wp1_used) - { + } else if (!arm7_9->wp1_used) { arm7_9->sw_breakpoints_added = 2; arm7_9->wp1_used = 3; - } - else - { + } else { LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); return ERROR_FAIL; } - if (arm7_9->sw_breakpoints_added == 1) - { + if (arm7_9->sw_breakpoints_added == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - } - else if (arm7_9->sw_breakpoints_added == 2) - { + } else if (arm7_9->sw_breakpoints_added == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - } - else - { + } else { LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); return ERROR_FAIL; } LOG_DEBUG("SW BP using hw wp: %d", - arm7_9->sw_breakpoints_added ); + arm7_9->sw_breakpoints_added); return jtag_execute_queue(); } @@ -199,116 +181,99 @@ static int arm7_9_setup(struct target *target) * @param target Pointer to the target device to set the breakpoints on * @param breakpoint Pointer to the breakpoint to be set * @return For hardware breakpoints, this is the result of executing the JTAG - * queue. For software breakpoints, this will be the status of the - * required memory reads and writes + * queue. For software breakpoints, this will be the status of the + * required memory reads and writes */ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" , - breakpoint->unique_id, - breakpoint->address, - breakpoint->type); + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d", + breakpoint->unique_id, + breakpoint->address, + breakpoint->type); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */ uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u; /* reassign a hw breakpoint */ if (breakpoint->set == 0) - { arm7_9_assign_wp(arm7_9, breakpoint); - } - if (breakpoint->set == 1) - { + if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - } - else if (breakpoint->set == 2) - { + } else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - } - else - { + } else { LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } retval = jtag_execute_queue(); - } - else if (breakpoint->type == BKPT_SOFT) - { + } else if (breakpoint->type == BKPT_SOFT) { /* did we already set this breakpoint? */ if (breakpoint->set) return ERROR_OK; - if (breakpoint->length == 4) - { + if (breakpoint->length == 4) { uint32_t verify = 0xffffffff; /* keep the original instruction in target endianness */ - if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK) - { + /* write the breakpoint instruction in target + * endianness (arm7_9->arm_bkpt is host endian) */ + retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK) - { + retval = target_read_u32(target, breakpoint->address, &verify); + if (retval != ERROR_OK) return retval; - } - if (verify != arm7_9->arm_bkpt) - { - LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); + if (verify != arm7_9->arm_bkpt) { + LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 + " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } - } - else - { + } else { uint16_t verify = 0xffff; /* keep the original instruction in target endianness */ - if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */ - if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK) - { + /* write the breakpoint instruction in target + * endianness (arm7_9->thumb_bkpt is host endian) */ + retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK) - { + retval = target_read_u16(target, breakpoint->address, &verify); + if (retval != ERROR_OK) return retval; - } - if (verify != arm7_9->thumb_bkpt) - { - LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); + if (verify != arm7_9->thumb_bkpt) { + LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 + " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } } - if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) + retval = arm7_9_set_software_breakpoints(arm7_9); + if (retval != ERROR_OK) return retval; arm7_9->sw_breakpoint_count++; @@ -328,8 +293,8 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break * @param target Pointer to ARM7/9 target to unset the breakpoint from * @param breakpoint Pointer to breakpoint to be unset * @return For hardware breakpoints, this is the result of executing the JTAG - * queue. For software breakpoints, this will be the status of the - * required memory reads and writes + * queue. For software breakpoints, this will be the status of the + * required memory reads and writes */ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { @@ -337,80 +302,71 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre struct arm7_9_common *arm7_9 = target_to_arm7_9(target); LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, - breakpoint->unique_id, - breakpoint->address ); + breakpoint->unique_id, + breakpoint->address); - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { LOG_DEBUG("BPID: %d Releasing hw wp: %d", - breakpoint->unique_id, - breakpoint->set ); - if (breakpoint->set == 1) - { + breakpoint->unique_id, + breakpoint->set); + if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); arm7_9->wp0_used = 0; arm7_9->wp_available++; - } - else if (breakpoint->set == 2) - { + } else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->wp1_used = 0; arm7_9->wp_available++; } retval = jtag_execute_queue(); breakpoint->set = 0; - } - else - { + } else { /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) - { + if (breakpoint->length == 4) { uint32_t current_instr; /* check that user program as not modified breakpoint instruction */ - if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK) - { + retval = target_read_memory(target, + breakpoint->address, 4, 1, (uint8_t *)¤t_instr); + if (retval != ERROR_OK) return retval; - } - current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); - if (current_instr == arm7_9->arm_bkpt) - if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) - { + current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); + if (current_instr == arm7_9->arm_bkpt) { + retval = target_write_memory(target, + breakpoint->address, 4, 1, breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - } - else - { + } + + } else { uint16_t current_instr; /* check that user program as not modified breakpoint instruction */ - if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK) - { + retval = target_read_memory(target, + breakpoint->address, 2, 1, (uint8_t *)¤t_instr); + if (retval != ERROR_OK) return retval; - } current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); if (current_instr == arm7_9->thumb_bkpt) - if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_write_memory(target, + breakpoint->address, 2, 1, breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } + } - if (--arm7_9->sw_breakpoint_count==0) - { - /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */ + if (--arm7_9->sw_breakpoint_count == 0) { + /* We have removed the last sw breakpoint, clear the hw breakpoint we used + *to implement it */ if (arm7_9->sw_breakpoints_added == 1) - { - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0); - } + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[ + EICE_W0_CONTROL_VALUE], 0); else if (arm7_9->sw_breakpoints_added == 2) - { - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0); - } + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[ + EICE_W1_CONTROL_VALUE], 0); } breakpoint->set = 0; @@ -426,36 +382,31 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre * @param target Pointer to the target ARM7/9 device to add a breakpoint to * @param breakpoint Pointer to the breakpoint to be added * @return An error status if there is a problem adding the breakpoint or the - * result of setting the breakpoint + * result of setting the breakpoint */ int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9->breakpoint_count == 0) - { + if (arm7_9->breakpoint_count == 0) { /* make sure we don't have any dangling breakpoints. This is vital upon * GDB connect/disconnect */ arm7_9_clear_watchpoints(arm7_9); } - if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1)) { LOG_INFO("no watchpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((breakpoint->length != 2) && (breakpoint->length != 4)) - { + if ((breakpoint->length != 2) && (breakpoint->length != 4)) { LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if (breakpoint->type == BKPT_HARD) - { arm7_9_assign_wp(arm7_9, breakpoint); - } arm7_9->breakpoint_count++; @@ -470,29 +421,26 @@ int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint) * @param target Pointer to the target to have a breakpoint removed * @param breakpoint Pointer to the breakpoint to be removed * @return Error status if there was a problem unsetting the breakpoint or the - * watchpoints could not be cleared + * watchpoints could not be cleared */ int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) - { + retval = arm7_9_unset_breakpoint(target, breakpoint); + if (retval != ERROR_OK) return retval; - } if (breakpoint->type == BKPT_HARD) arm7_9->wp_available++; arm7_9->breakpoint_count--; - if (arm7_9->breakpoint_count == 0) - { + if (arm7_9->breakpoint_count == 0) { /* make sure we don't have any dangling breakpoints */ - if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK) - { + retval = arm7_9_clear_watchpoints(arm7_9); + if (retval != ERROR_OK) return retval; - } } return ERROR_OK; @@ -506,7 +454,7 @@ int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoin * @param target Pointer to an ARM7/9 target to set a watchpoint on * @param watchpoint Pointer to the watchpoint to be set * @return Error status if watchpoint set fails or the result of executing the - * JTAG queue + * JTAG queue */ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { @@ -517,8 +465,7 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch mask = watchpoint->length - 1; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -528,42 +475,45 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch else rw_mask = 1; - if (!arm7_9->wp0_used) - { - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address); + if (!arm7_9->wp0_used) { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], + watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], + watchpoint->mask); if (watchpoint->mask != 0xffffffffu) - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], + watchpoint->value); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], + 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], + EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } watchpoint->set = 1; arm7_9->wp0_used = 2; - } - else if (!arm7_9->wp1_used) - { - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address); + } else if (!arm7_9->wp1_used) { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], + watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], + watchpoint->mask); if (watchpoint->mask != 0xffffffffu) - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], + watchpoint->value); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], + 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], + EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } watchpoint->set = 2; arm7_9->wp1_used = 2; - } - else - { + } else { LOG_ERROR("BUG: no hardware comparator available"); return ERROR_OK; } @@ -584,34 +534,27 @@ static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *wat int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!watchpoint->set) - { + if (!watchpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (watchpoint->set == 1) - { + if (watchpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } arm7_9->wp0_used = 0; - } - else if (watchpoint->set == 2) - { + } else if (watchpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } arm7_9->wp1_used = 0; } watchpoint->set = 0; @@ -632,14 +575,10 @@ int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (arm7_9->wp_available < 1) - { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4)) - { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } arm7_9->wp_available--; @@ -659,12 +598,10 @@ int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoin int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (watchpoint->set) - { - if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK) - { + if (watchpoint->set) { + retval = arm7_9_unset_watchpoint(target, watchpoint); + if (retval != ERROR_OK) return retval; - } } arm7_9->wp_available++; @@ -679,7 +616,7 @@ int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoin * * @param target Pointer to target to issue commands to * @return Error status if there is a timeout or a problem while executing the - * JTAG queue + * JTAG queue */ int arm7_9_execute_sys_speed(struct target *target) { @@ -701,26 +638,23 @@ int arm7_9_execute_sys_speed(struct target *target) long long then = timeval_ms(); int timeout; - while (!(timeout = ((timeval_ms()-then) > 1000))) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) - && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) + && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) break; if (debug_level >= 3) - { alive_sleep(100); - } else - { + else keep_alive(); - } } - if (timeout) - { - LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); + if (timeout) { + LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", + buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); return ERROR_TARGET_TIMEOUT; } @@ -737,7 +671,7 @@ int arm7_9_execute_sys_speed(struct target *target) */ static int arm7_9_execute_fast_sys_speed(struct target *target) { - static int set = 0; + static int set; static uint8_t check_value[4], check_mask[4]; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -756,8 +690,7 @@ static int arm7_9_execute_fast_sys_speed(struct target *target) if (retval != ERROR_OK) return retval; - if (!set) - { + if (!set) { /* check for DBGACK and SYSCOMP set (others don't care) */ /* NB! These are constants that must be available until after next jtag_execute() and @@ -797,9 +730,7 @@ int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *bu /* return the 32-bit ints in the 8-bit array */ for (i = 0; i < size; i++) - { h_u32_to_le(buffer + (i * 4), data[i]); - } free(data); @@ -813,7 +744,7 @@ int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *bu * * @param priv Void pointer expected to be a struct target pointer * @return ERROR_OK unless there are issues with the JTAG queue or when reading - * from the Embedded ICE unit + * from the Embedded ICE unit */ static int arm7_9_handle_target_request(void *priv) { @@ -828,28 +759,23 @@ static int arm7_9_handle_target_request(void *priv) if (!target->dbg_msg_enabled) return ERROR_OK; - if (target->state == TARGET_RUNNING) - { + if (target->state == TARGET_RUNNING) { /* read DCC control register */ embeddedice_read_reg(dcc_control); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } /* check W bit */ - if (buf_get_u32(dcc_control->value, 1, 1) == 1) - { + if (buf_get_u32(dcc_control->value, 1, 1) == 1) { uint32_t request; - if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK) - { + retval = embeddedice_receive(jtag_info, &request, 1); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_request(target, request)) != ERROR_OK) - { + retval = target_request(target, request); + if (retval != ERROR_OK) return retval; - } } } @@ -862,11 +788,12 @@ static int arm7_9_handle_target_request(void *priv) * what happens: * * <table> - * <tr><th > State</th><th > Action</th></tr> - * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr> - * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr> - * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr> - * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr> + * <tr><th > State</th><th > Action</th></tr> + * <tr><td > TARGET_RUNNING | TARGET_RESET</td> + * <td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr> + * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr> + * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr> + * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr> * </table> * * If the target does not end up in the halted state, a warning is produced. If @@ -884,53 +811,46 @@ int arm7_9_poll(struct target *target) /* read debug status register */ embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) - { -/* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/ - if (target->state == TARGET_UNKNOWN) - { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) { + /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, *32));*/ + if (target->state == TARGET_UNKNOWN) { /* Starting OpenOCD with target in debug-halt */ target->state = TARGET_RUNNING; LOG_DEBUG("DBGACK already set during server startup."); } - if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) - { + if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { target->state = TARGET_HALTED; - if ((retval = arm7_9_debug_entry(target)) != ERROR_OK) + retval = arm7_9_debug_entry(target); + if (retval != ERROR_OK) return retval; if (arm_semihosting(target, &retval) != 0) return retval; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (retval != ERROR_OK) return retval; - } } - if (target->state == TARGET_DEBUG_RUNNING) - { + if (target->state == TARGET_DEBUG_RUNNING) { target->state = TARGET_HALTED; - if ((retval = arm7_9_debug_entry(target)) != ERROR_OK) + retval = arm7_9_debug_entry(target); + if (retval != ERROR_OK) return retval; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); + if (retval != ERROR_OK) return retval; - } } if (target->state != TARGET_HALTED) - { - LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state); - } - } - else - { + LOG_WARNING( + "DBGACK set, but the target did not end up in the halted state %d", + target->state); + } else { if (target->state != TARGET_DEBUG_RUNNING) target->state = TARGET_RUNNING; } @@ -955,8 +875,7 @@ int arm7_9_assert_reset(struct target *target) enum reset_types jtag_reset_config = jtag_get_reset_config(); bool use_event = false; - LOG_DEBUG("target->state: %s", - target_state_name(target)); + LOG_DEBUG("target->state: %s", target_state_name(target)); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) use_event = true; @@ -976,16 +895,13 @@ int arm7_9_assert_reset(struct target *target) */ bool srst_asserted = false; - if (!use_event - && !(jtag_reset_config & RESET_SRST_PULLS_TRST) - && (jtag_reset_config & RESET_SRST_NO_GATING)) - { + if (!use_event && !(jtag_reset_config & RESET_SRST_PULLS_TRST) + && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); srst_asserted = true; } - if (target->reset_halt) - { + if (target->reset_halt) { /* * For targets that don't support communication while SRST is * asserted, we need to set up the reset vector catch first. @@ -994,42 +910,30 @@ int arm7_9_assert_reset(struct target *target) * reset, these settings may well be reset anyway; so setting * them here won't matter. */ - if (arm7_9->has_vector_catch) - { + if (arm7_9->has_vector_catch) { /* program vector catch register to catch reset */ - embeddedice_write_reg(&arm7_9->eice_cache - ->reg_list[EICE_VEC_CATCH], 0x1); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1); /* extra runtest added as issues were found with * certain ARM9 cores (maybe more) - AT91SAM9260 * and STR9 */ jtag_add_runtest(1, TAP_IDLE); - } - else - { + } else { /* program watchpoint unit to match on reset vector * address */ - embeddedice_write_reg(&arm7_9->eice_cache - ->reg_list[EICE_W0_ADDR_VALUE], 0x0); - embeddedice_write_reg(&arm7_9->eice_cache - ->reg_list[EICE_W0_ADDR_MASK], 0x3); - embeddedice_write_reg(&arm7_9->eice_cache - ->reg_list[EICE_W0_DATA_MASK], - 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache - ->reg_list[EICE_W0_CONTROL_VALUE], - EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache - ->reg_list[EICE_W0_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); } } - if (use_event) { + if (use_event) target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - } else { + else { /* If we use SRST ... we'd like to issue just SRST, but the * board or chip may be set up so we have to assert TRST as * well. On some chips that combination is equivalent to a @@ -1046,10 +950,7 @@ int arm7_9_assert_reset(struct target *target) register_cache_invalidate(arm7_9->arm.core_cache); /* REVISIT why isn't standard debug entry logic sufficient?? */ - if (target->reset_halt - && (!(jtag_reset_config & RESET_SRST_PULLS_TRST) - || use_event)) - { + if (target->reset_halt && (!(jtag_reset_config & RESET_SRST_PULLS_TRST) || use_event)) { /* debug entry was prepared above */ target->debug_reason = DBG_REASON_DBGRQ; } @@ -1069,8 +970,7 @@ int arm7_9_assert_reset(struct target *target) int arm7_9_deassert_reset(struct target *target) { int retval = ERROR_OK; - LOG_DEBUG("target->state: %s", - target_state_name(target)); + LOG_DEBUG("target->state: %s", target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -1082,22 +982,21 @@ int arm7_9_deassert_reset(struct target *target) * error messages as halt will believe that reset is * still in effect. */ - if ((retval = target_examine_one(target)) != ERROR_OK) + retval = target_examine_one(target); + if (retval != ERROR_OK) return retval; - if ((retval = target_poll(target)) != ERROR_OK) - { + retval = target_poll(target); + if (retval != ERROR_OK) return retval; - } enum reset_types jtag_reset_config = jtag_get_reset_config(); - if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) - { - LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset."); - if ((retval = target_halt(target)) != ERROR_OK) - { + if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) { + LOG_WARNING( + "srst pulls trst - can not reset into halted mode. Issuing halt after reset."); + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } } return retval; } @@ -1117,36 +1016,31 @@ static int arm7_9_clear_halt(struct target *target) struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; /* we used DBGRQ only if we didn't come out of reset */ - if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq) - { + if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq) { /* program EmbeddedICE Debug Control Register to deassert DBGRQ */ buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0); embeddedice_store_reg(dbg_ctrl); - } - else - { - if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch) - { + } else { + if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch) { /* if we came out of reset, and vector catch is supported, we used * vector catch to enter debug state * restore the register in that case */ embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]); - } - else - { + } else { /* restore registers if watchpoint unit 0 was in use */ - if (arm7_9->wp0_used) - { + if (arm7_9->wp0_used) { if (arm7_9->debug_entry_from_reset) - { - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]); - } - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]); - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[ + EICE_W0_ADDR_VALUE]); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[ + EICE_W0_ADDR_MASK]); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[ + EICE_W0_DATA_MASK]); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[ + EICE_W0_CONTROL_MASK]); } /* control value always has to be restored, as it was either disabled, * or enabled with possibly different bits @@ -1184,28 +1078,25 @@ int arm7_9_soft_reset_halt(struct target *target) * */ - if ((retval = target_halt(target)) != ERROR_OK) + retval = target_halt(target); + if (retval != ERROR_OK) return retval; long long then = timeval_ms(); int timeout; - while (!(timeout = ((timeval_ms()-then) > 1000))) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; if (debug_level >= 3) - { alive_sleep(100); - } else - { + else keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -1219,14 +1110,12 @@ int arm7_9_soft_reset_halt(struct target *target) buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1); embeddedice_store_reg(dbg_ctrl); - if ((retval = arm7_9_clear_halt(target)) != ERROR_OK) - { + retval = arm7_9_clear_halt(target); + if (retval != ERROR_OK) return retval; - } /* if the target is in Thumb state, change to ARM state */ - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) - { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) { uint32_t r0_thumb, pc_thumb; LOG_DEBUG("target entered debug from Thumb state, changing to ARM"); /* Entered debug from Thumb mode */ @@ -1254,8 +1143,7 @@ int arm7_9_soft_reset_halt(struct target *target) arm->pc->valid = 1; /* reset registers */ - for (i = 0; i <= 14; i++) - { + for (i = 0; i <= 14; i++) { struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, 0xffffffff); @@ -1263,10 +1151,9 @@ int arm7_9_soft_reset_halt(struct target *target) r->valid = 1; } - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -1282,9 +1169,9 @@ int arm7_9_soft_reset_halt(struct target *target) */ int arm7_9_halt(struct target *target) { - if (target->state == TARGET_RESET) - { - LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()"); + if (target->state == TARGET_RESET) { + LOG_ERROR( + "BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()"); return ERROR_OK; } @@ -1292,38 +1179,34 @@ int arm7_9_halt(struct target *target) struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", - target_state_name(target)); + target_state_name(target)); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - { LOG_WARNING("target was in unknown state when halt was requested"); - } - if (arm7_9->use_dbgrq) - { + if (arm7_9->use_dbgrq) { /* program EmbeddedICE Debug Control Register to assert DBGRQ */ - if (arm7_9->set_special_dbgrq) { + if (arm7_9->set_special_dbgrq) arm7_9->set_special_dbgrq(target); - } else { + else { buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1); embeddedice_store_reg(dbg_ctrl); } - } - else - { + } else { /* program watchpoint unit to match on any address */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], + EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], + ~EICE_W_CTRL_nOPC & 0xff); } target->debug_reason = DBG_REASON_DBGRQ; @@ -1346,7 +1229,7 @@ static int arm7_9_debug_entry(struct target *target) { int i; uint32_t context[16]; - uint32_t* context_p[16]; + uint32_t *context_p[16]; uint32_t r0_thumb, pc_thumb; uint32_t cpsr, cpsr_mask = 0; int retval; @@ -1367,29 +1250,25 @@ static int arm7_9_debug_entry(struct target *target) buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1); embeddedice_store_reg(dbg_ctrl); - if ((retval = arm7_9_clear_halt(target)) != ERROR_OK) - { + retval = arm7_9_clear_halt(target); + if (retval != ERROR_OK) return retval; - } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } - if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK) + retval = arm7_9->examine_debug_reason(target); + if (retval != ERROR_OK) return retval; - - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } /* if the target is in Thumb state, change to ARM state */ - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) - { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) { LOG_DEBUG("target entered debug from Thumb state"); /* Entered debug from Thumb mode */ arm->core_state = ARM_STATE_THUMB; @@ -1420,7 +1299,8 @@ static int arm7_9_debug_entry(struct target *target) arm7_9->read_xpsr(target, &cpsr, 0); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; /* Sync our CPSR copy with J or T bits EICE reported, but @@ -1428,23 +1308,20 @@ static int arm7_9_debug_entry(struct target *target) */ arm_set_cpsr(arm, cpsr | cpsr_mask); - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } LOG_DEBUG("target entered debug state in %s mode", - arm_mode_name(arm->core_mode)); + arm_mode_name(arm->core_mode)); - if (arm->core_state == ARM_STATE_THUMB) - { + if (arm->core_state == ARM_STATE_THUMB) { LOG_DEBUG("thumb state, applying fixups"); context[0] = r0_thumb; context[15] = pc_thumb; - } else if (arm->core_state == ARM_STATE_ARM) - { + } else if (arm->core_state == ARM_STATE_ARM) { /* adjust value stored by STM */ context[15] -= 3 * 4; } @@ -1452,10 +1329,10 @@ static int arm7_9_debug_entry(struct target *target) if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq)) context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); else - context[15] -= arm7_9->dbgreq_adjust_pc * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); + context[15] -= arm7_9->dbgreq_adjust_pc * + ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { struct reg *r = arm_reg_current(arm, i); LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); @@ -1472,20 +1349,19 @@ static int arm7_9_debug_entry(struct target *target) if (arm->spsr) { uint32_t spsr; arm7_9->read_xpsr(target, &spsr, 1); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } buf_set_u32(arm->spsr->value, 0, 32, spsr); arm->spsr->dirty = 0; arm->spsr->valid = 1; } - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - if (arm7_9->post_debug_entry) - { + if (arm7_9->post_debug_entry) { retval = arm7_9->post_debug_entry(target); if (retval != ERROR_OK) return retval; @@ -1512,14 +1388,12 @@ static int arm7_9_full_context(struct target *target) LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -1527,41 +1401,43 @@ static int arm7_9_full_context(struct target *target) /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS */ - for (i = 0; i < 6; i++) - { + for (i = 0; i < 6; i++) { uint32_t mask = 0; - uint32_t* reg_p[16]; + uint32_t *reg_p[16]; int j; int valid = 1; /* check if there are invalid registers in the current mode */ - for (j = 0; j <= 16; j++) - { + for (j = 0; j <= 16; j++) { if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) valid = 0; } - if (!valid) - { + if (!valid) { uint32_t tmp_cpsr; /* change processor mode (and mask T bit) */ tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) - & 0xe0; + & 0xe0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); - for (j = 0; j < 15; j++) - { - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) - { - reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, - armv4_5_number_to_mode(i), j).value; + for (j = 0; j < 15; j++) { + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), j).valid == 0) { + reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE( + arm->core_cache, + armv4_5_number_to_mode(i), + j).value; mask |= 1 << j; - ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid = 1; - ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; + ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), + j).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), + j).dirty = 0; } } @@ -1570,25 +1446,26 @@ static int arm7_9_full_context(struct target *target) arm7_9->read_core_regs(target, mask, reg_p); /* check if the PSR has to be read */ - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid == 0) - { - arm7_9->read_xpsr(target, (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), + 16).valid == 0) { + arm7_9->read_xpsr(target, + (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).value, 1); - ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; - ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), + 16).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), + 16).dirty = 0; } } } /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, - 0, 0); + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -1602,7 +1479,7 @@ static int arm7_9_full_context(struct target *target) * * @param target Pointer to the ARM7/9 target to have its context restored * @return Error status if the target is not halted or the core mode in the - * armv4_5 struct is invalid. + * armv4_5 struct is invalid. */ static int arm7_9_restore_context(struct target *target) { @@ -1616,8 +1493,7 @@ static int arm7_9_restore_context(struct target *target) LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1625,8 +1501,7 @@ static int arm7_9_restore_context(struct target *target) if (arm7_9->pre_restore_context) arm7_9->pre_restore_context(target); - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -1634,51 +1509,42 @@ static int arm7_9_restore_context(struct target *target) /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS */ - for (i = 0; i < 6; i++) - { + for (i = 0; i < 6; i++) { LOG_DEBUG("examining %s mode", - arm_mode_name(arm->core_mode)); + arm_mode_name(arm->core_mode)); dirty = 0; mode_change = 0; /* check if there are dirty registers in the current mode */ - for (j = 0; j <= 16; j++) - { + for (j = 0; j <= 16; j++) { reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); - if (reg->dirty == 1) - { - if (reg->valid == 1) - { + if (reg->dirty == 1) { + if (reg->valid == 1) { dirty = 1; LOG_DEBUG("examining dirty reg: %s", reg->name); struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; if ((reg_arch_info->mode != ARM_MODE_ANY) - && (reg_arch_info->mode != current_mode) - && !((reg_arch_info->mode == ARM_MODE_USR) - && (arm->core_mode == ARM_MODE_SYS)) - && !((reg_arch_info->mode == ARM_MODE_SYS) - && (arm->core_mode == ARM_MODE_USR))) - { + && (reg_arch_info->mode != current_mode) + && !((reg_arch_info->mode == ARM_MODE_USR) + && (arm->core_mode == ARM_MODE_SYS)) + && !((reg_arch_info->mode == ARM_MODE_SYS) + && (arm->core_mode == ARM_MODE_USR))) { mode_change = 1; LOG_DEBUG("require mode change"); } - } - else - { - LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name); - } + } else + LOG_ERROR("BUG: dirty register '%s', but no valid data", + reg->name); } } - if (dirty) - { + if (dirty) { uint32_t mask = 0x0; int num_regs = 0; uint32_t regs[16]; - if (mode_change) - { + if (mode_change) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ @@ -1690,12 +1556,12 @@ static int arm7_9_restore_context(struct target *target) current_mode = armv4_5_number_to_mode(i); } - for (j = 0; j <= 14; j++) - { - reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); + for (j = 0; j <= 14; j++) { + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), + j); - if (reg->dirty == 1) - { + if (reg->dirty == 1) { regs[j] = buf_get_u32(reg->value, 0, 32); mask |= 1 << j; num_regs++; @@ -1709,16 +1575,17 @@ static int arm7_9_restore_context(struct target *target) } if (mask) - { arm7_9->write_core_regs(target, mask, regs); - } - reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16); + reg = + &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode( + i), 16); struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; - if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) - { - LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32)); + if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) { + LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", + i, + buf_get_u32(reg->value, 0, 32)); arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1); } } @@ -1737,17 +1604,17 @@ static int arm7_9_restore_context(struct target *target) } else if (arm->cpsr->dirty) { /* CPSR has been changed, full restore necessary (mask T bit) */ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(arm->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); arm7_9->write_xpsr(target, - buf_get_u32(arm->cpsr->value, 0, 32) - & ~0x20, 0); + buf_get_u32(arm->cpsr->value, 0, 32) + & ~0x20, 0); arm->cpsr->dirty = 0; arm->cpsr->valid = 1; } /* restore PC */ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, - buf_get_u32(arm->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32)); arm->pc->dirty = 0; @@ -1794,8 +1661,7 @@ static void arm7_9_enable_watchpoints(struct target *target) { struct watchpoint *watchpoint = target->watchpoints; - while (watchpoint) - { + while (watchpoint) { if (watchpoint->set == 0) arm7_9_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; @@ -1813,14 +1679,17 @@ static void arm7_9_enable_breakpoints(struct target *target) struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ - while (breakpoint) - { + while (breakpoint) { arm7_9_set_breakpoint(target, breakpoint); breakpoint = breakpoint->next; } } -int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +int arm7_9_resume(struct target *target, + int current, + uint32_t address, + int handle_breakpoints, + int debug_execution) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; @@ -1829,16 +1698,13 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!debug_execution) - { target_free_all_working_areas(target); - } /* current = 1: continue on current pc, otherwise continue at <address> */ if (!current) @@ -1848,26 +1714,27 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand current_pc = buf_get_u32(arm->pc->value, 0, 32); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { struct breakpoint *breakpoint; breakpoint = breakpoint_find(target, buf_get_u32(arm->pc->value, 0, 32)); - if (breakpoint != NULL) - { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id ); - if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) - { + if (breakpoint != NULL) { + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", + breakpoint->address, + breakpoint->unique_id); + retval = arm7_9_unset_breakpoint(target, breakpoint); + if (retval != ERROR_OK) return retval; - } /* calculate PC of next instruction */ uint32_t next_pc; - if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) - { + retval = arm_simulate_step(target, &next_pc); + if (retval != ERROR_OK) { uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); + LOG_ERROR( + "Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", + current_opcode); return retval; } @@ -1876,7 +1743,8 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand target->debug_reason = DBG_REASON_SINGLESTEP; - if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + retval = arm7_9_restore_context(target); + if (retval != ERROR_OK) return retval; if (arm->core_state == ARM_STATE_ARM) @@ -1889,18 +1757,17 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand } buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0); - embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size)); + embeddedice_write_reg(dbg_ctrl, + buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size)); err = arm7_9_execute_sys_speed(target); LOG_DEBUG("disable single-step"); arm7_9->disable_single_step(target); - if (err != ERROR_OK) - { - if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) - { + if (err != ERROR_OK) { + retval = arm7_9_set_breakpoint(target, breakpoint); + if (retval != ERROR_OK) return retval; - } target->state = TARGET_UNKNOWN; return err; } @@ -1909,13 +1776,12 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand if (retval != ERROR_OK) return retval; LOG_DEBUG("new PC after step: 0x%8.8" PRIx32, - buf_get_u32(arm->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); - if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) - { + retval = arm7_9_set_breakpoint(target, breakpoint); + if (retval != ERROR_OK) return retval; - } } } @@ -1923,7 +1789,8 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand arm7_9_enable_breakpoints(target); arm7_9_enable_watchpoints(target); - if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + retval = arm7_9_restore_context(target); + if (retval != ERROR_OK) return retval; if (arm->core_state == ARM_STATE_ARM) @@ -1942,30 +1809,24 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0); embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size)); - if ((retval = arm7_9_restart_core(target)) != ERROR_OK) - { + retval = arm7_9_restart_core(target); + if (retval != ERROR_OK) return retval; - } target->debug_reason = DBG_REASON_NOTHALTED; - if (!debug_execution) - { + if (!debug_execution) { /* registers are now invalid */ register_cache_invalidate(arm->core_cache); target->state = TARGET_RUNNING; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if (retval != ERROR_OK) return retval; - } - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); + if (retval != ERROR_OK) return retval; - } } LOG_DEBUG("target resumed"); @@ -1980,24 +1841,25 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) uint32_t current_pc; current_pc = buf_get_u32(arm->pc->value, 0, 32); - if (next_pc != current_pc) - { + if (next_pc != current_pc) { /* setup an inverse breakpoint on the current PC * - comparator 1 matches the current address * - rangeout from comparator 1 is connected to comparator 0 rangein * - comparator 0 matches any address, as long as rangein is low */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], + EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], + ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], + current_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); - } - else - { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], + ~EICE_W_CTRL_nOPC & 0xff); + } else { embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); @@ -2005,8 +1867,10 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], + EICE_W_CTRL_ENABLE); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], + ~EICE_W_CTRL_nOPC & 0xff); } } @@ -2032,8 +1896,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle struct breakpoint *breakpoint = NULL; int err, retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2057,15 +1920,18 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle /* calculate PC of next instruction */ uint32_t next_pc; - if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) - { + retval = arm_simulate_step(target, &next_pc); + if (retval != ERROR_OK) { uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); + LOG_ERROR( + "Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", + current_opcode); return retval; } - if ((retval = arm7_9_restore_context(target)) != ERROR_OK) + retval = arm7_9_restore_context(target); + if (retval != ERROR_OK) return retval; arm7_9->enable_single_step(target, next_pc); @@ -2079,10 +1945,9 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle return ERROR_FAIL; } - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED); + if (retval != ERROR_OK) return retval; - } err = arm7_9_execute_sys_speed(target); arm7_9->disable_single_step(target); @@ -2091,32 +1956,30 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle register_cache_invalidate(arm->core_cache); if (err != ERROR_OK) - { target->state = TARGET_UNKNOWN; - } else { + else { retval = arm7_9_debug_entry(target); if (retval != ERROR_OK) return retval; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (retval != ERROR_OK) return retval; - } LOG_DEBUG("target stepped"); } - if (breakpoint) - if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) - { + if (breakpoint) { + retval = arm7_9_set_breakpoint(target, breakpoint); + if (retval != ERROR_OK) return retval; - } + } return err; } static int arm7_9_read_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode) + int num, enum arm_mode mode) { - uint32_t* reg_p[16]; + uint32_t *reg_p[16]; int retval; struct arm_reg *areg = r->arch_info; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2127,10 +1990,8 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, if ((num < 0) || (num > 16)) return ERROR_COMMAND_SYNTAX_ERROR; - if ((mode != ARM_MODE_ANY) - && (mode != arm->core_mode) - && (areg->mode != ARM_MODE_ANY)) - { + if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) + && (areg->mode != ARM_MODE_ANY)) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ @@ -2141,44 +2002,38 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, } uint32_t value = 0; - if ((num >= 0) && (num <= 15)) - { + if ((num >= 0) && (num <= 15)) { /* read a normal core register */ reg_p[num] = &value; arm7_9->read_core_regs(target, 1 << num, reg_p); - } - else - { + } else { /* read a program status register * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr */ arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY); } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } r->valid = 1; r->dirty = 0; buf_set_u32(r->value, 0, 32, value); - if ((mode != ARM_MODE_ANY) - && (mode != arm->core_mode) - && (areg->mode != ARM_MODE_ANY)) { + if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) + && (areg->mode != ARM_MODE_ANY)) { /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(arm->cpsr->value, 0, 8) - & ~0x20, 0, 0); + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); } return ERROR_OK; } static int arm7_9_write_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode, uint32_t value) + int num, enum arm_mode mode, uint32_t value) { uint32_t reg[16]; struct arm_reg *areg = r->arch_info; @@ -2190,9 +2045,8 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, if ((num < 0) || (num > 16)) return ERROR_COMMAND_SYNTAX_ERROR; - if ((mode != ARM_MODE_ANY) - && (mode != arm->core_mode) - && (areg->mode != ARM_MODE_ANY)) { + if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) + && (areg->mode != ARM_MODE_ANY)) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ @@ -2202,15 +2056,12 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); } - if ((num >= 0) && (num <= 15)) - { + if ((num >= 0) && (num <= 15)) { /* write a normal core register */ reg[num] = value; arm7_9->write_core_regs(target, 1 << num, reg); - } - else - { + } else { /* write a program status register * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr */ @@ -2226,19 +2077,21 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, r->valid = 1; r->dirty = 0; - if ((mode != ARM_MODE_ANY) - && (mode != arm->core_mode) - && (areg->mode != ARM_MODE_ANY)) { + if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) + && (areg->mode != ARM_MODE_ANY)) { /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(arm->cpsr->value, 0, 8) - & ~0x20, 0, 0); + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); } return jtag_execute_queue(); } -int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_read_memory(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; @@ -2250,10 +2103,10 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u int retval; int last_reg = 0; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + address, size, count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2271,13 +2124,12 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u int j = 0; - switch (size) - { + switch (size) { case 4: - while (num_accesses < count) - { + while (num_accesses < count) { uint32_t reg_list; - thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; if (last_reg <= thisrun_accesses) @@ -2302,22 +2154,19 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u num_accesses += thisrun_accesses; if ((j++%1024) == 0) - { keep_alive(); - } } break; case 2: - while (num_accesses < count) - { + while (num_accesses < count) { uint32_t reg_list; - thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { if (i > last_reg) - last_reg = i; + last_reg = i; arm7_9->load_hword_reg(target, i); /* fast memory reads are only safe when the target is running * from a sufficiently high clock (32 kHz is usually too slow) @@ -2327,9 +2176,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u else retval = arm7_9_execute_sys_speed(target); if (retval != ERROR_OK) - { return retval; - } } @@ -2340,20 +2187,17 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u num_accesses += thisrun_accesses; if ((j++%1024) == 0) - { keep_alive(); - } } break; case 1: - while (num_accesses < count) - { + while (num_accesses < count) { uint32_t reg_list; - thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { if (i > last_reg) last_reg = i; arm7_9->load_byte_reg(target, i); @@ -2365,9 +2209,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u else retval = arm7_9_execute_sys_speed(target); if (retval != ERROR_OK) - { return retval; - } } arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); @@ -2377,9 +2219,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u num_accesses += thisrun_accesses; if ((j++%1024) == 0) - { keep_alive(); - } } break; } @@ -2389,24 +2229,26 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u for (i = 0; i <= last_reg; i++) { struct reg *r = arm_reg_current(arm, i); - r->dirty = r->valid; } arm7_9->read_xpsr(target, &cpsr, 0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while reading cpsr"); return ERROR_TARGET_DATA_ABORT; } - if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) - { - LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); + if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { + LOG_WARNING( + "memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", + address, + size, + count); arm7_9->write_xpsr_im8(target, - buf_get_u32(arm->cpsr->value, 0, 8) - & ~0x20, 0, 0); + buf_get_u32(arm->cpsr->value, 0, 8) + & ~0x20, 0, 0); return ERROR_TARGET_DATA_ABORT; } @@ -2414,7 +2256,11 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u return ERROR_OK; } -int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) +int arm7_9_write_memory(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; @@ -2432,8 +2278,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); #endif - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2453,17 +2298,15 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0); embeddedice_store_reg(dbg_ctrl); - switch (size) - { + switch (size) { case 4: - while (num_accesses < count) - { + while (num_accesses < count) { uint32_t reg_list; - thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { if (i > last_reg) last_reg = i; reg[i] = target_buffer_get_u32(target, buffer); @@ -2479,8 +2322,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, */ if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); - else - { + else { retval = arm7_9_execute_sys_speed(target); /* @@ -2495,22 +2337,19 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, } if (retval != ERROR_OK) - { return retval; - } num_accesses += thisrun_accesses; } break; case 2: - while (num_accesses < count) - { + while (num_accesses < count) { uint32_t reg_list; - thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { if (i > last_reg) last_reg = i; reg[i] = target_buffer_get_u16(target, buffer) & 0xffff; @@ -2519,8 +2358,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, arm7_9->write_core_regs(target, reg_list, reg); - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { arm7_9->store_hword_reg(target, i); /* fast memory writes are only safe when the target is running @@ -2528,39 +2366,35 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, */ if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); - else - { + else { retval = arm7_9_execute_sys_speed(target); - /* - * if memory writes are made when the clock is running slow - * (i.e. 32 kHz) which is necessary in some scripts to reconfigure - * processor operations after a "reset halt" or "reset init", - * need to immediately stroke the keep alive or will end up with - * gdb "keep alive not sent error message" problem. - */ + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ - keep_alive(); + keep_alive(); } if (retval != ERROR_OK) - { return retval; - } } num_accesses += thisrun_accesses; } break; case 1: - while (num_accesses < count) - { + while (num_accesses < count) { uint32_t reg_list; - thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { if (i > last_reg) last_reg = i; reg[i] = *buffer++ & 0xff; @@ -2568,33 +2402,29 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, arm7_9->write_core_regs(target, reg_list, reg); - for (i = 1; i <= thisrun_accesses; i++) - { + for (i = 1; i <= thisrun_accesses; i++) { arm7_9->store_byte_reg(target, i); /* fast memory writes are only safe when the target is running * from a sufficiently high clock (32 kHz is usually too slow) */ if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); - else - { - retval = arm7_9_execute_sys_speed(target); + else { + retval = arm7_9_execute_sys_speed(target); - /* - * if memory writes are made when the clock is running slow - * (i.e. 32 kHz) which is necessary in some scripts to reconfigure - * processor operations after a "reset halt" or "reset init", - * need to immediately stroke the keep alive or will end up with - * gdb "keep alive not sent error message" problem. - */ + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ - keep_alive(); - } + keep_alive(); + } if (retval != ERROR_OK) - { return retval; - } } @@ -2612,24 +2442,26 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, for (i = 0; i <= last_reg; i++) { struct reg *r = arm_reg_current(arm, i); - r->dirty = r->valid; } arm7_9->read_xpsr(target, &cpsr, 0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while reading cpsr"); return ERROR_TARGET_DATA_ABORT; } - if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) - { - LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); + if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { + LOG_WARNING( + "memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", + address, + size, + count); arm7_9->write_xpsr_im8(target, - buf_get_u32(arm->cpsr->value, 0, 8) - & ~0x20, 0, 0); + buf_get_u32(arm->cpsr->value, 0, 8) + & ~0x20, 0, 0); return ERROR_TARGET_DATA_ABORT; } @@ -2640,25 +2472,30 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, static int dcc_count; static const uint8_t *dcc_buffer; -static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) +static int arm7_9_dcc_completion(struct target *target, + uint32_t exit_point, + int timeout_ms, + void *arch_info) { int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) + retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500); + if (retval != ERROR_OK) return retval; int little = target->endianness == TARGET_LITTLE_ENDIAN; int count = dcc_count; const uint8_t *buffer = dcc_buffer; - if (count > 2) - { + if (count > 2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the * core function repeated. */ - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], + fast_target_buffer_get_u32(buffer, little)); buffer += 4; - struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + struct embeddedice_reg *ice_reg = + arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; struct jtag_tap *tap; tap = ice_reg->jtag_info->tap; @@ -2666,26 +2503,24 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2); buffer += (count-2)*4; - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - } else - { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], + fast_target_buffer_get_u32(buffer, little)); + } else { int i; - for (i = 0; i < count; i++) - { - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); + for (i = 0; i < count; i++) { + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], + fast_target_buffer_get_u32(buffer, little)); buffer += 4; } } - if ((retval = target_halt(target))!= ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } return target_wait_state(target, TARGET_HALTED, 500); } -static const uint32_t dcc_code[] = -{ +static const uint32_t dcc_code[] = { /* r0 == input, points to memory buffer * r1 == scratch */ @@ -2703,7 +2538,10 @@ static const uint32_t dcc_code[] = 0xeafffff9 /* b w */ }; -int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer) +int arm7_9_bulk_write_memory(struct target *target, + uint32_t address, + uint32_t count, + const uint8_t *buffer) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2713,28 +2551,24 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c return target_write_memory(target, address, 4, count, buffer); /* regrab previously allocated working_area, or allocate a new one */ - if (!arm7_9->dcc_working_area) - { + if (!arm7_9->dcc_working_area) { uint8_t dcc_code_buf[6 * 4]; /* make sure we have a working area */ - if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) - { + if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); return target_write_memory(target, address, 4, count, buffer); } /* copy target instructions to target endianness */ for (i = 0; i < 6; i++) - { target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); - } /* write DCC code to working area */ - if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK) - { + retval = target_write_memory(target, + arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf); + if (retval != ERROR_OK) return retval; - } } struct arm_algorithm armv4_5_info; @@ -2752,15 +2586,16 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c dcc_buffer = buffer; retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, arm7_9->dcc_working_area->address, - arm7_9->dcc_working_area->address + 6*4, + arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); - if (endaddress != (address + count*4)) - { - LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress); + if (endaddress != (address + count*4)) { + LOG_ERROR( + "DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", + (address + count*4), + endaddress); retval = ERROR_FAIL; } } @@ -2811,19 +2646,15 @@ int arm7_9_check_reset(struct target *target) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (get_target_reset_nag() && !arm7_9->dcc_downloads) - { - LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'."); - } + LOG_WARNING( + "NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'."); if (get_target_reset_nag() && (target->working_area_size == 0)) - { LOG_WARNING("NOTE! Severe performance degradation without working memory enabled."); - } if (get_target_reset_nag() && !arm7_9->fast_memory_access) - { - LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'."); - } + LOG_WARNING( + "NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'."); return ERROR_OK; } @@ -2833,16 +2664,17 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command) struct target *target = get_current_target(CMD_CTX); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (!is_arm7_9(arm7_9)) - { + if (!is_arm7_9(arm7_9)) { command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } if (CMD_ARGC > 0) - COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq); + COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->use_dbgrq); - command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled"); + command_print(CMD_CTX, + "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", + (arm7_9->use_dbgrq) ? "enabled" : "disabled"); return ERROR_OK; } @@ -2852,8 +2684,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) struct target *target = get_current_target(CMD_CTX); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (!is_arm7_9(arm7_9)) - { + if (!is_arm7_9(arm7_9)) { command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } @@ -2861,7 +2692,9 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) if (CMD_ARGC > 0) COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access); - command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled"); + command_print(CMD_CTX, + "fast memory access is %s", + (arm7_9->fast_memory_access) ? "enabled" : "disabled"); return ERROR_OK; } @@ -2871,8 +2704,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) struct target *target = get_current_target(CMD_CTX); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (!is_arm7_9(arm7_9)) - { + if (!is_arm7_9(arm7_9)) { command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } @@ -2880,7 +2712,9 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) if (CMD_ARGC > 0) COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads); - command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled"); + command_print(CMD_CTX, + "dcc downloads are %s", + (arm7_9->dcc_downloads) ? "enabled" : "disabled"); return ERROR_OK; } @@ -2889,15 +2723,14 @@ static int arm7_9_setup_semihosting(struct target *target, int enable) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (!is_arm7_9(arm7_9)) - { + if (!is_arm7_9(arm7_9)) { LOG_USER("current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } if (arm7_9->has_vector_catch) { struct reg *vector_catch = &arm7_9->eice_cache - ->reg_list[EICE_VEC_CATCH]; + ->reg_list[EICE_VEC_CATCH]; if (!vector_catch->valid) embeddedice_read_reg(vector_catch); @@ -2921,7 +2754,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) arm7_9->common_magic = ARM7_9_COMMON_MAGIC; - if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) + retval = arm_jtag_setup_connection(&arm7_9->jtag_info); + if (retval != ERROR_OK) return retval; /* caller must have allocated via calloc(), so everything's zeroed */ @@ -2942,7 +2776,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) return retval; return target_register_timer_callback(arm7_9_handle_target_request, - 1, 1, target); + 1, 1, target); } static const struct command_registration arm7_9_any_command_handlers[] = { diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index 536f561..6f1b51f 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -26,6 +26,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM7_9_COMMON_H #define ARM7_9_COMMON_H @@ -37,8 +38,7 @@ /** * Structure for items that are common between both ARM7 and ARM9 targets. */ -struct arm7_9_common -{ +struct arm7_9_common { struct arm arm; uint32_t common_magic; @@ -71,16 +71,26 @@ struct arm7_9_common struct working_area *dcc_working_area; - int (*examine_debug_reason)(struct target *target); /**< Function for determining why debug state was entered */ + int (*examine_debug_reason)(struct target *target); + /**< Function for determining why debug state was entered */ + + void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); + /**< Function for changing from Thumb to ARM mode */ + + void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); + /**< Function for reading the core registers */ - void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */ + void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, + void *buffer, int size); + void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); + /**< Function for reading CPSR or SPSR */ - void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */ - void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size); - void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */ + void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); + /**< Function for writing to CPSR or SPSR */ + + void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); + /**< Function for writing an immediate value to CPSR or SPSR */ - void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */ - void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */ void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]); void (*load_word_regs)(struct target *target, uint32_t mask); @@ -91,25 +101,28 @@ struct arm7_9_common void (*store_hword_reg)(struct target *target, int num); void (*store_byte_reg)(struct target *target, int num); - void (*write_pc)(struct target *target, uint32_t pc); /**< Function for writing to the program counter */ + void (*write_pc)(struct target *target, uint32_t pc); + /**< Function for writing to the program counter */ + void (*branch_resume)(struct target *target); void (*branch_resume_thumb)(struct target *target); void (*enable_single_step)(struct target *target, uint32_t next_pc); void (*disable_single_step)(struct target *target); - void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */ + void (*set_special_dbgrq)(struct target *target); + /**< Function for setting DBGRQ if the normal way won't work */ - int (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */ + int (*post_debug_entry)(struct target *target); + /**< Callback function called after entering debug mode */ - void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */ + void (*pre_restore_context)(struct target *target); + /**< Callback function called before restoring the processor context */ }; -static inline struct arm7_9_common * -target_to_arm7_9(struct target *target) +static inline struct arm7_9_common *target_to_arm7_9(struct target *target) { - return container_of(target->arch_info, struct arm7_9_common, - arm); + return container_of(target->arch_info, struct arm7_9_common, arm); } static inline bool is_arm7_9(struct arm7_9_common *arm7_9) @@ -131,13 +144,20 @@ int arm7_9_soft_reset_halt(struct target *target); int arm7_9_prepare_reset_halt(struct target *target); int arm7_9_halt(struct target *target); -int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints); -int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer); -int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer); - -int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info); +int arm7_9_resume(struct target *target, int current, uint32_t address, + int handle_breakpoints, int debug_execution); +int arm7_9_step(struct target *target, int current, uint32_t address, + int handle_breakpoints); +int arm7_9_read_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer); +int arm7_9_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); +int arm7_9_bulk_write_memory(struct target *target, uint32_t address, + uint32_t count, const uint8_t *buffer); + +int arm7_9_run_algorithm(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_prams, + struct reg_param *reg_param, uint32_t entry_point, void *arch_info); int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint); int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint); diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index d39ef3f..377c302 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -32,7 +33,6 @@ #include "register.h" #include "arm_opcodes.h" - /* * For information about ARM7TDMI, see ARM DDI 0210C (r4p1) * or ARM DDI 0029G (r3). "Debug In Depth", Appendix B, @@ -50,8 +50,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target) /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { struct scan_field fields[2]; uint8_t databus[4]; uint8_t breakpoint; @@ -64,19 +63,17 @@ static int arm7tdmi_examine_debug_reason(struct target *target) fields[1].out_value = NULL; fields[1].in_value = databus; - if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) return retval; jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } fields[0].in_value = NULL; fields[0].out_value = &breakpoint; @@ -96,9 +93,9 @@ static int arm7tdmi_examine_debug_reason(struct target *target) static const int arm7tdmi_num_bits[] = {1, 32}; -static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint) +static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint) { - uint32_t values[2]={breakpoint, flip_u32(out, 32)}; + uint32_t values[2] = {breakpoint, flip_u32(out, 32)}; jtag_add_dr_out(jtag_info->tap, 2, @@ -116,7 +113,7 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_ * * FIXME remove the unused "deprecated" parameter */ -static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info, +static inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint) { int retval; @@ -136,10 +133,9 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) int retval = ERROR_OK; struct scan_field fields[2]; - if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) return retval; @@ -159,7 +155,8 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; if (in) @@ -176,28 +173,21 @@ void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip) uint32_t readback = le_to_h_u32(tmp); if (flip) readback = flip_u32(readback, 32); - switch (size) - { + switch (size) { case 4: if (be) - { - h_u32_to_be(((uint8_t*)in), readback); - } else - { - h_u32_to_le(((uint8_t*)in), readback); - } + h_u32_to_be(((uint8_t *)in), readback); + else + h_u32_to_le(((uint8_t *)in), readback); break; case 2: if (be) - { - h_u16_to_be(((uint8_t*)in), readback & 0xffff); - } else - { - h_u16_to_le(((uint8_t*)in), readback & 0xffff); - } + h_u16_to_be(((uint8_t *)in), readback & 0xffff); + else + h_u16_to_le(((uint8_t *)in), readback & 0xffff); break; case 1: - *((uint8_t *)in)= readback & 0xff; + *((uint8_t *)in) = readback & 0xff; break; } } @@ -222,10 +212,9 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, int retval = ERROR_OK; struct scan_field fields[2]; - if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) return retval; @@ -250,19 +239,14 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { - LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); - } + LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in); else - { LOG_ERROR("BUG: called with in == NULL"); - } } #endif @@ -318,7 +302,6 @@ static void arm7tdmi_change_to_arm(struct target *target, *pc -= 0xa; } - /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? * @@ -326,7 +309,7 @@ static void arm7tdmi_change_to_arm(struct target *target, * and convert data afterwards. */ static void arm7tdmi_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]) + uint32_t mask, uint32_t *core_regs[16]) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -342,8 +325,7 @@ static void arm7tdmi_read_core_regs(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_data_in(jtag_info, core_regs[i]); @@ -351,7 +333,7 @@ static void arm7tdmi_read_core_regs(struct target *target, } static void arm7tdmi_read_core_regs_target_buffer(struct target *target, - uint32_t mask, void* buffer, int size) + uint32_t mask, void *buffer, int size) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -371,13 +353,10 @@ static void arm7tdmi_read_core_regs_target_buffer(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ - if (mask & (1 << i)) - { - switch (size) - { + if (mask & (1 << i)) { + switch (size) { case 4: arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -474,8 +453,7 @@ static void arm7tdmi_write_core_regs(struct target *target, /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); @@ -711,7 +689,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp) { struct arm7_9_common *arm7_9; - arm7_9 = calloc(1,sizeof(struct arm7_9_common)); + arm7_9 = calloc(1, sizeof(struct arm7_9_common)); arm7tdmi_init_arch_info(target, arm7_9, target->tap); arm7_9->arm.is_armv4 = true; @@ -719,8 +697,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp) } /** Holds methods for ARM7TDMI targets. */ -struct target_type arm7tdmi_target = -{ +struct target_type arm7tdmi_target = { .name = "arm7tdmi", .poll = arm7_9_poll, diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h index b6bbe59..6c65db4 100644 --- a/src/target/arm7tdmi.h +++ b/src/target/arm7tdmi.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM7TDMI_H #define ARM7TDMI_H diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 055e46f..0e3c326 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -18,6 +18,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -28,7 +29,6 @@ #include "register.h" #include "arm_opcodes.h" - /* * For information about the ARM920T, see ARM DDI 0151C especially * Chapter 9 about debug support, which shows how to manipulate each @@ -68,20 +68,20 @@ #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z)) /* Registers supporting physical Read access (from table 9-9) */ -#define CP15PHYS_CACHETYPE ARM920T_CP15_PHYS_ADDR(0, 0x0, 1) -#define CP15PHYS_ICACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xd, 1) -#define CP15PHYS_DCACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xe, 1) +#define CP15PHYS_CACHETYPE ARM920T_CP15_PHYS_ADDR(0, 0x0, 1) +#define CP15PHYS_ICACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xd, 1) +#define CP15PHYS_DCACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xe, 1) /* NOTE: several more registers support only physical read access */ /* Registers supporting physical Read/Write access (from table 9-9) */ -#define CP15PHYS_CTRL ARM920T_CP15_PHYS_ADDR(0, 0x1, 0) -#define CP15PHYS_PID ARM920T_CP15_PHYS_ADDR(0, 0xd, 0) -#define CP15PHYS_TESTSTATE ARM920T_CP15_PHYS_ADDR(0, 0xf, 0) -#define CP15PHYS_ICACHE ARM920T_CP15_PHYS_ADDR(1, 0x1, 1) -#define CP15PHYS_DCACHE ARM920T_CP15_PHYS_ADDR(1, 0x2, 1) +#define CP15PHYS_CTRL ARM920T_CP15_PHYS_ADDR(0, 0x1, 0) +#define CP15PHYS_PID ARM920T_CP15_PHYS_ADDR(0, 0xd, 0) +#define CP15PHYS_TESTSTATE ARM920T_CP15_PHYS_ADDR(0, 0xf, 0) +#define CP15PHYS_ICACHE ARM920T_CP15_PHYS_ADDR(1, 0x1, 1) +#define CP15PHYS_DCACHE ARM920T_CP15_PHYS_ADDR(1, 0x2, 1) static int arm920t_read_cp15_physical(struct target *target, - int reg_addr, uint32_t *value) + int reg_addr, uint32_t *value) { struct arm920t_common *arm920t = target_to_arm920(target); struct arm_jtag *jtag_info; @@ -133,7 +133,7 @@ static int arm920t_read_cp15_physical(struct target *target, } static int arm920t_write_cp15_physical(struct target *target, - int reg_addr, uint32_t value) + int reg_addr, uint32_t value) { struct arm920t_common *arm920t = target_to_arm920(target); struct arm_jtag *jtag_info; @@ -188,7 +188,7 @@ static int arm920t_write_cp15_physical(struct target *target, * executed using scan chain 15 interpreted mode. */ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, - uint32_t arm_opcode) + uint32_t arm_opcode) { int retval; struct arm920t_common *arm920t = target_to_arm920(target); @@ -234,8 +234,8 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, if (retval != ERROR_OK) return retval; - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("failed executing JTAG queue"); return retval; } @@ -244,10 +244,10 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, } static int arm920t_read_cp15_interpreted(struct target *target, - uint32_t cp15_opcode, uint32_t address, uint32_t *value) + uint32_t cp15_opcode, uint32_t address, uint32_t *value) { struct arm *arm = target_to_arm(target); - uint32_t* regs_p[1]; + uint32_t *regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; struct reg *r = arm->core_cache->reg_list; @@ -277,11 +277,10 @@ static int arm920t_read_cp15_interpreted(struct target *target, #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", - cp15_opcode, address, *value); + cp15_opcode, address, *value); #endif - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -294,7 +293,7 @@ static int arm920t_read_cp15_interpreted(struct target *target, static int arm920t_write_cp15_interpreted(struct target *target, - uint32_t cp15_opcode, uint32_t value, uint32_t address) + uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; struct arm *arm = target_to_arm(target); @@ -322,11 +321,10 @@ int arm920t_write_cp15_interpreted(struct target *target, #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", - cp15_opcode, value, address); + cp15_opcode, value, address); #endif - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -337,24 +335,25 @@ int arm920t_write_cp15_interpreted(struct target *target, return ERROR_OK; } -// EXPORTED to FA256 +/* EXPORTED to FA256 */ int arm920t_get_ttb(struct target *target, uint32_t *result) { int retval; uint32_t ttb = 0x0; - if ((retval = arm920t_read_cp15_interpreted(target, + retval = arm920t_read_cp15_interpreted(target, /* FIXME use opcode macro */ - 0xeebf0f51, 0x0, &ttb)) != ERROR_OK) + 0xeebf0f51, 0x0, &ttb); + if (retval != ERROR_OK) return retval; *result = ttb; return ERROR_OK; } -// EXPORTED to FA256 +/* EXPORTED to FA256 */ int arm920t_disable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) + int d_u_cache, int i_cache) { uint32_t cp15_control; int retval; @@ -380,9 +379,9 @@ int arm920t_disable_mmu_caches(struct target *target, int mmu, return retval; } -// EXPORTED to FA256 +/* EXPORTED to FA256 */ int arm920t_enable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) + int d_u_cache, int i_cache) { uint32_t cp15_control; int retval; @@ -408,7 +407,7 @@ int arm920t_enable_mmu_caches(struct target *target, int mmu, return retval; } -// EXPORTED to FA256 +/* EXPORTED to FA256 */ int arm920t_post_debug_entry(struct target *target) { uint32_t cp15c15; @@ -425,8 +424,7 @@ int arm920t_post_debug_entry(struct target *target) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg); - if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1) - { + if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1) { uint32_t cache_type_reg; /* identify caches */ retval = arm920t_read_cp15_physical(target, @@ -437,18 +435,18 @@ int arm920t_post_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; armv4_5_identify_cache(cache_type_reg, - &arm920t->armv4_5_mmu.armv4_5_cache); + &arm920t->armv4_5_mmu.armv4_5_cache); } arm920t->armv4_5_mmu.mmu_enabled = - (arm920t->cp15_control_reg & 0x1U) ? 1 : 0; + (arm920t->cp15_control_reg & 0x1U) ? 1 : 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = - (arm920t->cp15_control_reg & 0x4U) ? 1 : 0; + (arm920t->cp15_control_reg & 0x4U) ? 1 : 0; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = - (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0; + (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0; - /* save i/d fault status and address register */ - /* FIXME use opcode macros */ + /* save i/d fault status and address register + * FIXME use opcode macros */ retval = arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr); if (retval != ERROR_OK) return retval; @@ -466,8 +464,7 @@ int arm920t_post_debug_entry(struct target *target) ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32, arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far); - if (arm920t->preserve_cache) - { + if (arm920t->preserve_cache) { /* read-modify-write CP15 test state register * to disable I/D-cache linefills */ retval = arm920t_read_cp15_physical(target, @@ -486,7 +483,7 @@ int arm920t_post_debug_entry(struct target *target) return ERROR_OK; } -// EXPORTED to FA256 +/* EXPORTED to FA256 */ void arm920t_pre_restore_context(struct target *target) { uint32_t cp15c15; @@ -500,21 +497,20 @@ void arm920t_pre_restore_context(struct target *target) /* read-modify-write CP15 test state register * to reenable I/D-cache linefills */ - if (arm920t->preserve_cache) - { + if (arm920t->preserve_cache) { arm920t_read_cp15_physical(target, - CP15PHYS_TESTSTATE, &cp15c15); + CP15PHYS_TESTSTATE, &cp15c15); jtag_execute_queue(); cp15c15 &= ~0x600U; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); } } static const char arm920_not[] = "target is not an ARM920"; static int arm920t_verify_pointer(struct command_context *cmd_ctx, - struct arm920t_common *arm920t) + struct arm920t_common *arm920t) { if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { command_print(cmd_ctx, arm920_not); @@ -527,24 +523,22 @@ static int arm920t_verify_pointer(struct command_context *cmd_ctx, /** Logs summary of ARM920 state for a halted target. */ int arm920t_arch_state(struct target *target) { - static const char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; struct arm920t_common *arm920t = target_to_arm920(target); - if (arm920t->common_magic != ARM920T_COMMON_MAGIC) - { + if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { LOG_ERROR("BUG: %s", arm920_not); return ERROR_TARGET_INVALID; } arm_arch_state(target); LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", - state[arm920t->armv4_5_mmu.mmu_enabled], - state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], - state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); + state[arm920t->armv4_5_mmu.mmu_enabled], + state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], + state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); return ERROR_OK; } @@ -561,7 +555,7 @@ static int arm920_mmu(struct target *target, int *enabled) } static int arm920_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys) + uint32_t virt, uint32_t *phys) { uint32_t cb; struct arm920t_common *arm920t = target_to_arm920(target); @@ -577,7 +571,7 @@ static int arm920_virt2phys(struct target *target, /** Reads a buffer, in the specified word size, with current MMU settings. */ int arm920t_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -588,32 +582,31 @@ int arm920t_read_memory(struct target *target, uint32_t address, static int arm920t_read_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { struct arm920t_common *arm920t = target_to_arm920(target); return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, - address, size, count, buffer); + address, size, count, buffer); } static int arm920t_write_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { struct arm920t_common *arm920t = target_to_arm920(target); return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, - address, size, count, buffer); + address, size, count, buffer); } - /** Writes a buffer, in the specified word size, with current MMU settings. */ int arm920t_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; - const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */ + const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */ struct arm920t_common *arm920t = target_to_arm920(target); /* FIX!!!! this should be cleaned up and made much more general. The @@ -624,8 +617,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, * specifically and not the generic memory write fn's. See XScale code. */ if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && - ((size==2) || (size==4))) - { + ((size == 2) || (size == 4))) { /* special case the handling of single word writes to * bypass MMU, to allow implementation of breakpoints * in memory marked read only @@ -642,26 +634,23 @@ int arm920t_write_memory(struct target *target, uint32_t address, if (retval != ERROR_OK) return retval; - if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { - if (cb & 0x1) - { + if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { + if (cb & 0x1) { LOG_DEBUG("D-Cache buffered, " - "drain write buffer"); + "drain write buffer"); /* * Buffered ? * Drain write buffer - MCR p15,0,Rd,c7,c10,4 */ retval = arm920t_write_cp15_interpreted(target, - ARMV4_5_MCR(15, 0, 0, 7, 10, 4), - 0x0, 0); + ARMV4_5_MCR(15, 0, 0, 7, 10, 4), + 0x0, 0); if (retval != ERROR_OK) return retval; } - if (cb == 0x3) - { + if (cb == 0x3) { /* * Write back memory ? -> clean cache * @@ -672,7 +661,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, uint8_t data[32]; LOG_DEBUG("D-Cache in 'write back' mode, " - "flush cache line"); + "flush cache line"); retval = target_read_memory(target, address & cache_mask, 1, @@ -689,8 +678,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, } /* Cached ? */ - if (cb & 0x2) - { + if (cb & 0x2) { /* * Cached ? -> Invalidate data cache using MVA * @@ -700,8 +688,8 @@ int arm920t_write_memory(struct target *target, uint32_t address, "invalidate cache line"); retval = arm920t_write_cp15_interpreted(target, - ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0, - address & cache_mask); + ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0, + address & cache_mask); if (retval != ERROR_OK) return retval; } @@ -715,10 +703,9 @@ int arm920t_write_memory(struct target *target, uint32_t address, count, buffer); if (retval != ERROR_OK) return retval; - } else - { - if ((retval = arm7_9_write_memory(target, address, - size, count, buffer)) != ERROR_OK) + } else { + retval = arm7_9_write_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) return retval; } @@ -726,10 +713,8 @@ int arm920t_write_memory(struct target *target, uint32_t address, * the DCache is forced to write-through, * so we don't have to clean it here */ - if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) - { - if (count <= 1) - { + if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) { + if (count <= 1) { /* invalidate ICache single entry with MVA * mcr 15, 0, r0, cr7, cr5, {1} */ @@ -740,9 +725,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, 0x0, address & cache_mask); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* invalidate ICache * mcr 15, 0, r0, cr7, cr5, {0} */ @@ -757,7 +740,7 @@ int arm920t_write_memory(struct target *target, uint32_t address, return ERROR_OK; } -// EXPORTED to FA256 +/* EXPORTED to FA256 */ int arm920t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; @@ -766,38 +749,27 @@ int arm920t_soft_reset_halt(struct target *target) struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } long long then = timeval_ms(); int timeout; - while (!(timeout = ((timeval_ms()-then) > 1000))) - { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) - == 0) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } } else - { break; - } - if (debug_level >= 3) - { + if (debug_level >= 3) { /* do not eat all CPU, time out after 1 se*/ alive_sleep(100); } else - { keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -837,7 +809,7 @@ static int arm920t_mcr(struct target *target, int cpnum, uint32_t value); static int arm920t_init_arch_info(struct target *target, - struct arm920t_common *arm920t, struct jtag_tap *tap) + struct arm920t_common *arm920t, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; @@ -877,7 +849,7 @@ static int arm920t_target_create(struct target *target, Jim_Interp *interp) { struct arm920t_common *arm920t; - arm920t = calloc(1,sizeof(struct arm920t_common)); + arm920t = calloc(1, sizeof(struct arm920t_common)); return arm920t_init_arch_info(target, arm920t, target->tap); } @@ -903,12 +875,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) return retval; if (CMD_ARGC != 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - if ((output = fopen(CMD_ARGV[0], "w")) == NULL) - { + output = fopen(CMD_ARGV[0], "w"); + if (output == NULL) { LOG_DEBUG("error opening cache content file"); return ERROR_OK; } @@ -918,13 +888,12 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* disable MMU and Caches */ arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } cp15_ctrl_saved = cp15_ctrl; cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED - | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); + | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl); /* read CP15 test state register */ @@ -936,9 +905,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ for (segment = 0; - segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; - segment++) - { + segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; + segment++) { fprintf(output, "\nsegment: %i\n----------", segment); /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */ @@ -948,23 +916,22 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* D CAM Read, loads current victim into C15.C.D.Ind */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0)); + ARMV4_5_MCR(15, 2, 0, 15, 6, 2), ARMV4_5_LDR(1, 0)); /* read current victim */ arm920t_read_cp15_physical(target, - CP15PHYS_DCACHE_IDX, &C15_C_D_Ind); + CP15PHYS_DCACHE_IDX, &C15_C_D_Ind); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); - for (index_t = 0; index_t < 64; index_t++) - { + for (index_t = 0; index_t < 64; index_t++) { /* Ra: * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ @@ -974,33 +941,32 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write DCache victim */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 9, 1, 0), ARMV4_5_LDR(1, 0)); /* Read D RAM */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,2,0,15,10,2), + ARMV4_5_MCR(15, 2, 0, 15, 10, 2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); /* Read D CAM */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,2,0,15,6,2), + ARMV4_5_MCR(15, 2, 0, 15, 6, 2), ARMV4_5_LDR(9, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* read D RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } /* mask LFSR[6] */ regs[9] &= 0xfffffffe; @@ -1009,10 +975,9 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) segment, index_t, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); - for (i = 1; i < 9; i++) - { - fprintf(output, "%i: 0x%8.8" PRIx32 "\n", - i-1, regs[i]); + for (i = 1; i < 9; i++) { + fprintf(output, "%i: 0x%8.8" PRIx32 "\n", + i-1, regs[i]); } } @@ -1024,16 +989,16 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write DCache victim */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 9, 1, 0), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); } /* read ICache content */ @@ -1041,9 +1006,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ for (segment = 0; - segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; - segment++) - { + segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; + segment++) { fprintf(output, "segment: %i\n----------", segment); /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */ @@ -1053,23 +1017,22 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* I CAM Read, loads current victim into C15.C.I.Ind */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0)); + ARMV4_5_MCR(15, 2, 0, 15, 5, 2), ARMV4_5_LDR(1, 0)); /* read current victim */ arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX, - &C15_C_I_Ind); + &C15_C_I_Ind); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); - for (index_t = 0; index_t < 64; index_t++) - { + for (index_t = 0; index_t < 64; index_t++) { /* Ra: * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ @@ -1079,33 +1042,32 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write ICache victim */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 9, 1, 1), ARMV4_5_LDR(1, 0)); /* Read I RAM */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,2,0,15,9,2), + ARMV4_5_MCR(15, 2, 0, 15, 9, 2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); /* Read I CAM */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,2,0,15,5,2), + ARMV4_5_MCR(15, 2, 0, 15, 5, 2), ARMV4_5_LDR(9, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* read I RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } /* mask LFSR[6] */ regs[9] &= 0xfffffffe; @@ -1114,10 +1076,9 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) segment, index_t, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); - for (i = 1; i < 9; i++) - { - fprintf(output, "%i: 0x%8.8" PRIx32 "\n", - i-1, regs[i]); + for (i = 1; i < 9; i++) { + fprintf(output, "%i: 0x%8.8" PRIx32 "\n", + i-1, regs[i]); } } @@ -1128,28 +1089,27 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write ICache victim */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 9, 1, 1), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); } /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved); command_print(CMD_CTX, "cache content successfully output to %s", - CMD_ARGV[0]); + CMD_ARGV[0]); fclose(output); - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -1197,12 +1157,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) return retval; if (CMD_ARGC != 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - if ((output = fopen(CMD_ARGV[0], "w")) == NULL) - { + output = fopen(CMD_ARGV[0], "w"); + if (output == NULL) { LOG_DEBUG("error opening mmu content file"); return ERROR_OK; } @@ -1212,10 +1170,9 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* disable MMU and Caches */ arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } cp15_ctrl_saved = cp15_ctrl; cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); @@ -1223,10 +1180,9 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* read CP15 test state register */ arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } /* prepare reading D TLB content * */ @@ -1237,7 +1193,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* Read D TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0)); + ARMV4_5_MRC(15, 0, 0, 10, 0, 0), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; @@ -1245,14 +1201,12 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* read D TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } Dlockdown = regs[1]; - for (victim = 0; victim < 64; victim += 8) - { + for (victim = 0; victim < 64; victim += 8) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ @@ -1262,36 +1216,34 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write D TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,10,0,0), + ARMV4_5_MCR(15, 0, 0, 10, 0, 0), ARMV4_5_STR(1, 0)); /* Read D TLB CAM */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,4,0,15,6,4), + ARMV4_5_MCR(15, 4, 0, 15, 6, 4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* read D TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } for (i = 0; i < 8; i++) d_tlb[victim + i].cam = regs[i + 2]; } - for (victim = 0; victim < 64; victim++) - { + for (victim = 0; victim < 64; victim++) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ @@ -1301,31 +1253,30 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write D TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 10, 0, 0), ARMV4_5_STR(1, 0)); /* Read D TLB RAM1 */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0)); + ARMV4_5_MCR(15, 4, 0, 15, 10, 4), ARMV4_5_LDR(2, 0)); /* Read D TLB RAM2 */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0)); + ARMV4_5_MCR(15, 4, 0, 15, 2, 5), ARMV4_5_LDR(3, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* read D TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } d_tlb[victim].ram1 = regs[2]; d_tlb[victim].ram2 = regs[3]; @@ -1337,7 +1288,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* Write D TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 10, 0, 0), ARMV4_5_STR(1, 0)); /* prepare reading I TLB content * */ @@ -1348,7 +1299,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* Read I TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0)); + ARMV4_5_MRC(15, 0, 0, 10, 0, 1), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; @@ -1356,14 +1307,12 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* read I TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } Ilockdown = regs[1]; - for (victim = 0; victim < 64; victim += 8) - { + for (victim = 0; victim < 64; victim += 8) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ @@ -1373,36 +1322,34 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write I TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,10,0,1), - ARMV4_5_STR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 10, 0, 1), + ARMV4_5_STR(1, 0)); /* Read I TLB CAM */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,4,0,15,5,4), - ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); + ARMV4_5_MCR(15, 4, 0, 15, 5, 4), + ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* read I TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } for (i = 0; i < 8; i++) i_tlb[i + victim].cam = regs[i + 2]; } - for (victim = 0; victim < 64; victim++) - { + for (victim = 0; victim < 64; victim++) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ @@ -1412,31 +1359,30 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* Write I TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 10, 0, 1), ARMV4_5_STR(1, 0)); /* Read I TLB RAM1 */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0)); + ARMV4_5_MCR(15, 4, 0, 15, 9, 4), ARMV4_5_LDR(2, 0)); /* Read I TLB RAM2 */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0)); + ARMV4_5_MCR(15, 4, 0, 15, 1, 5), ARMV4_5_LDR(3, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, - CP15PHYS_TESTSTATE, cp15c15); + CP15PHYS_TESTSTATE, cp15c15); /* read I TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } i_tlb[victim].ram1 = regs[2]; i_tlb[victim].ram2 = regs[3]; @@ -1448,15 +1394,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) /* Write I TLB lockdown */ arm920t_execute_cp15(target, - ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); + ARMV4_5_MCR(15, 0, 0, 10, 0, 1), ARMV4_5_STR(1, 0)); /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved); /* output data to file */ fprintf(output, "D TLB content:\n"); - for (i = 0; i < 64; i++) - { + for (i = 0; i < 64; i++) { fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, @@ -1464,8 +1409,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) } fprintf(output, "\n\nI TLB content:\n"); - for (i = 0; i < 64; i++) - { + for (i = 0; i < 64; i++) { fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, @@ -1473,12 +1417,11 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) } command_print(CMD_CTX, "mmu content successfully output to %s", - CMD_ARGV[0]); + CMD_ARGV[0]); fclose(output); - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } @@ -1513,8 +1456,7 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for " "\"%s\" command", CMD_NAME); return ERROR_OK; @@ -1523,44 +1465,37 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) /* one argument, read a register. * two arguments, write it. */ - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { int address; COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address); - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm920t_read_cp15_physical(target, - address, &value)) != ERROR_OK) - { + retval = arm920t_read_cp15_physical(target, address, &value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } command_print(CMD_CTX, "%i: %8.8" PRIx32, - address, value); - } - else if (CMD_ARGC == 2) - { + address, value); + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); retval = arm920t_write_cp15_physical(target, address, value); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %i", address); /* REVISIT why lie? "return retval"? */ return ERROR_OK; } command_print(CMD_CTX, "%i: %8.8" PRIx32, - address, value); + address, value); } } @@ -1578,28 +1513,24 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for " - "\"%s\" command", CMD_NAME); + "\"%s\" command", CMD_NAME); return ERROR_OK; } /* one argument, read a register. * two arguments, write it. */ - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { uint32_t opcode; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't execute %8.8" PRIx32, opcode); @@ -1608,16 +1539,13 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) } command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32, - opcode, value); - } - else if (CMD_ARGC == 2) - { + opcode, value); + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); retval = arm920t_write_cp15_interpreted(target, opcode, value, 0); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't execute %8.8" PRIx32, opcode); @@ -1625,31 +1553,25 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) return ERROR_OK; } command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32, - opcode, value); - } - else if (CMD_ARGC == 3) - { + opcode, value); + } else if (CMD_ARGC == 3) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); uint32_t address; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address); retval = arm920t_write_cp15_interpreted(target, opcode, value, address); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't execute %8.8" PRIx32, opcode); /* REVISIT why lie? "return retval"? */ return ERROR_OK; } command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 - " %8.8" PRIx32, opcode, value, address); + " %8.8" PRIx32, opcode, value, address); } - } - else - { - return ERROR_COMMAND_SYNTAX_ERROR; - } + } else + return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_OK; } @@ -1665,42 +1587,40 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command) return retval; return armv4_5_handle_cache_info_command(CMD_CTX, - &arm920t->armv4_5_mmu.armv4_5_cache); + &arm920t->armv4_5_mmu.armv4_5_cache); } static int arm920t_mrc(struct target *target, int cpnum, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, - uint32_t *value) + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { - if (cpnum!=15) - { + if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } /* read "to" r0 */ return arm920t_read_cp15_interpreted(target, - ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), - 0, value); + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } static int arm920t_mcr(struct target *target, int cpnum, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, - uint32_t value) + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { - if (cpnum!=15) - { + if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } /* write "from" r0 */ return arm920t_write_cp15_interpreted(target, - ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), - 0, value); + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } static const struct command_registration arm920t_exec_command_handlers[] = { @@ -1758,8 +1678,7 @@ const struct command_registration arm920t_command_handlers[] = { }; /** Holds methods for ARM920 targets. */ -struct target_type arm920t_target = -{ +struct target_type arm920t_target = { .name = "arm920t", .poll = arm7_9_poll, diff --git a/src/target/arm920t.h b/src/target/arm920t.h index 0cefd1e..25d5970 100644 --- a/src/target/arm920t.h +++ b/src/target/arm920t.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM920T_H #define ARM920T_H @@ -25,8 +26,7 @@ #define ARM920T_COMMON_MAGIC 0xa920a920 -struct arm920t_common -{ +struct arm920t_common { struct arm7_9_common arm7_9_common; uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; @@ -38,21 +38,17 @@ struct arm920t_common int preserve_cache; }; -static inline struct arm920t_common * -target_to_arm920(struct target *target) +static inline struct arm920t_common *target_to_arm920(struct target *target) { - return container_of(target->arch_info, struct arm920t_common, - arm7_9_common.arm); + return container_of(target->arch_info, struct arm920t_common, arm7_9_common.arm); } -struct arm920t_cache_line -{ +struct arm920t_cache_line { uint32_t cam; uint32_t data[8]; }; -struct arm920t_tlb_entry -{ +struct arm920t_tlb_entry { uint32_t cam; uint32_t ram1; uint32_t ram2; diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index aaf4021..6a076c1 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -63,10 +64,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2 buf_set_u32(address_buf, 0, 14, address); - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -91,8 +91,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2 long long then = timeval_ms(); - for (;;) - { + for (;;) { /* rescan with NOP, to wait for the access to complete */ access_t = 0; nr_w_buf = 0; @@ -100,19 +99,15 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (buf_get_u32(&access_t, 0, 1) == 1) - { break; - } /* 10ms timeout */ - if ((timeval_ms()-then)>10) - { + if ((timeval_ms()-then) > 10) { LOG_ERROR("cp15 read operation timed out"); return ERROR_FAIL; } @@ -155,10 +150,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -183,25 +177,20 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op long long then = timeval_ms(); - for (;;) - { + for (;;) { /* rescan with NOP, to wait for the access to complete */ access_t = 0; nr_w_buf = 0; jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (buf_get_u32(&access_t, 0, 1) == 1) - { break; - } /* 10ms timeout */ - if ((timeval_ms()-then)>10) - { + if ((timeval_ms()-then) > 10) { LOG_ERROR("cp15 write operation timed out"); return ERROR_FAIL; } @@ -236,14 +225,14 @@ static int arm926ejs_examine_debug_reason(struct target *target) int retval; embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; /* Method-Of-Entry (MOE) field */ debug_reason = buf_get_u32(dbg_stat->value, 6, 4); - switch (debug_reason) - { + switch (debug_reason) { case 0: LOG_DEBUG("no *NEW* debug entry (?missed one?)"); /* ... since last restart or debug reset ... */ @@ -337,7 +326,8 @@ static int arm926ejs_get_ttb(struct target *target, uint32_t *result) int retval; uint32_t ttb = 0x0; - if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK) + retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb); + if (retval != ERROR_OK) return retval; *result = ttb; @@ -360,8 +350,7 @@ static int arm926ejs_disable_mmu_caches(struct target *target, int mmu, if (retval != ERROR_OK) return retval; - if (mmu) - { + if (mmu) { /* invalidate TLB */ retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); if (retval != ERROR_OK) @@ -370,8 +359,7 @@ static int arm926ejs_disable_mmu_caches(struct target *target, int mmu, cp15_control &= ~0x1U; } - if (d_u_cache) - { + if (d_u_cache) { uint32_t debug_override; /* read-modify-write CP15 debug override register * to enable "test and clean all" */ @@ -398,8 +386,7 @@ static int arm926ejs_disable_mmu_caches(struct target *target, int mmu, cp15_control &= ~0x4U; } - if (i_cache) - { + if (i_cache) { /* invalidate ICache */ retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); if (retval != ERROR_OK) @@ -454,8 +441,7 @@ static int arm926ejs_post_debug_entry(struct target *target) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg); - if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) - { + if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) { uint32_t cache_type_reg; /* identify caches */ retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); @@ -530,15 +516,13 @@ static int arm926ejs_verify_pointer(struct command_context *cmd_ctx, /** Logs summary of ARM926 state for a halted target. */ int arm926ejs_arch_state(struct target *target) { - static const char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; struct arm926ejs_common *arm926ejs = target_to_arm926(target); - if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) - { + if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) { LOG_ERROR("BUG: %s", arm926_not); return ERROR_TARGET_INVALID; } @@ -560,37 +544,27 @@ int arm926ejs_soft_reset_halt(struct target *target) struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } long long then = timeval_ms(); int timeout; - while (!(timeout = ((timeval_ms()-then) > 1000))) - { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } - } else - { + } else break; - } - if (debug_level >= 1) - { + if (debug_level >= 1) { /* do not eat all CPU, time out after 1 se*/ alive_sleep(100); } else - { keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -636,13 +610,11 @@ int arm926ejs_write_memory(struct target *target, uint32_t address, * Also it should be moved to the callbacks that handle breakpoints * specifically and not the generic memory write fn's. See XScale code. **/ - if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4))) - { + if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size == 2) || (size == 4))) { /* special case the handling of single word writes to bypass MMU * to allow implementation of breakpoints in memory marked read only * by MMU */ - if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { + if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { /* flush and invalidate data cache * * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address @@ -662,24 +634,20 @@ int arm926ejs_write_memory(struct target *target, uint32_t address, retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer); if (retval != ERROR_OK) return retval; - } else - { - if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) + } else { + retval = arm7_9_write_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) return retval; } /* If ICache is enabled, we have to invalidate affected ICache lines * the DCache is forced to write-through, so we don't have to clean it here */ - if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) - { - if (count <= 1) - { + if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) { + if (count <= 1) { /* invalidate ICache single entry with MVA */ arm926ejs->write_cp15(target, 0, 1, 7, 5, address); - } - else - { + } else { /* invalidate ICache */ arm926ejs->write_cp15(target, 0, 0, 7, 5, address); } @@ -748,7 +716,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm static int arm926ejs_target_create(struct target *target, Jim_Interp *interp) { - struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common)); + struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); /* ARM9EJ-S core always reports 0x1 in Capture-IR */ target->tap->ir_capture_mask = 0x0f; @@ -787,8 +755,7 @@ static int arm926ejs_mmu(struct target *target, int *enabled) { struct arm926ejs_common *arm926ejs = target_to_arm926(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_INVALID; } @@ -822,8 +789,7 @@ const struct command_registration arm926ejs_command_handlers[] = { }; /** Holds methods for ARM926 targets. */ -struct target_type arm926ejs_target = -{ +struct target_type arm926ejs_target = { .name = "arm926ejs", .poll = arm7_9_poll, diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h index e2a53a6..d3a1cb6 100644 --- a/src/target/arm926ejs.h +++ b/src/target/arm926ejs.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM926EJS_H #define ARM926EJS_H @@ -25,27 +26,25 @@ #define ARM926EJS_COMMON_MAGIC 0xa926a926 -struct arm926ejs_common -{ +struct arm926ejs_common { struct arm7_9_common arm7_9_common; uint32_t common_magic; struct armv4_5_mmu_common armv4_5_mmu; - int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value); - int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value); + int (*read_cp15)(struct target *target, uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t *value); + int (*write_cp15)(struct target *target, uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t value); uint32_t cp15_control_reg; uint32_t d_fsr; uint32_t i_fsr; uint32_t d_far; }; -static inline struct arm926ejs_common * -target_to_arm926(struct target *target) +static inline struct arm926ejs_common *target_to_arm926(struct target *target) { - return container_of(target->arch_info, struct arm926ejs_common, - arm7_9_common.arm); + return container_of(target->arch_info, struct arm926ejs_common, arm7_9_common.arm); } - int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, struct jtag_tap *tap); int arm926ejs_arch_state(struct target *target); diff --git a/src/target/arm946e.c b/src/target/arm946e.c index 11e79c9..4739237 100644 --- a/src/target/arm946e.c +++ b/src/target/arm946e.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -39,8 +40,8 @@ #define NB_CACHE_WAYS 4 -static uint32_t dc = 0x0; -static uint32_t ic = 0x0; +static uint32_t dc; +static uint32_t ic; /** * flag to give info about cache manipulation during debug : @@ -55,8 +56,9 @@ int arm946e_post_debug_entry(struct target *target); void arm946e_pre_restore_context(struct target *target); static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value); - -int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e, struct jtag_tap *tap) +int arm946e_init_arch_info(struct target *target, + struct arm946e_common *arm946e, + struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm946e->arm7_9_common; @@ -84,14 +86,14 @@ int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e arm946e_preserve_cache = 0; /* override hw single-step capability from ARM9TDMI */ - //arm7_9->has_single_step = 1; + /* arm7_9->has_single_step = 1; */ return ERROR_OK; } static int arm946e_target_create(struct target *target, Jim_Interp *interp) { - struct arm946e_common *arm946e = calloc(1,sizeof(struct arm946e_common)); + struct arm946e_common *arm946e = calloc(1, sizeof(struct arm946e_common)); arm946e_init_arch_info(target, arm946e, target->tap); @@ -99,7 +101,7 @@ static int arm946e_target_create(struct target *target, Jim_Interp *interp) } static int arm946e_verify_pointer(struct command_context *cmd_ctx, - struct arm946e_common *arm946e) + struct arm946e_common *arm946e) { if (arm946e->common_magic != ARM946E_COMMON_MAGIC) { command_print(cmd_ctx, "target is not an ARM946"); @@ -123,10 +125,9 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -157,10 +158,9 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value); #endif - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -177,10 +177,9 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value) buf_set_u32(value_buf, 0, 32, value); - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -203,10 +202,9 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value) LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); #endif - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -214,21 +212,21 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value) uint32_t arm946e_invalidate_whole_dcache(struct target *target) { - uint32_t csize = 0; - uint32_t shift = 0; - uint32_t cp15_idx, seg, dtag; - int nb_idx, idx = 0; - int retval; + uint32_t csize = 0; + uint32_t shift = 0; + uint32_t cp15_idx, seg, dtag; + int nb_idx, idx = 0; + int retval; - /* Get cache type */ - arm946e_read_cp15(target, 0x01, (uint32_t *) &csize); + /* Get cache type */ + arm946e_read_cp15(target, 0x01, (uint32_t *) &csize); - csize = (csize >> 18) & 0x0F; + csize = (csize >> 18) & 0x0F; if (csize == 0) shift = 0; else - shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */ + shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */ /* Cache size, given in bytes */ csize = 1 << (12 + shift); @@ -236,16 +234,13 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target) nb_idx = (csize / 32); /* gives nb of lines (indexes) in the cache */ /* Loop for all segmentde (i.e. ways) */ - for( seg=0; seg < NB_CACHE_WAYS; seg++) - { + for (seg = 0; seg < NB_CACHE_WAYS; seg++) { /* Loop for all indexes */ - for(idx=0; idx < nb_idx; idx++) - { + for (idx = 0; idx < nb_idx; idx++) { /* Form and write cp15 index (segment + line idx) */ cp15_idx = seg << 30 | idx << 5; retval = arm946e_write_cp15(target, 0x3a, cp15_idx); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR writing index"); return retval; } @@ -254,21 +249,19 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target) arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag); /* Check cache line VALID bit */ - if ( !(dtag >> 4 & 0x1) ) + if (!(dtag >> 4 & 0x1)) continue; /* Clean data cache line */ retval = arm946e_write_cp15(target, 0x35, 0x1); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR cleaning cache line"); return retval; } /* Flush data cache line */ retval = arm946e_write_cp15(target, 0x1a, 0x1); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR flushing cache line"); return retval; } @@ -289,8 +282,7 @@ uint32_t arm946e_invalidate_whole_icache(struct target *target) * mcr 15, 0, r0, cr7, cr5, {0} */ retval = arm946e_write_cp15(target, 0x0f, 0x1); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR flushing I$"); return retval; } @@ -309,10 +301,8 @@ int arm946e_post_debug_entry(struct target *target) dc = (ctr_reg >> 2) & 0x01; ic = (ctr_reg >> 12) & 0x01; - if (arm946e_preserve_cache) - { - if (dc == 1) - { + if (arm946e_preserve_cache) { + if (dc == 1) { /* Clean and flush D$ */ arm946e_invalidate_whole_dcache(target); @@ -320,8 +310,7 @@ int arm946e_post_debug_entry(struct target *target) ctr_reg &= ~(1 << 2); } - if (ic == 1) - { + if (ic == 1) { /* Flush I$ */ arm946e_invalidate_whole_icache(target); @@ -331,12 +320,11 @@ int arm946e_post_debug_entry(struct target *target) /* Write the new configuration */ retval = arm946e_write_cp15(target, 0x02, ctr_reg); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR disabling cache"); return retval; } - } /* if preserve_cache */ + } /* if preserve_cache */ return ERROR_OK; } @@ -346,8 +334,7 @@ void arm946e_pre_restore_context(struct target *target) uint32_t ctr_reg = 0x0; uint32_t retval; - if (arm946e_preserve_cache) - { + if (arm946e_preserve_cache) { /* Get the contents of the CTR reg */ arm946e_read_cp15(target, 0x02, (uint32_t *) &ctr_reg); @@ -355,14 +342,12 @@ void arm946e_pre_restore_context(struct target *target) * Read-modify-write CP15 test state register * to reenable I/D-cache linefills */ - if (dc == 1) - { + if (dc == 1) { /* Enable D$ */ ctr_reg |= 1 << 2; } - if (ic == 1) - { + if (ic == 1) { /* Enable I$ */ ctr_reg |= 1 << 12; } @@ -370,14 +355,12 @@ void arm946e_pre_restore_context(struct target *target) /* Write the new configuration */ retval = arm946e_write_cp15(target, 0x02, ctr_reg); if (retval != ERROR_OK) - { LOG_DEBUG("ERROR enabling cache"); - } - } /* if preserve_cache */ + } /* if preserve_cache */ } uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address, - uint32_t size, uint32_t count) + uint32_t size, uint32_t count) { uint32_t csize = 0x0; uint32_t shift = 0; @@ -386,8 +369,7 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address, uint32_t i = 0; int retval; - for(i = 0; i < count*size; i++) - { + for (i = 0; i < count*size; i++) { cur_addr = address + i; /* Get cache type */ @@ -399,14 +381,13 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address, if (csize == 0) shift = 0; else - shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */ + shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */ csize = 1 << (12 + shift); set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */ - for (way = 0; way < NB_CACHE_WAYS; way++) - { + for (way = 0; way < NB_CACHE_WAYS; way++) { /** * Find if the affected address is kept in the cache. * Because JTAG Scan Chain 15 offers limited approach, @@ -417,8 +398,7 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address, /* Form and write cp15 index (segment + line idx) */ cp15_idx = way << 30 | set << 5; retval = arm946e_write_cp15(target, 0x3a, cp15_idx); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR writing index"); return retval; } @@ -427,57 +407,51 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address, arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag); /* Check cache line VALID bit */ - if ( !(dtag >> 4 & 0x1) ) + if (!(dtag >> 4 & 0x1)) continue; /* If line is valid and corresponds to affected address - invalidate it */ - if (dtag >> 5 == cur_addr >> 5) - { + if (dtag >> 5 == cur_addr >> 5) { /* Clean data cache line */ retval = arm946e_write_cp15(target, 0x35, 0x1); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR cleaning cache line"); return retval; } /* Flush data cache line */ retval = arm946e_write_cp15(target, 0x1c, 0x1); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR flushing cache line"); return retval; } break; } - } /* loop through all 4 ways */ - } /* loop through all addresses */ + } /* loop through all 4 ways */ + } /* loop through all addresses */ return ERROR_OK; } uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address, - uint32_t size, uint32_t count) + uint32_t size, uint32_t count) { uint32_t cur_addr = 0x0; uint32_t cp15_idx, set, way, itag; uint32_t i = 0; int retval; - for(i = 0; i < count*size; i++) - { + for (i = 0; i < count*size; i++) { cur_addr = address + i; set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */ - for (way = 0; way < NB_CACHE_WAYS; way++) - { + for (way = 0; way < NB_CACHE_WAYS; way++) { /* Form and write cp15 index (segment + line idx) */ cp15_idx = way << 30 | set << 5; retval = arm946e_write_cp15(target, 0x3a, cp15_idx); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR writing index"); return retval; } @@ -486,31 +460,29 @@ uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address, arm946e_read_cp15(target, 0x17, (uint32_t *) &itag); /* Check cache line VALID bit */ - if ( !(itag >> 4 & 0x1) ) + if (!(itag >> 4 & 0x1)) continue; /* If line is valid and corresponds to affected address - invalidate it */ - if (itag >> 5 == cur_addr >> 5) - { + if (itag >> 5 == cur_addr >> 5) { /* Flush I$ line */ retval = arm946e_write_cp15(target, 0x1d, 0x0); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_DEBUG("ERROR flushing cache line"); return retval; } break; } - } /* way loop */ - } /* addr loop */ + } /* way loop */ + } /* addr loop */ return ERROR_OK; } /** Writes a buffer, in the specified word size, with current MMU settings. */ int arm946e_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; @@ -518,18 +490,14 @@ int arm946e_write_memory(struct target *target, uint32_t address, /* Invalidate D$ if it is ON */ if (!arm946e_preserve_cache && dc == 1) - { arm946e_invalidate_dcache(target, address, size, count); - } /** * Write memory */ - if ( ( retval = arm7_9_write_memory(target, address, - size, count, buffer) ) != ERROR_OK ) - { + retval = arm7_9_write_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) return retval; - } /* * * Invalidate I$ if it is ON. @@ -554,26 +522,22 @@ int arm946e_write_memory(struct target *target, uint32_t address, * If the data is not in the cache, the controller writes to main memory only. */ if (!arm946e_preserve_cache && ic == 1) - { arm946e_invalidate_icache(target, address, size, count); - } return ERROR_OK; } int arm946e_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; LOG_DEBUG("-"); - if ( ( retval = arm7_9_read_memory(target, address, - size, count, buffer) ) != ERROR_OK ) - { + retval = arm7_9_read_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -589,49 +553,37 @@ COMMAND_HANDLER(arm946e_handle_cp15_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { uint32_t address; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm946e_read_cp15(target, address, &value)) != ERROR_OK) - { - command_print(CMD_CTX, - "couldn't access reg %" PRIi32, - address); + retval = arm946e_read_cp15(target, address, &value); + if (retval != ERROR_OK) { + command_print(CMD_CTX, "couldn't access reg %" PRIi32, address); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } - command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, - address, value); - } - else if (CMD_ARGC == 2) - { + command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value); + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); - if ((retval = arm946e_write_cp15(target, address, value)) != ERROR_OK) - { - command_print(CMD_CTX, - "couldn't access reg %" PRIi32, - address); + retval = arm946e_write_cp15(target, address, value); + if (retval != ERROR_OK) { + command_print(CMD_CTX, "couldn't access reg %" PRIi32, address); return ERROR_OK; } - command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, - address, value); + command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value); } } @@ -664,8 +616,7 @@ const struct command_registration arm946e_command_handlers[] = { }; /** Holds methods for ARM946 targets. */ -struct target_type arm946e_target = -{ +struct target_type arm946e_target = { .name = "arm946e", .poll = arm7_9_poll, @@ -683,8 +634,8 @@ struct target_type arm946e_target = .get_gdb_reg_list = arm_get_gdb_reg_list, - //.read_memory = arm7_9_read_memory, - //.write_memory = arm7_9_write_memory, + /* .read_memory = arm7_9_read_memory, */ + /* .write_memory = arm7_9_write_memory, */ .read_memory = arm946e_read_memory, .write_memory = arm946e_write_memory, @@ -697,8 +648,8 @@ struct target_type arm946e_target = .add_breakpoint = arm7_9_add_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint, - //.add_breakpoint = arm946e_add_breakpoint, - //.remove_breakpoint = arm946e_remove_breakpoint, + /* .add_breakpoint = arm946e_add_breakpoint, */ + /* .remove_breakpoint = arm946e_remove_breakpoint, */ .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, diff --git a/src/target/arm946e.h b/src/target/arm946e.h index ce0ead9..1837bad 100644 --- a/src/target/arm946e.h +++ b/src/target/arm946e.h @@ -23,31 +23,30 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM946E_H #define ARM946E_H #include "arm9tdmi.h" -#define ARM946E_COMMON_MAGIC 0x20f920f9 +#define ARM946E_COMMON_MAGIC 0x20f920f9 -struct arm946e_common -{ +struct arm946e_common { struct arm7_9_common arm7_9_common; int common_magic; uint32_t cp15_control_reg; }; -static inline struct arm946e_common * -target_to_arm946(struct target *target) +static inline struct arm946e_common *target_to_arm946(struct target *target) { return container_of(target->arch_info, struct arm946e_common, arm7_9_common.arm); } int arm946e_init_arch_info(struct target *target, - struct arm946e_common *arm946e, struct jtag_tap *tap); + struct arm946e_common *arm946e, struct jtag_tap *tap); int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value); extern const struct command_registration arm946e_command_handlers[]; -#endif /* ARM946E_H */ +#endif /* ARM946E_H */ diff --git a/src/target/arm966e.c b/src/target/arm966e.c index 439b0f6..90f241f 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -28,7 +29,6 @@ #include "target_type.h" #include "arm_opcodes.h" - #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif @@ -53,7 +53,7 @@ int arm966e_init_arch_info(struct target *target, struct arm966e_common *arm966e static int arm966e_target_create(struct target *target, Jim_Interp *interp) { - struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common)); + struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common)); return arm966e_init_arch_info(target, arm966e, target->tap); } @@ -84,10 +84,9 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -117,17 +116,16 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value); #endif return ERROR_OK; } -// EXPORTED to str9x (flash) +/* EXPORTED to str9x (flash) */ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value) { int retval = ERROR_OK; @@ -140,10 +138,9 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value) buf_set_u32(value_buf, 0, 32, value); - if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -179,42 +176,36 @@ COMMAND_HANDLER(arm966e_handle_cp15_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { uint32_t address; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm966e_read_cp15(target, address, &value)) != ERROR_OK) - { + retval = arm966e_read_cp15(target, address, &value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %" PRIi32, address); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value); - } - else if (CMD_ARGC == 2) - { + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); - if ((retval = arm966e_write_cp15(target, address, value)) != ERROR_OK) - { + retval = arm966e_write_cp15(target, address, value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %" PRIi32, address); @@ -254,8 +245,7 @@ const struct command_registration arm966e_command_handlers[] = { }; /** Holds methods for ARM966 targets. */ -struct target_type arm966e_target = -{ +struct target_type arm966e_target = { .name = "arm966e", .poll = arm7_9_poll, diff --git a/src/target/arm966e.h b/src/target/arm966e.h index cfd80d2..2371144 100644 --- a/src/target/arm966e.h +++ b/src/target/arm966e.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM966E_H #define ARM966E_H @@ -27,8 +28,7 @@ #define ARM966E_COMMON_MAGIC 0x20f920f9 -struct arm966e_common -{ +struct arm966e_common { struct arm7_9_common arm7_9_common; int common_magic; uint32_t cp15_control_reg; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index b3cd359..380dca5 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -32,7 +33,6 @@ #include "register.h" #include "arm_opcodes.h" - /* * NOTE: this holds code that's used with multiple ARM9 processors: * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores @@ -47,8 +47,7 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -enum arm9tdmi_vector_bit -{ +enum arm9tdmi_vector_bit { ARM9TDMI_RESET_VECTOR = 0x01, ARM9TDMI_UNDEF_VECTOR = 0x02, ARM9TDMI_SWI_VECTOR = 0x04, @@ -80,8 +79,7 @@ int arm9tdmi_examine_debug_reason(struct target *target) /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { struct scan_field fields[3]; uint8_t databus[4]; uint8_t instructionbus[4]; @@ -99,19 +97,17 @@ int arm9tdmi_examine_debug_reason(struct target *target) fields[2].out_value = NULL; fields[2].in_value = instructionbus; - if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) return retval; jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } fields[0].in_value = NULL; fields[0].out_value = databus; @@ -154,10 +150,9 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, if (sysspeed) buf_set_u32(&sysspeed_buf, 2, 1, 1); - if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) @@ -175,31 +170,24 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, fields[2].out_value = instr_buf; fields[2].in_value = NULL; - if (in) - { + if (in) { fields[0].in_value = (uint8_t *)in; jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); - } - else - { + } else jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE); - } jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); - } else LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out); } @@ -211,13 +199,12 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, /* just read data (instruction and data-out = don't care) */ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { - int retval = ERROR_OK;; + int retval = ERROR_OK; struct scan_field fields[3]; - if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) @@ -243,19 +230,14 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { LOG_DEBUG("in: 0x%8.8x", *in); - } else - { LOG_ERROR("BUG: called with in == NULL"); - } } #endif @@ -282,10 +264,9 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, int retval = ERROR_OK; struct scan_field fields[3]; - if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); if (retval != ERROR_OK) @@ -315,19 +296,14 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { - LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); - } + LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in); else - { LOG_ERROR("BUG: called with in == NULL"); - } } #endif @@ -376,10 +352,9 @@ static void arm9tdmi_change_to_arm(struct target *target, /* NOP fetched, BX in Execute (1) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return; - } /* fix program counter: * MOV r0, r15 was the 5th instruction (+8) @@ -389,7 +364,7 @@ static void arm9tdmi_change_to_arm(struct target *target, } void arm9tdmi_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]) + uint32_t mask, uint32_t *core_regs[16]) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -405,8 +380,7 @@ void arm9tdmi_read_core_regs(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ arm9tdmi_clock_data_in(jtag_info, core_regs[i]); @@ -414,7 +388,7 @@ void arm9tdmi_read_core_regs(struct target *target, } static void arm9tdmi_read_core_regs_target_buffer(struct target *target, - uint32_t mask, void* buffer, int size) + uint32_t mask, void *buffer, int size) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -434,12 +408,10 @@ static void arm9tdmi_read_core_regs_target_buffer(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -525,8 +497,7 @@ static void arm9tdmi_write_xpsr_im8(struct target *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* rot == 4 writes flags, which takes only one cycle */ - if (rot != 4) - { + if (rot != 4) { /* nothing fetched, MSR in EXECUTE (2) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* nothing fetched, MSR in EXECUTE (3) */ @@ -551,8 +522,7 @@ void arm9tdmi_write_core_regs(struct target *target, /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); @@ -718,30 +688,22 @@ void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9->has_single_step) - { + if (arm7_9->has_single_step) { buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - } - else - { + } else arm7_9_enable_eice_step(target, next_pc); - } } void arm9tdmi_disable_single_step(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9->has_single_step) - { + if (arm7_9->has_single_step) { buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - } - else - { + } else arm7_9_disable_eice_step(target); - } } static void arm9tdmi_build_reg_cache(struct target *target) @@ -815,7 +777,7 @@ int arm9tdmi_init_arch_info(struct target *target, static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp) { - struct arm7_9_common *arm7_9 = calloc(1,sizeof(struct arm7_9_common)); + struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common)); arm9tdmi_init_arch_info(target, arm7_9, target->tap); arm7_9->arm.is_armv4 = true; @@ -830,8 +792,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) struct reg *vector_catch; uint32_t vector_catch_value; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -853,42 +814,31 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) /* get the current setting */ vector_catch_value = buf_get_u32(vector_catch->value, 0, 8); - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { vector_catch_value = 0x0; if (strcmp(CMD_ARGV[0], "all") == 0) - { vector_catch_value = 0xdf; - } - else if (strcmp(CMD_ARGV[0], "none") == 0) - { + else if (strcmp(CMD_ARGV[0], "none") == 0) { /* do nothing */ - } - else - { - for (unsigned i = 0; i < CMD_ARGC; i++) - { + } else { + for (unsigned i = 0; i < CMD_ARGC; i++) { /* go through list of vectors */ unsigned j; - for (j = 0; arm9tdmi_vectors[j].name; j++) - { - if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) - { + for (j = 0; arm9tdmi_vectors[j].name; j++) { + if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) { vector_catch_value |= arm9tdmi_vectors[j].value; break; } } /* complain if vector wasn't found */ - if (!arm9tdmi_vectors[j].name) - { + if (!arm9tdmi_vectors[j].name) { command_print(CMD_CTX, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV[i]); /* reread current setting */ vector_catch_value = buf_get_u32( vector_catch->value, 0, 8); - break; } } @@ -935,8 +885,7 @@ const struct command_registration arm9tdmi_command_handlers[] = { }; /** Holds methods for ARM9TDMI targets. */ -struct target_type arm9tdmi_target = -{ +struct target_type arm9tdmi_target = { .name = "arm9tdmi", .poll = arm7_9_poll, diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h index aff9fc5..8d90a38 100644 --- a/src/target/arm9tdmi.h +++ b/src/target/arm9tdmi.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM9TDMI_H #define ARM9TDMI_H @@ -37,7 +38,7 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in); int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be); void arm9tdmi_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]); + uint32_t mask, uint32_t *core_regs[16]); void arm9tdmi_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16]); diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 77d01a0..2203eb5 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -73,7 +73,6 @@ #include "arm_adi_v5.h" #include <helper/time_support.h> - /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ /* @@ -100,12 +99,11 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address * @param apsel Number of the AP to (implicitly) use with further * transactions. This normally identifies a MEM-AP. */ -void dap_ap_select(struct adiv5_dap *dap,uint8_t ap) +void dap_ap_select(struct adiv5_dap *dap, uint8_t ap) { uint32_t new_ap = (ap << 24) & 0xFF000000; - if (new_ap != dap->ap_current) - { + if (new_ap != dap->ap_current) { dap->ap_current = new_ap; /* Switching AP invalidates cached values. * Values MUST BE UPDATED BEFORE AP ACCESS. @@ -140,16 +138,14 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar) int retval; csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if (csw != dap->ap_csw_value) - { + if (csw != dap->ap_csw_value) { /* LOG_DEBUG("DAP: Set CSW %x",csw); */ retval = dap_queue_ap_write(dap, AP_REG_CSW, csw); if (retval != ERROR_OK) return retval; dap->ap_csw_value = csw; } - if (tar != dap->ap_tar_value) - { + if (tar != dap->ap_tar_value) { /* LOG_DEBUG("DAP: Set TAR %x",tar); */ retval = dap_queue_ap_write(dap, AP_REG_TAR, tar); if (retval != ERROR_OK) @@ -274,23 +270,20 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count { int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; - const uint8_t* pBuffer = buffer; + const uint8_t *pBuffer = buffer; count >>= 2; wcount = count; /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (writecount = 0; writecount < count; writecount++) - { + if (adr & 0x3u) { + for (writecount = 0; writecount < count; writecount++) { int i; uint32_t outvalue; memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++) - { - *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; + for (i = 0; i < 4; i++) { + *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue; outvalue >>= 8; adr++; } @@ -298,8 +291,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count } } - while (wcount > 0) - { + while (wcount > 0) { /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) @@ -313,27 +305,22 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count if (retval != ERROR_OK) return retval; - for (writecount = 0; writecount < blocksize; writecount++) - { + for (writecount = 0; writecount < blocksize; writecount++) { retval = dap_queue_ap_write(dap, AP_REG_DRW, *(uint32_t *) ((void *) (buffer + 4 * writecount))); if (retval != ERROR_OK) break; } - if ((retval = dap_run(dap)) == ERROR_OK) - { + retval = dap_run(dap); + if (retval == ERROR_OK) { wcount = wcount - blocksize; address = address + 4 * blocksize; buffer = buffer + 4 * blocksize; - } - else - { + } else errorcount++; - } - if (errorcount > 1) - { + if (errorcount > 1) { LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); return retval; } @@ -350,8 +337,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, wcount = count >> 1; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -369,16 +355,13 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, return retval; writecount = blocksize; - do - { + do { nbytes = MIN((writecount << 1), 4); - if (nbytes < 4) - { + if (nbytes < 4) { retval = mem_ap_write_buf_u16(dap, buffer, nbytes, address); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -386,15 +369,12 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, } address += nbytes >> 1; - } - else - { + } else { uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } @@ -405,8 +385,8 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, if (retval != ERROR_OK) break; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -431,8 +411,7 @@ int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count if (count >= 4) return mem_ap_write_buf_packed_u16(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -463,8 +442,7 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, wcount = count; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -478,15 +456,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, return retval; writecount = blocksize; - do - { + do { nbytes = MIN(writecount, 4); - if (nbytes < 4) - { + if (nbytes < 4) { retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -494,15 +469,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, } address += nbytes; - } - else - { + } else { uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } @@ -513,8 +485,8 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, if (retval != ERROR_OK) break; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -539,8 +511,7 @@ int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, if (count >= 4) return mem_ap_write_buf_packed_u8(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -581,13 +552,12 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, { int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; - uint8_t* pBuffer = buffer; + uint8_t *pBuffer = buffer; count >>= 2; wcount = count; - while (wcount > 0) - { + while (wcount > 0) { /* Adjust to read blocks within boundaries aligned to the * TAR autoincrement size (at least 2^10). Autoincrement * mode avoids an extra per-word roundtrip to update TAR. @@ -618,8 +588,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, DPAP_READ, 0, NULL, NULL); if (retval != ERROR_OK) return retval; - for (readcount = 0; readcount < blocksize - 1; readcount++) - { + for (readcount = 0; readcount < blocksize - 1; readcount++) { /* Scan out next read; scan in posted value for the * previous one. Assumes read is acked "OK/FAULT", * and CTRL_STAT says that meant "OK". @@ -641,11 +610,9 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, return retval; retval = dap_run(dap); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { errorcount++; - if (errorcount <= 1) - { + if (errorcount <= 1) { /* try again */ continue; } @@ -658,17 +625,14 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, } /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (readcount = 0; readcount < count; readcount++) - { + if (adr & 0x3u) { + for (readcount = 0; readcount < count; readcount++) { int i; uint32_t data; memcpy(&data, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++) - { - *((uint8_t*)pBuffer) = + for (i = 0; i < 4; i++) { + *((uint8_t *)pBuffer) = (data >> 8 * (adr & 0x3)); pBuffer++; adr++; @@ -688,8 +652,7 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, wcount = count >> 1; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -706,22 +669,20 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, blocksize = 1; readcount = blocksize; - do - { + do { retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return retval; } nbytes = MIN((readcount << 1), 4); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -751,8 +712,7 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, if (count >= 4) return mem_ap_read_buf_packed_u16(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -764,17 +724,13 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, if (retval != ERROR_OK) break; - if (address & 0x1) - { - for (i = 0; i < 2; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + if (address & 0x1) { + for (i = 0; i < 2; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } - } - else - { + } else { uint16_t svalue = (invalue >> 8 * (address & 0x3)); memcpy(buffer, &svalue, sizeof(uint16_t)); address += 2; @@ -801,8 +757,7 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, wcount = count; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -816,22 +771,20 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, return retval; readcount = blocksize; - do - { + do { retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return retval; } nbytes = MIN(readcount, 4); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -861,8 +814,7 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, if (count >= 4) return mem_ap_read_buf_packed_u8(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -873,7 +825,7 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, if (retval != ERROR_OK) break; - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); count--; address++; buffer++; @@ -999,9 +951,8 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) return retval; dap_run(dap); - if ( val != 0x001C0000 ) - { - LOG_DEBUG("id doesn't match %08X != 0x001C0000",val); + if (val != 0x001C0000) { + LOG_DEBUG("id doesn't match %08X != 0x001C0000", val); dap_ap_select(dap, 0); return ERROR_FAIL; } @@ -1015,40 +966,28 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X",val); + LOG_DEBUG("MDM_REG_STAT %08X", val); - if ( (val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY) ) - { + if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) { LOG_DEBUG("MDMAP: system is secured, masserase needed"); - if ( !(val & MDM_STAT_FMEEN) ) - { + if (!(val & MDM_STAT_FMEEN)) LOG_DEBUG("MDMAP: masserase is disabled"); - } - else - { + else { /* we need to assert reset */ - if ( jtag_reset_config & RESET_HAS_SRST ) - { + if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { jtag_add_reset(1, 1); - } else - { jtag_add_reset(0, 1); - } - } - else - { + } else { LOG_DEBUG("SRST not configured"); dap_ap_select(dap, 0); return ERROR_FAIL; } - while(1) - { + while (1) { retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP); if (retval != ERROR_OK) return retval; @@ -1058,14 +997,13 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X",val); + LOG_DEBUG("MDM_REG_STAT %08X", val); - if ( (val&1)) + if ((val & 1)) break; } - while(1) - { + while (1) { retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0); if (retval != ERROR_OK) return retval; @@ -1075,15 +1013,15 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X",val); + LOG_DEBUG("MDM_REG_STAT %08X", val); /* read control register and wait for ready */ retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val); if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_CTRL %08X",val); + LOG_DEBUG("MDM_REG_CTRL %08X", val); - if ( val == 0x00 ) + if (val == 0x00) break; } } @@ -1107,7 +1045,6 @@ static struct dap_syssec_filter dap_syssec_filter_data[] = { { 0x4BA00477, dap_syssec_kinetis_mdmap } }; - /** * */ @@ -1116,15 +1053,12 @@ int dap_syssec(struct adiv5_dap *dap) unsigned int i; struct jtag_tap *tap; - for(i=0;i<sizeof(dap_syssec_filter_data);i++) - { + for (i = 0; i < sizeof(dap_syssec_filter_data); i++) { tap = dap->jtag_info->tap; - while (tap != NULL) - { - if ( tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode) ) - { - LOG_DEBUG("DAP: mdmap_init for idcode: %08x",tap->idcode); + while (tap != NULL) { + if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) { + LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode); dap_syssec_filter_data[i].dap_init(dap); } tap = tap->next_tap; @@ -1202,28 +1136,29 @@ int ahbap_debugport_init(struct adiv5_dap *dap) retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; /* Check that we have debug power domains activated */ - while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) - { + while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { LOG_DEBUG("DAP: wait CDBGPWRUPACK"); retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; alive_sleep(10); } - while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) - { + while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { LOG_DEBUG("DAP: wait CSYSPWRUPACK"); retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; alive_sleep(10); } @@ -1248,16 +1183,15 @@ int ahbap_debugport_init(struct adiv5_dap *dap) /* CID interpretation -- see ARM IHI 0029B section 3 * and ARM IHI 0031A table 13-3. */ -static const char *class_description[16] ={ +static const char *class_description[16] = { "Reserved", "ROM table", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", "Reserved", "OptimoDE DESS", - "Generic IP component", "PrimeCell or System component" + "Generic IP component", "PrimeCell or System component" }; -static bool -is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) +static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) { return cid3 == 0xb1 && cid2 == 0x05 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; @@ -1320,8 +1254,7 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, ap_old = dap->ap_current; dap_ap_select(dap, ap); - do - { + do { retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); if (retval != ERROR_OK) @@ -1367,10 +1300,8 @@ static int dap_info_command(struct command_context *cmd_ctx, /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); - if (apid) - { - switch (apid&0x0F) - { + if (apid) { + switch (apid&0x0F) { case 0: command_print(cmd_ctx, "\tType is JTAG-AP"); break; @@ -1389,18 +1320,13 @@ static int dap_info_command(struct command_context *cmd_ctx, * not a ROM table ... or have no such components at all. */ if (mem_ap) - command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, - dbgbase); - } - else - { + command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase); + } else command_print(cmd_ctx, "No AP found at this ap 0x%x", ap); - } romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); - if (romtable_present) - { - uint32_t cid0,cid1,cid2,cid3,memtype,romentry; + if (romtable_present) { + uint32_t cid0, cid1, cid2, cid3, memtype, romentry; uint16_t entry_offset; /* bit 16 of apid indicates a memory access port */ @@ -1444,78 +1370,61 @@ static int dap_info_command(struct command_context *cmd_ctx, /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ entry_offset = 0; - do - { + do { retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); if (retval != ERROR_OK) return retval; - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); - if (romentry&0x01) - { + command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry); + if (romentry & 0x01) { uint32_t c_cid0, c_cid1, c_cid2, c_cid3; uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; uint32_t component_base; unsigned part_num; char *type, *full; - component_base = (dbgbase & 0xFFFFF000) - + (romentry & 0xFFFFF000); + component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); /* IDs are in last 4K section */ - - - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFE0, &c_pid0); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); if (retval != ERROR_OK) return retval; c_pid0 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFE4, &c_pid1); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); if (retval != ERROR_OK) return retval; c_pid1 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFE8, &c_pid2); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); if (retval != ERROR_OK) return retval; c_pid2 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFEC, &c_pid3); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); if (retval != ERROR_OK) return retval; c_pid3 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFD0, &c_pid4); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); if (retval != ERROR_OK) return retval; c_pid4 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFF0, &c_cid0); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); if (retval != ERROR_OK) return retval; c_cid0 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFF4, &c_cid1); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); if (retval != ERROR_OK) return retval; c_cid1 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFF8, &c_cid2); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); if (retval != ERROR_OK) return retval; c_cid2 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFFC, &c_cid3); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); if (retval != ERROR_OK) return retval; c_cid3 &= 0xff; - - command_print(cmd_ctx, - "\t\tComponent base address 0x%" PRIx32 - ", start address 0x%" PRIx32, - component_base, + command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 "," + "start address 0x%" PRIx32, component_base, /* component may take multiple 4K pages */ component_base - 0x1000*(c_pid4 >> 4)); command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", @@ -1638,7 +1547,7 @@ static int dap_info_command(struct command_context *cmd_ctx, if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) command_print(cmd_ctx, - "\t\tCID3 0%2.2x" + "\t\tCID3 0%2.2x" ", CID2 0%2.2x" ", CID1 0%2.2x" ", CID0 0%2.2x", @@ -1681,7 +1590,7 @@ static int dap_info_command(struct command_context *cmd_ctx, type = "CoreSight ETM11"; full = "(Embedded Trace)"; break; - // case 0x113: what? + /* case 0x113: what? */ case 0x120: /* from OMAP3 memmap */ type = "TI SDTI"; full = "(System Debug Trace Interface)"; @@ -1741,9 +1650,7 @@ static int dap_info_command(struct command_context *cmd_ctx, } command_print(cmd_ctx, "\t\tPart is %s %s", type, full); - } - else - { + } else { if (romentry) command_print(cmd_ctx, "\t\tComponent not present"); else @@ -1751,11 +1658,8 @@ static int dap_info_command(struct command_context *cmd_ctx, } entry_offset += 4; } while (romentry > 0); - } - else - { + } else command_print(cmd_ctx, "\tNo ROM table present"); - } dap_ap_select(dap, ap_old); return ERROR_OK; @@ -1980,5 +1884,3 @@ const struct command_registration dap_command_handlers[] = { }, COMMAND_REGISTRATION_DONE }; - - diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 1c08547..37b7771 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM_ADI_V5_H #define ARM_ADI_V5_H @@ -133,15 +134,13 @@ * as part of setting up a debug session (if all the dual-role JTAG/SWD * signals are available). */ -struct adiv5_dap -{ +struct adiv5_dap { const struct dap_ops *ops; struct arm_jtag *jtag_info; /* Control config */ uint32_t dp_ctrl_stat; - uint32_t apsel; /** @@ -182,6 +181,7 @@ struct adiv5_dap * MEM-AP access before we try to read its status (and/or result). */ uint32_t memaccess_tck; + /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */ uint32_t tar_autoincr_block; }; @@ -216,6 +216,7 @@ struct dap_ops { /** AP register write. */ int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data); + /** AP operation abort. */ int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack); @@ -249,7 +250,7 @@ static inline int dap_queue_idcode_read(struct adiv5_dap *dap, * @param dap The DAP used for reading. * @param reg The two-bit number of the DP register being read. * @param data Pointer saying where to store the register's value - * (in host endianness). + * (in host endianness). * * @return ERROR_OK for success, else a fault code. */ @@ -284,7 +285,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap, * @param dap The DAP used for reading. * @param reg The number of the AP register being read. * @param data Pointer saying where to store the register's value - * (in host endianness). + * (in host endianness). * * @return ERROR_OK for success, else a fault code. */ @@ -347,11 +348,11 @@ static inline int dap_run(struct adiv5_dap *dap) /** Accessor for currently selected DAP-AP number (0..255) */ static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp) { - return (uint8_t)(swjdp ->ap_current >> 24); + return (uint8_t)(swjdp->ap_current >> 24); } /* AP selection applies to future AP transactions */ -void dap_ap_select(struct adiv5_dap *dap,uint8_t ap); +void dap_ap_select(struct adiv5_dap *dap, uint8_t ap); /* Queued AP transactions */ int dap_setup_accessport(struct adiv5_dap *swjdp, @@ -382,8 +383,6 @@ int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, const uint8_t *buffer, int count, uint32_t address); - - /* Queued MEM-AP memory mapped single word transfers with selection of ap */ int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap, uint32_t address, uint32_t *value); @@ -411,8 +410,6 @@ int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap, int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, const uint8_t *buffer, int count, uint32_t address); - - /* Initialisation of the debug system, power domains and registers */ int ahbap_debugport_init(struct adiv5_dap *swjdp); diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 34d679c..f11a522 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -19,6 +19,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -27,7 +28,6 @@ #include "arm_disassembler.h" #include <helper/log.h> - /* * This disassembler supports two main functions for OpenOCD: * @@ -94,10 +94,9 @@ * the Cortex-M implementations). */ -/* textual represenation of the condition field */ -/* ALways (default) is ommitted (empty string) */ -static const char *arm_condition_strings[] = -{ +/* textual represenation of the condition field + * ALways (default) is ommitted (empty string) */ +static const char *arm_condition_strings[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "", "NV" }; @@ -108,7 +107,7 @@ static uint32_t ror(uint32_t value, int places) } static int evaluate_unknown(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, @@ -118,14 +117,17 @@ static int evaluate_unknown(uint32_t opcode, } static int evaluate_pld(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { /* PLD */ - if ((opcode & 0x0d70f000) == 0x0550f000) - { + if ((opcode & 0x0d70f000) == 0x0550f000) { instruction->type = ARM_PLD; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD ...TODO...", address, opcode); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD ...TODO...", + address, + opcode); return ERROR_OK; } @@ -133,51 +135,51 @@ static int evaluate_pld(uint32_t opcode, } static int evaluate_srs(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { const char *wback = (opcode & (1 << 21)) ? "!" : ""; const char *mode = ""; switch ((opcode >> 23) & 0x3) { - case 0: - mode = "DA"; - break; - case 1: - /* "IA" is default */ - break; - case 2: - mode = "DB"; - break; - case 3: - mode = "IB"; - break; + case 0: + mode = "DA"; + break; + case 1: + /* "IA" is default */ + break; + case 2: + mode = "DB"; + break; + case 3: + mode = "IB"; + break; } switch (opcode & 0x0e500000) { - case 0x08400000: - snprintf(instruction->text, 128, "0x%8.8" PRIx32 + case 0x08400000: + snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSRS%s\tSP%s, #%d", address, opcode, mode, wback, (unsigned)(opcode & 0x1f)); - break; - case 0x08100000: - snprintf(instruction->text, 128, "0x%8.8" PRIx32 + break; + case 0x08100000: + snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tRFE%s\tr%d%s", address, opcode, mode, (unsigned)((opcode >> 16) & 0xf), wback); - break; - default: - return evaluate_unknown(opcode, address, instruction); + break; + default: + return evaluate_unknown(opcode, address, instruction); } return ERROR_OK; } static int evaluate_swi(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { instruction->type = ARM_SWI; @@ -189,7 +191,7 @@ static int evaluate_swi(uint32_t opcode, } static int evaluate_blx_imm(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { int offset; uint32_t immediate; @@ -213,7 +215,12 @@ static int evaluate_blx_imm(uint32_t opcode, target_address = address + 8 + offset; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "", address, opcode, target_address); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "", + address, + opcode, + target_address); instruction->info.b_bl_bx_blx.reg_operand = -1; instruction->info.b_bl_bx_blx.target_address = target_address; @@ -222,7 +229,7 @@ static int evaluate_blx_imm(uint32_t opcode, } static int evaluate_b_bl(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t L; uint32_t immediate; @@ -248,8 +255,14 @@ static int evaluate_b_bl(uint32_t opcode, else instruction->type = ARM_B; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32 , address, opcode, - (L) ? "L" : "", COND(opcode), target_address); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32, + address, + opcode, + (L) ? "L" : "", + COND(opcode), + target_address); instruction->info.b_bl_bx_blx.reg_operand = -1; instruction->info.b_bl_bx_blx.target_address = target_address; @@ -257,16 +270,15 @@ static int evaluate_b_bl(uint32_t opcode, return ERROR_OK; } -/* Coprocessor load/store and double register transfers */ -/* both normal and extended instruction space (condition field b1111) */ +/* Coprocessor load/store and double register transfers + * both normal and extended instruction space (condition field b1111) */ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t cp_num = (opcode & 0xf00) >> 8; /* MCRR or MRRC */ - if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000)) - { + if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000)) { uint8_t cp_opcode, Rd, Rn, CRm; char *mnemonic; @@ -276,8 +288,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, CRm = (opcode & 0xf); /* MCRR */ - if ((opcode & 0x0ff00000) == 0x0c400000) - { + if ((opcode & 0x0ff00000) == 0x0c400000) { instruction->type = ARM_MCRR; mnemonic = "MCRR"; } else if ((opcode & 0x0ff00000) == 0x0c500000) { @@ -292,13 +303,11 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s p%i, %x, r%i, r%i, c%i", - address, opcode, mnemonic, + address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) - ? "2" : COND(opcode), - COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm); - } - else /* LDC or STC */ - { + ? "2" : COND(opcode), + COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm); + } else {/* LDC or STC */ uint8_t CRd, Rn, offset; uint8_t U; char *mnemonic; @@ -309,13 +318,10 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, offset = (opcode & 0xff) << 2; /* load/store */ - if (opcode & 0x00100000) - { + if (opcode & 0x00100000) { instruction->type = ARM_LDC; mnemonic = "LDC"; - } - else - { + } else { instruction->type = ARM_STC; mnemonic = "STC"; } @@ -323,16 +329,16 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, U = (opcode & 0x00800000) >> 23; /* addressing modes */ - if ((opcode & 0x01200000) == 0x01000000) /* offset */ + if ((opcode & 0x01200000) == 0x01000000)/* offset */ snprintf(addressing_mode, 32, "[r%i, #%s%d]", Rn, U ? "" : "-", offset); - else if ((opcode & 0x01200000) == 0x01200000) /* pre-indexed */ + else if ((opcode & 0x01200000) == 0x01200000) /* pre-indexed */ snprintf(addressing_mode, 32, "[r%i, #%s%d]!", Rn, U ? "" : "-", offset); - else if ((opcode & 0x01200000) == 0x00200000) /* post-indexed */ + else if ((opcode & 0x01200000) == 0x00200000) /* post-indexed */ snprintf(addressing_mode, 32, "[r%i], #%s%d", Rn, U ? "" : "-", offset); - else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */ + else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */ snprintf(addressing_mode, 32, "[r%i], {%d}", Rn, offset >> 2); @@ -341,7 +347,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, "\t%s%s%s p%i, c%i, %s", address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) - ? "2" : COND(opcode), + ? "2" : COND(opcode), (opcode & (1 << 22)) ? "L" : "", cp_num, CRd, addressing_mode); } @@ -349,14 +355,14 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, return ERROR_OK; } -/* Coprocessor data processing instructions */ -/* Coprocessor register transfer instructions */ -/* both normal and extended instruction space (condition field b1111) */ +/* Coprocessor data processing instructions + * Coprocessor register transfer instructions + * both normal and extended instruction space (condition field b1111) */ static int evaluate_cdp_mcr_mrc(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { const char *cond; - char* mnemonic; + char *mnemonic; uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2; cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode); @@ -367,35 +373,49 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode, opcode_2 = (opcode & 0xe0) >> 5; /* CDP or MRC/MCR */ - if (opcode & 0x00000010) /* bit 4 set -> MRC/MCR */ - { - if (opcode & 0x00100000) /* bit 20 set -> MRC */ - { + if (opcode & 0x00000010) { /* bit 4 set -> MRC/MCR */ + if (opcode & 0x00100000) { /* bit 20 set -> MRC */ instruction->type = ARM_MRC; mnemonic = "MRC"; - } - else /* bit 20 not set -> MCR */ - { + } else {/* bit 20 not set -> MCR */ instruction->type = ARM_MCR; mnemonic = "MCR"; } opcode_1 = (opcode & 0x00e00000) >> 21; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x", - address, opcode, mnemonic, cond, - cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2); - } - else /* bit 4 not set -> CDP */ - { + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x", + address, + opcode, + mnemonic, + cond, + cp_num, + opcode_1, + CRd_Rd, + CRn, + CRm, + opcode_2); + } else {/* bit 4 not set -> CDP */ instruction->type = ARM_CDP; mnemonic = "CDP"; opcode_1 = (opcode & 0x00f00000) >> 20; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x", - address, opcode, mnemonic, cond, - cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x", + address, + opcode, + mnemonic, + cond, + cp_num, + opcode_1, + CRd_Rd, + CRn, + CRm, + opcode_2); } return ERROR_OK; @@ -403,12 +423,12 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode, /* Load/store instructions */ static int evaluate_load_store(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t I, P, U, B, W, L; uint8_t Rn, Rd; - char *operation; /* "LDR" or "STR" */ - char *suffix; /* "", "B", "T", "BT" */ + char *operation;/* "LDR" or "STR" */ + char *suffix; /* "", "B", "T", "BT" */ char offset[32]; /* examine flags */ @@ -436,37 +456,28 @@ static int evaluate_load_store(uint32_t opcode, operation = "STR"; /* determine instruction type and suffix */ - if (B) - { - if ((P == 0) && (W == 1)) - { + if (B) { + if ((P == 0) && (W == 1)) { if (L) instruction->type = ARM_LDRBT; else instruction->type = ARM_STRBT; suffix = "BT"; - } - else - { + } else { if (L) instruction->type = ARM_LDRB; else instruction->type = ARM_STRB; suffix = "B"; } - } - else - { - if ((P == 0) && (W == 1)) - { + } else { + if ((P == 0) && (W == 1)) { if (L) instruction->type = ARM_LDRT; else instruction->type = ARM_STRT; suffix = "T"; - } - else - { + } else { if (L) instruction->type = ARM_LDR; else @@ -475,8 +486,7 @@ static int evaluate_load_store(uint32_t opcode, } } - if (!I) /* #+-<offset_12> */ - { + if (!I) { /* #+-<offset_12> */ uint32_t offset_12 = (opcode & 0xfff); if (offset_12) snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12); @@ -485,9 +495,7 @@ static int evaluate_load_store(uint32_t opcode, instruction->info.load_store.offset_mode = 0; instruction->info.load_store.offset.offset = offset_12; - } - else /* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */ - { + } else {/* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */ uint8_t shift_imm, shift; uint8_t Rm; @@ -512,57 +520,71 @@ static int evaluate_load_store(uint32_t opcode, instruction->info.load_store.offset.reg.shift = shift; instruction->info.load_store.offset.reg.shift_imm = shift_imm; - if ((shift_imm == 0x0) && (shift == 0x0)) /* +-<Rm> */ - { + if ((shift_imm == 0x0) && (shift == 0x0)) /* +-<Rm> */ snprintf(offset, 32, ", %sr%i", (U) ? "" : "-", Rm); - } - else /* +-<Rm>, <Shift>, #<shift_imm> */ - { - switch (shift) - { - case 0x0: /* LSL */ + else { /* +-<Rm>, <Shift>, #<shift_imm> */ + switch (shift) { + case 0x0: /* LSL */ snprintf(offset, 32, ", %sr%i, LSL #0x%x", (U) ? "" : "-", Rm, shift_imm); break; - case 0x1: /* LSR */ + case 0x1: /* LSR */ snprintf(offset, 32, ", %sr%i, LSR #0x%x", (U) ? "" : "-", Rm, shift_imm); break; - case 0x2: /* ASR */ + case 0x2: /* ASR */ snprintf(offset, 32, ", %sr%i, ASR #0x%x", (U) ? "" : "-", Rm, shift_imm); break; - case 0x3: /* ROR */ + case 0x3: /* ROR */ snprintf(offset, 32, ", %sr%i, ROR #0x%x", (U) ? "" : "-", Rm, shift_imm); break; - case 0x4: /* RRX */ + case 0x4: /* RRX */ snprintf(offset, 32, ", %sr%i, RRX", (U) ? "" : "-", Rm); break; } } } - if (P == 1) - { - if (W == 0) /* offset */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]", - address, opcode, operation, COND(opcode), suffix, - Rd, Rn, offset); + if (P == 1) { + if (W == 0) { /* offset */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]", + address, + opcode, + operation, + COND(opcode), + suffix, + Rd, + Rn, + offset); instruction->info.load_store.index_mode = 0; - } - else /* pre-indexed */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]!", - address, opcode, operation, COND(opcode), suffix, - Rd, Rn, offset); + } else {/* pre-indexed */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]!", + address, + opcode, + operation, + COND(opcode), + suffix, + Rd, + Rn, + offset); instruction->info.load_store.index_mode = 1; } - } - else /* post-indexed */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i]%s", - address, opcode, operation, COND(opcode), suffix, - Rd, Rn, offset); + } else {/* post-indexed */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i]%s", + address, + opcode, + operation, + COND(opcode), + suffix, + Rd, + Rn, + offset); instruction->info.load_store.index_mode = 2; } @@ -578,33 +600,33 @@ static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp) char *type, *rot; switch ((opcode >> 24) & 0x3) { - case 0: - type = "B16"; - break; - case 1: - sprintf(cp, "UNDEFINED"); - return ARM_UNDEFINED_INSTRUCTION; - case 2: - type = "B"; - break; - default: - type = "H"; - break; + case 0: + type = "B16"; + break; + case 1: + sprintf(cp, "UNDEFINED"); + return ARM_UNDEFINED_INSTRUCTION; + case 2: + type = "B"; + break; + default: + type = "H"; + break; } switch ((opcode >> 10) & 0x3) { - case 0: - rot = ""; - break; - case 1: - rot = ", ROR #8"; - break; - case 2: - rot = ", ROR #16"; - break; - default: - rot = ", ROR #24"; - break; + case 0: + rot = ""; + break; + case 1: + rot = ", ROR #8"; + break; + case 2: + rot = ", ROR #16"; + break; + default: + rot = ", ROR #24"; + break; } if (rn == 0xf) { @@ -629,55 +651,55 @@ static int evaluate_p_add_sub(uint32_t opcode, uint32_t address, char *cp) int type; switch ((opcode >> 20) & 0x7) { - case 1: - prefix = "S"; - break; - case 2: - prefix = "Q"; - break; - case 3: - prefix = "SH"; - break; - case 5: - prefix = "U"; - break; - case 6: - prefix = "UQ"; - break; - case 7: - prefix = "UH"; - break; - default: - goto undef; + case 1: + prefix = "S"; + break; + case 2: + prefix = "Q"; + break; + case 3: + prefix = "SH"; + break; + case 5: + prefix = "U"; + break; + case 6: + prefix = "UQ"; + break; + case 7: + prefix = "UH"; + break; + default: + goto undef; } switch ((opcode >> 5) & 0x7) { - case 0: - op = "ADD16"; - type = ARM_ADD; - break; - case 1: - op = "ADDSUBX"; - type = ARM_ADD; - break; - case 2: - op = "SUBADDX"; - type = ARM_SUB; - break; - case 3: - op = "SUB16"; - type = ARM_SUB; - break; - case 4: - op = "ADD8"; - type = ARM_ADD; - break; - case 7: - op = "SUB8"; - type = ARM_SUB; - break; - default: - goto undef; + case 0: + op = "ADD16"; + type = ARM_ADD; + break; + case 1: + op = "ADDSUBX"; + type = ARM_ADD; + break; + case 2: + op = "SUBADDX"; + type = ARM_SUB; + break; + case 3: + op = "SUB16"; + type = ARM_SUB; + break; + case 4: + op = "ADD8"; + type = ARM_ADD; + break; + case 7: + op = "SUB8"; + type = ARM_SUB; + break; + default: + goto undef; } sprintf(cp, "%s%s%s\tr%d, r%d, r%d", prefix, op, COND(opcode), @@ -694,14 +716,14 @@ undef: /* ARMv6 and later support "media" instructions (includes SIMD) */ static int evaluate_media(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { char *cp = instruction->text; char *mnemonic = NULL; sprintf(cp, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t", - address, opcode); + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t", + address, opcode); cp = strchr(cp, 0); /* parallel add/subtract */ @@ -725,11 +747,11 @@ static int evaluate_media(uint32_t opcode, uint32_t address, shift = "LSL"; } sprintf(cp, "PKH%s%s\tr%d, r%d, r%d, %s #%d", - type, COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - shift, imm); + type, COND(opcode), + (int) (opcode >> 12) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + shift, imm); return ERROR_OK; } @@ -742,17 +764,16 @@ static int evaluate_media(uint32_t opcode, uint32_t address, shift = "ASR"; if (imm == 0) imm = 32; - } else { + } else shift = "LSL"; - } sprintf(cp, "%cSAT%s\tr%d, #%d, r%d, %s #%d", - (opcode & (1 << 22)) ? 'U' : 'S', - COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0x1f, - (int) (opcode >> 0) & 0xf, - shift, imm); + (opcode & (1 << 22)) ? 'U' : 'S', + COND(opcode), + (int) (opcode >> 12) & 0xf, + (int) (opcode >> 16) & 0x1f, + (int) (opcode >> 0) & 0xf, + shift, imm); return ERROR_OK; } @@ -768,110 +789,109 @@ static int evaluate_media(uint32_t opcode, uint32_t address, if (rn != 0xf) sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d", - (opcode & (1 << 6)) ? 'S' : 'A', - (opcode & (1 << 5)) ? "X" : "", - COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf, - rn); + (opcode & (1 << 6)) ? 'S' : 'A', + (opcode & (1 << 5)) ? "X" : "", + COND(opcode), + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 8) & 0xf, + rn); else sprintf(cp, "SMU%cD%s%s\tr%d, r%d, r%d", + (opcode & (1 << 6)) ? 'S' : 'A', + (opcode & (1 << 5)) ? "X" : "", + COND(opcode), + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 8) & 0xf); + return ERROR_OK; + } + if ((opcode & 0x01f00000) == 0x01400000) { + sprintf(cp, "SML%cLD%s%s\tr%d, r%d, r%d, r%d", (opcode & (1 << 6)) ? 'S' : 'A', (opcode & (1 << 5)) ? "X" : "", COND(opcode), + (int) (opcode >> 12) & 0xf, (int) (opcode >> 16) & 0xf, (int) (opcode >> 0) & 0xf, (int) (opcode >> 8) & 0xf); return ERROR_OK; } - if ((opcode & 0x01f00000) == 0x01400000) { - sprintf(cp, "SML%cLD%s%s\tr%d, r%d, r%d, r%d", - (opcode & (1 << 6)) ? 'S' : 'A', - (opcode & (1 << 5)) ? "X" : "", - COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf); - return ERROR_OK; - } if ((opcode & 0x01f00000) == 0x01500000) { unsigned rn = (opcode >> 12) & 0xf; switch (opcode & 0xc0) { - case 3: - if (rn == 0xf) - goto undef; + case 3: + if (rn == 0xf) + goto undef; /* FALL THROUGH */ - case 0: - break; - default: - goto undef; + case 0: + break; + default: + goto undef; } if (rn != 0xf) sprintf(cp, "SMML%c%s%s\tr%d, r%d, r%d, r%d", - (opcode & (1 << 6)) ? 'S' : 'A', - (opcode & (1 << 5)) ? "R" : "", - COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf, - rn); + (opcode & (1 << 6)) ? 'S' : 'A', + (opcode & (1 << 5)) ? "R" : "", + COND(opcode), + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 8) & 0xf, + rn); else sprintf(cp, "SMMUL%s%s\tr%d, r%d, r%d", - (opcode & (1 << 5)) ? "R" : "", - COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf); + (opcode & (1 << 5)) ? "R" : "", + COND(opcode), + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 8) & 0xf); return ERROR_OK; } - /* simple matches against the remaining decode bits */ switch (opcode & 0x01f000f0) { - case 0x00a00030: - case 0x00e00030: - /* parallel halfword saturate */ - sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d", - (opcode & (1 << 22)) ? 'U' : 'S', - COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - return ERROR_OK; - case 0x00b00030: - mnemonic = "REV"; - break; - case 0x00b000b0: - mnemonic = "REV16"; - break; - case 0x00f000b0: - mnemonic = "REVSH"; - break; - case 0x008000b0: - /* select bytes */ - sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - return ERROR_OK; - case 0x01800010: - /* unsigned sum of absolute differences */ - if (((opcode >> 12) & 0xf) == 0xf) - sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode), + case 0x00a00030: + case 0x00e00030: + /* parallel halfword saturate */ + sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d", + (opcode & (1 << 22)) ? 'U' : 'S', + COND(opcode), + (int) (opcode >> 12) & 0xf, (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf); - else - sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode), + (int) (opcode >> 0) & 0xf); + return ERROR_OK; + case 0x00b00030: + mnemonic = "REV"; + break; + case 0x00b000b0: + mnemonic = "REV16"; + break; + case 0x00f000b0: + mnemonic = "REVSH"; + break; + case 0x008000b0: + /* select bytes */ + sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode), + (int) (opcode >> 12) & 0xf, (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf, - (int) (opcode >> 12) & 0xf); - return ERROR_OK; + (int) (opcode >> 0) & 0xf); + return ERROR_OK; + case 0x01800010: + /* unsigned sum of absolute differences */ + if (((opcode >> 12) & 0xf) == 0xf) + sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode), + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 8) & 0xf); + else + sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode), + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 12) & 0xf); + return ERROR_OK; } if (mnemonic) { unsigned rm = (opcode >> 0) & 0xf; @@ -889,12 +909,12 @@ undef: /* Miscellaneous load/store instructions */ static int evaluate_misc_load_store(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t P, U, I, W, L, S, H; uint8_t Rn, Rd; - char *operation; /* "LDR" or "STR" */ - char *suffix; /* "H", "SB", "SH", "D" */ + char *operation;/* "LDR" or "STR" */ + char *suffix; /* "H", "SB", "SH", "D" */ char offset[32]; /* examine flags */ @@ -917,63 +937,46 @@ static int evaluate_misc_load_store(uint32_t opcode, instruction->info.load_store.U = U; /* determine instruction type and suffix */ - if (S) /* signed */ - { - if (L) /* load */ - { - if (H) - { + if (S) {/* signed */ + if (L) {/* load */ + if (H) { operation = "LDR"; instruction->type = ARM_LDRSH; suffix = "SH"; - } - else - { + } else { operation = "LDR"; instruction->type = ARM_LDRSB; suffix = "SB"; } - } - else /* there are no signed stores, so this is used to encode double-register load/stores */ - { + } else {/* there are no signed stores, so this is used to encode double-register + *load/stores */ suffix = "D"; - if (H) - { + if (H) { operation = "STR"; instruction->type = ARM_STRD; - } - else - { + } else { operation = "LDR"; instruction->type = ARM_LDRD; } } - } - else /* unsigned */ - { + } else {/* unsigned */ suffix = "H"; - if (L) /* load */ - { + if (L) {/* load */ operation = "LDR"; instruction->type = ARM_LDRH; - } - else /* store */ - { + } else {/* store */ operation = "STR"; instruction->type = ARM_STRH; } } - if (I) /* Immediate offset/index (#+-<offset_8>)*/ - { + if (I) {/* Immediate offset/index (#+-<offset_8>)*/ uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf); snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8); instruction->info.load_store.offset_mode = 0; instruction->info.load_store.offset.offset = offset_8; - } - else /* Register offset/index (+-<Rm>) */ - { + } else {/* Register offset/index (+-<Rm>) */ uint8_t Rm; Rm = (opcode & 0xf); snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm); @@ -984,30 +987,48 @@ static int evaluate_misc_load_store(uint32_t opcode, instruction->info.load_store.offset.reg.shift_imm = 0x0; } - if (P == 1) - { - if (W == 0) /* offset */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]", - address, opcode, operation, COND(opcode), suffix, - Rd, Rn, offset); + if (P == 1) { + if (W == 0) { /* offset */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]", + address, + opcode, + operation, + COND(opcode), + suffix, + Rd, + Rn, + offset); instruction->info.load_store.index_mode = 0; - } - else /* pre-indexed */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]!", - address, opcode, operation, COND(opcode), suffix, - Rd, Rn, offset); + } else {/* pre-indexed */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]!", + address, + opcode, + operation, + COND(opcode), + suffix, + Rd, + Rn, + offset); instruction->info.load_store.index_mode = 1; } - } - else /* post-indexed */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i], %s", - address, opcode, operation, COND(opcode), suffix, - Rd, Rn, offset); + } else {/* post-indexed */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i], %s", + address, + opcode, + operation, + COND(opcode), + suffix, + Rd, + Rn, + offset); instruction->info.load_store.index_mode = 2; } @@ -1017,7 +1038,7 @@ static int evaluate_misc_load_store(uint32_t opcode, /* Load/store multiples instructions */ static int evaluate_ldm_stm(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t P, U, S, W, L, Rn; uint32_t register_list; @@ -1041,82 +1062,68 @@ static int evaluate_ldm_stm(uint32_t opcode, instruction->info.load_store_multiple.S = S; instruction->info.load_store_multiple.W = W; - if (L) - { + if (L) { instruction->type = ARM_LDM; mnemonic = "LDM"; - } - else - { + } else { instruction->type = ARM_STM; mnemonic = "STM"; } - if (P) - { - if (U) - { + if (P) { + if (U) { instruction->info.load_store_multiple.addressing_mode = 1; addressing_mode = "IB"; - } - else - { + } else { instruction->info.load_store_multiple.addressing_mode = 3; addressing_mode = "DB"; } - } - else - { - if (U) - { + } else { + if (U) { instruction->info.load_store_multiple.addressing_mode = 0; /* "IA" is the default in UAL syntax */ addressing_mode = ""; - } - else - { + } else { instruction->info.load_store_multiple.addressing_mode = 2; addressing_mode = "DA"; } } reg_list_p = reg_list; - for (i = 0; i <= 15; i++) - { - if ((register_list >> i) & 1) - { - if (first_reg) - { + for (i = 0; i <= 15; i++) { + if ((register_list >> i) & 1) { + if (first_reg) { first_reg = 0; - reg_list_p += snprintf(reg_list_p, (reg_list + 69 - reg_list_p), "r%i", i); - } - else - { - reg_list_p += snprintf(reg_list_p, (reg_list + 69 - reg_list_p), ", r%i", i); - } + reg_list_p += snprintf(reg_list_p, + (reg_list + 69 - reg_list_p), + "r%i", + i); + } else + reg_list_p += snprintf(reg_list_p, + (reg_list + 69 - reg_list_p), + ", r%i", + i); } } snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s", - address, opcode, - mnemonic, addressing_mode, COND(opcode), - Rn, (W) ? "!" : "", reg_list, (S) ? "^" : ""); + address, opcode, + mnemonic, addressing_mode, COND(opcode), + Rn, (W) ? "!" : "", reg_list, (S) ? "^" : ""); return ERROR_OK; } /* Multiplies, extra load/stores */ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { /* Multiply (accumulate) (long) and Swap/swap byte */ - if ((opcode & 0x000000f0) == 0x00000090) - { + if ((opcode & 0x000000f0) == 0x00000090) { /* Multiply (accumulate) */ - if ((opcode & 0x0f800000) == 0x00000000) - { + if ((opcode & 0x0f800000) == 0x00000000) { uint8_t Rm, Rs, Rn, Rd, S; Rm = opcode & 0xf; Rs = (opcode & 0xf00) >> 8; @@ -1125,26 +1132,39 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, S = (opcode & 0x00100000) >> 20; /* examine A bit (accumulate) */ - if (opcode & 0x00200000) - { + if (opcode & 0x00200000) { instruction->type = ARM_MLA; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMLA%s%s r%i, r%i, r%i, r%i", - address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs, Rn); - } - else - { + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMLA%s%s r%i, r%i, r%i, r%i", + address, + opcode, + COND(opcode), + (S) ? "S" : "", + Rd, + Rm, + Rs, + Rn); + } else { instruction->type = ARM_MUL; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMUL%s%s r%i, r%i, r%i", - address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMUL%s%s r%i, r%i, r%i", + address, + opcode, + COND(opcode), + (S) ? "S" : "", + Rd, + Rm, + Rs); } return ERROR_OK; } /* Multiply (accumulate) long */ - if ((opcode & 0x0f800000) == 0x00800000) - { - char* mnemonic = NULL; + if ((opcode & 0x0f800000) == 0x00800000) { + char *mnemonic = NULL; uint8_t Rm, Rs, RdHi, RdLow, S; Rm = opcode & 0xf; Rs = (opcode & 0xf00) >> 8; @@ -1152,8 +1172,7 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, RdLow = (opcode & 0xf0000) >> 16; S = (opcode & 0x00100000) >> 20; - switch ((opcode & 0x00600000) >> 21) - { + switch ((opcode & 0x00600000) >> 21) { case 0x0: instruction->type = ARM_UMULL; mnemonic = "UMULL"; @@ -1172,16 +1191,24 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, break; } - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, r%i, r%i", - address, opcode, mnemonic, COND(opcode), (S) ? "S" : "", - RdLow, RdHi, Rm, Rs); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, r%i, r%i", + address, + opcode, + mnemonic, + COND(opcode), + (S) ? "S" : "", + RdLow, + RdHi, + Rm, + Rs); return ERROR_OK; } /* Swap/swap byte */ - if ((opcode & 0x0f800000) == 0x01000000) - { + if ((opcode & 0x0f800000) == 0x01000000) { uint8_t Rm, Rd, Rn; Rm = opcode & 0xf; Rd = (opcode & 0xf000) >> 12; @@ -1190,8 +1217,16 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, /* examine B flag */ instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, [r%i]", - address, opcode, (opcode & 0x00400000) ? "SWPB" : "SWP", COND(opcode), Rd, Rm, Rn); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, [r%i]", + address, + opcode, + (opcode & 0x00400000) ? "SWPB" : "SWP", + COND(opcode), + Rd, + Rm, + Rn); return ERROR_OK; } @@ -1201,54 +1236,64 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, } static int evaluate_mrs_msr(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { int R = (opcode & 0x00400000) >> 22; char *PSR = (R) ? "SPSR" : "CPSR"; /* Move register to status register (MSR) */ - if (opcode & 0x00200000) - { + if (opcode & 0x00200000) { instruction->type = ARM_MSR; /* immediate variant */ - if (opcode & 0x02000000) - { + if (opcode & 0x02000000) { uint8_t immediate = (opcode & 0xff); uint8_t rotate = (opcode & 0xf00); - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, 0x%8.8" PRIx32 , - address, opcode, COND(opcode), PSR, - (opcode & 0x10000) ? "c" : "", - (opcode & 0x20000) ? "x" : "", - (opcode & 0x40000) ? "s" : "", - (opcode & 0x80000) ? "f" : "", - ror(immediate, (rotate * 2)) -); - } - else /* register variant */ - { + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, 0x%8.8" PRIx32, + address, + opcode, + COND(opcode), + PSR, + (opcode & 0x10000) ? "c" : "", + (opcode & 0x20000) ? "x" : "", + (opcode & 0x40000) ? "s" : "", + (opcode & 0x80000) ? "f" : "", + ror(immediate, (rotate * 2)) + ); + } else {/* register variant */ uint8_t Rm = opcode & 0xf; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i", - address, opcode, COND(opcode), PSR, - (opcode & 0x10000) ? "c" : "", - (opcode & 0x20000) ? "x" : "", - (opcode & 0x40000) ? "s" : "", - (opcode & 0x80000) ? "f" : "", - Rm -); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i", + address, + opcode, + COND(opcode), + PSR, + (opcode & 0x10000) ? "c" : "", + (opcode & 0x20000) ? "x" : "", + (opcode & 0x40000) ? "s" : "", + (opcode & 0x80000) ? "f" : "", + Rm + ); } - } - else /* Move status register to register (MRS) */ - { + } else {/* Move status register to register (MRS) */ uint8_t Rd; instruction->type = ARM_MRS; Rd = (opcode & 0x0000f000) >> 12; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMRS%s r%i, %s", - address, opcode, COND(opcode), Rd, PSR); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMRS%s r%i, %s", + address, + opcode, + COND(opcode), + Rd, + PSR); } return ERROR_OK; @@ -1256,80 +1301,78 @@ static int evaluate_mrs_msr(uint32_t opcode, /* Miscellaneous instructions */ static int evaluate_misc_instr(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { /* MRS/MSR */ if ((opcode & 0x000000f0) == 0x00000000) - { evaluate_mrs_msr(opcode, address, instruction); - } /* BX */ - if ((opcode & 0x006000f0) == 0x00200010) - { + if ((opcode & 0x006000f0) == 0x00200010) { uint8_t Rm; instruction->type = ARM_BX; Rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i", - address, opcode, COND(opcode), Rm); + address, opcode, COND(opcode), Rm); instruction->info.b_bl_bx_blx.reg_operand = Rm; instruction->info.b_bl_bx_blx.target_address = -1; } /* BXJ - "Jazelle" support (ARMv5-J) */ - if ((opcode & 0x006000f0) == 0x00200020) - { + if ((opcode & 0x006000f0) == 0x00200020) { uint8_t Rm; instruction->type = ARM_BX; Rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i", - address, opcode, COND(opcode), Rm); + address, opcode, COND(opcode), Rm); instruction->info.b_bl_bx_blx.reg_operand = Rm; instruction->info.b_bl_bx_blx.target_address = -1; } /* CLZ */ - if ((opcode & 0x006000f0) == 0x00600010) - { + if ((opcode & 0x006000f0) == 0x00600010) { uint8_t Rm, Rd; instruction->type = ARM_CLZ; Rm = opcode & 0xf; Rd = (opcode & 0xf000) >> 12; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCLZ%s r%i, r%i", - address, opcode, COND(opcode), Rd, Rm); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCLZ%s r%i, r%i", + address, + opcode, + COND(opcode), + Rd, + Rm); } /* BLX(2) */ - if ((opcode & 0x006000f0) == 0x00200030) - { + if ((opcode & 0x006000f0) == 0x00200030) { uint8_t Rm; instruction->type = ARM_BLX; Rm = opcode & 0xf; snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i", - address, opcode, COND(opcode), Rm); + address, opcode, COND(opcode), Rm); instruction->info.b_bl_bx_blx.reg_operand = Rm; instruction->info.b_bl_bx_blx.target_address = -1; } /* Enhanced DSP add/subtracts */ - if ((opcode & 0x0000000f0) == 0x00000050) - { + if ((opcode & 0x0000000f0) == 0x00000050) { uint8_t Rm, Rd, Rn; char *mnemonic = NULL; Rm = opcode & 0xf; Rd = (opcode & 0xf000) >> 12; Rn = (opcode & 0xf0000) >> 16; - switch ((opcode & 0x00600000) >> 21) - { + switch ((opcode & 0x00600000) >> 21) { case 0x0: instruction->type = ARM_QADD; mnemonic = "QADD"; @@ -1348,30 +1391,39 @@ static int evaluate_misc_instr(uint32_t opcode, break; } - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, r%i", - address, opcode, mnemonic, COND(opcode), Rd, Rm, Rn); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, r%i", + address, + opcode, + mnemonic, + COND(opcode), + Rd, + Rm, + Rn); } /* Software breakpoints */ - if ((opcode & 0x0000000f0) == 0x00000070) - { + if ((opcode & 0x0000000f0) == 0x00000070) { uint32_t immediate; instruction->type = ARM_BKPT; immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "", - address, opcode, immediate); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "", + address, + opcode, + immediate); } /* Enhanced DSP multiplies */ - if ((opcode & 0x000000090) == 0x00000080) - { + if ((opcode & 0x000000090) == 0x00000080) { int x = (opcode & 0x20) >> 5; int y = (opcode & 0x40) >> 6; /* SMLA < x><y> */ - if ((opcode & 0x00600000) == 0x00000000) - { + if ((opcode & 0x00600000) == 0x00000000) { uint8_t Rd, Rm, Rs, Rn; instruction->type = ARM_SMLAxy; Rd = (opcode & 0xf0000) >> 16; @@ -1379,14 +1431,22 @@ static int evaluate_misc_instr(uint32_t opcode, Rs = (opcode & 0xf00) >> 8; Rn = (opcode & 0xf000) >> 12; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i", - address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode), - Rd, Rm, Rs, Rn); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i", + address, + opcode, + (x) ? "T" : "B", + (y) ? "T" : "B", + COND(opcode), + Rd, + Rm, + Rs, + Rn); } /* SMLAL < x><y> */ - if ((opcode & 0x00600000) == 0x00400000) - { + if ((opcode & 0x00600000) == 0x00400000) { uint8_t RdLow, RdHi, Rm, Rs; instruction->type = ARM_SMLAxy; RdHi = (opcode & 0xf0000) >> 16; @@ -1394,14 +1454,22 @@ static int evaluate_misc_instr(uint32_t opcode, Rm = (opcode & 0xf); Rs = (opcode & 0xf00) >> 8; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i", - address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode), - RdLow, RdHi, Rm, Rs); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i", + address, + opcode, + (x) ? "T" : "B", + (y) ? "T" : "B", + COND(opcode), + RdLow, + RdHi, + Rm, + Rs); } /* SMLAW < y> */ - if (((opcode & 0x00600000) == 0x00100000) && (x == 0)) - { + if (((opcode & 0x00600000) == 0x00100000) && (x == 0)) { uint8_t Rd, Rm, Rs, Rn; instruction->type = ARM_SMLAWy; Rd = (opcode & 0xf0000) >> 16; @@ -1409,37 +1477,58 @@ static int evaluate_misc_instr(uint32_t opcode, Rs = (opcode & 0xf00) >> 8; Rn = (opcode & 0xf000) >> 12; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLAW%s%s r%i, r%i, r%i, r%i", - address, opcode, (y) ? "T" : "B", COND(opcode), - Rd, Rm, Rs, Rn); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLAW%s%s r%i, r%i, r%i, r%i", + address, + opcode, + (y) ? "T" : "B", + COND(opcode), + Rd, + Rm, + Rs, + Rn); } /* SMUL < x><y> */ - if ((opcode & 0x00600000) == 0x00300000) - { + if ((opcode & 0x00600000) == 0x00300000) { uint8_t Rd, Rm, Rs; instruction->type = ARM_SMULxy; Rd = (opcode & 0xf0000) >> 16; Rm = (opcode & 0xf); Rs = (opcode & 0xf00) >> 8; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s%s r%i, r%i, r%i", - address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode), - Rd, Rm, Rs); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s%s r%i, r%i, r%i", + address, + opcode, + (x) ? "T" : "B", + (y) ? "T" : "B", + COND(opcode), + Rd, + Rm, + Rs); } /* SMULW < y> */ - if (((opcode & 0x00600000) == 0x00100000) && (x == 1)) - { + if (((opcode & 0x00600000) == 0x00100000) && (x == 1)) { uint8_t Rd, Rm, Rs; instruction->type = ARM_SMULWy; Rd = (opcode & 0xf0000) >> 16; Rm = (opcode & 0xf); Rs = (opcode & 0xf00) >> 8; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s r%i, r%i, r%i", - address, opcode, (y) ? "T" : "B", COND(opcode), - Rd, Rm, Rs); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s r%i, r%i, r%i", + address, + opcode, + (y) ? "T" : "B", + COND(opcode), + Rd, + Rm, + Rs); } } @@ -1447,7 +1536,7 @@ static int evaluate_misc_instr(uint32_t opcode, } static int evaluate_data_proc(uint32_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t I, op, S, Rn, Rd; char *mnemonic = NULL; @@ -1464,8 +1553,7 @@ static int evaluate_data_proc(uint32_t opcode, instruction->info.data_proc.Rn = Rn; instruction->info.data_proc.S = S; - switch (op) - { + switch (op) { case 0x0: instruction->type = ARM_AND; mnemonic = "AND"; @@ -1532,8 +1620,7 @@ static int evaluate_data_proc(uint32_t opcode, break; } - if (I) /* immediate shifter operand (#<immediate>)*/ - { + if (I) {/* immediate shifter operand (#<immediate>)*/ uint8_t immed_8 = opcode & 0xff; uint8_t rotate_imm = (opcode & 0xf00) >> 8; uint32_t immediate; @@ -1544,21 +1631,20 @@ static int evaluate_data_proc(uint32_t opcode, instruction->info.data_proc.variant = 0; instruction->info.data_proc.shifter_operand.immediate.immediate = immediate; - } - else /* register-based shifter operand */ - { + } else {/* register-based shifter operand */ uint8_t shift, Rm; shift = (opcode & 0x60) >> 5; Rm = (opcode & 0xf); - if ((opcode & 0x10) != 0x10) /* Immediate shifts ("<Rm>" or "<Rm>, <shift> #<shift_immediate>") */ - { + if ((opcode & 0x10) != 0x10) { /* Immediate shifts ("<Rm>" or "<Rm>, <shift> + *#<shift_immediate>") */ uint8_t shift_imm; shift_imm = (opcode & 0xf80) >> 7; instruction->info.data_proc.variant = 1; instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm; - instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm; + instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = + shift_imm; instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift; /* LSR encodes a shift by 32 bit as 0x0 */ @@ -1574,35 +1660,36 @@ static int evaluate_data_proc(uint32_t opcode, shift = 0x4; if ((shift_imm == 0x0) && (shift == 0x0)) - { snprintf(shifter_operand, 32, "r%i", Rm); - } - else - { - if (shift == 0x0) /* LSL */ - { - snprintf(shifter_operand, 32, "r%i, LSL #0x%x", Rm, shift_imm); - } - else if (shift == 0x1) /* LSR */ - { - snprintf(shifter_operand, 32, "r%i, LSR #0x%x", Rm, shift_imm); - } - else if (shift == 0x2) /* ASR */ - { - snprintf(shifter_operand, 32, "r%i, ASR #0x%x", Rm, shift_imm); - } - else if (shift == 0x3) /* ROR */ - { - snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm); - } - else if (shift == 0x4) /* RRX */ - { + else { + if (shift == 0x0) /* LSL */ + snprintf(shifter_operand, + 32, + "r%i, LSL #0x%x", + Rm, + shift_imm); + else if (shift == 0x1) /* LSR */ + snprintf(shifter_operand, + 32, + "r%i, LSR #0x%x", + Rm, + shift_imm); + else if (shift == 0x2) /* ASR */ + snprintf(shifter_operand, + 32, + "r%i, ASR #0x%x", + Rm, + shift_imm); + else if (shift == 0x3) /* ROR */ + snprintf(shifter_operand, + 32, + "r%i, ROR #0x%x", + Rm, + shift_imm); + else if (shift == 0x4) /* RRX */ snprintf(shifter_operand, 32, "r%i, RRX", Rm); - } } - } - else /* Register shifts ("<Rm>, <shift> <Rs>") */ - { + } else {/* Register shifts ("<Rm>, <shift> <Rs>") */ uint8_t Rs = (opcode & 0xf00) >> 8; instruction->info.data_proc.variant = 2; @@ -1610,52 +1697,60 @@ static int evaluate_data_proc(uint32_t opcode, instruction->info.data_proc.shifter_operand.register_shift.Rs = Rs; instruction->info.data_proc.shifter_operand.register_shift.shift = shift; - if (shift == 0x0) /* LSL */ - { + if (shift == 0x0) /* LSL */ snprintf(shifter_operand, 32, "r%i, LSL r%i", Rm, Rs); - } - else if (shift == 0x1) /* LSR */ - { + else if (shift == 0x1) /* LSR */ snprintf(shifter_operand, 32, "r%i, LSR r%i", Rm, Rs); - } - else if (shift == 0x2) /* ASR */ - { + else if (shift == 0x2) /* ASR */ snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs); - } - else if (shift == 0x3) /* ROR */ - { + else if (shift == 0x3) /* ROR */ snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs); - } } } - if ((op < 0x8) || (op == 0xc) || (op == 0xe)) /* <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand> */ - { - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, %s", - address, opcode, mnemonic, COND(opcode), - (S) ? "S" : "", Rd, Rn, shifter_operand); - } - else if ((op == 0xd) || (op == 0xf)) /* <opcode1>{<cond>}{S} <Rd>, <shifter_operand> */ - { - if (opcode == 0xe1a00000) /* print MOV r0,r0 as NOP */ - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tNOP",address, opcode); + if ((op < 0x8) || (op == 0xc) || (op == 0xe)) { /* <opcode3>{<cond>}{S} <Rd>, <Rn>, + *<shifter_operand> */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, %s", + address, + opcode, + mnemonic, + COND(opcode), + (S) ? "S" : "", + Rd, + Rn, + shifter_operand); + } else if ((op == 0xd) || (op == 0xf)) { /* <opcode1>{<cond>}{S} <Rd>, + *<shifter_operand> */ + if (opcode == 0xe1a00000) /* print MOV r0,r0 as NOP */ + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tNOP", + address, + opcode); else - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, %s", - address, opcode, mnemonic, COND(opcode), - (S) ? "S" : "", Rd, shifter_operand); - } - else /* <opcode2>{<cond>} <Rn>, <shifter_operand> */ - { + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, %s", + address, + opcode, + mnemonic, + COND(opcode), + (S) ? "S" : "", + Rd, + shifter_operand); + } else {/* <opcode2>{<cond>} <Rn>, <shifter_operand> */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, %s", - address, opcode, mnemonic, COND(opcode), - Rn, shifter_operand); + address, opcode, mnemonic, COND(opcode), + Rn, shifter_operand); } return ERROR_OK; } int arm_evaluate_opcode(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { /* clear fields, to avoid confusion */ memset(instruction, 0, sizeof(struct arm_instruction)); @@ -1663,8 +1758,7 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, instruction->instruction_size = 4; /* catch opcodes with condition field [31:28] = b1111 */ - if ((opcode & 0xf0000000) == 0xf0000000) - { + if ((opcode & 0xf0000000) == 0xf0000000) { /* Undefined instruction (or ARMv5E cache preload PLD) */ if ((opcode & 0x08000000) == 0x00000000) return evaluate_pld(opcode, address, instruction); @@ -1677,8 +1771,8 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, if ((opcode & 0x0e000000) == 0x0a000000) return evaluate_blx_imm(opcode, address, instruction); - /* Extended coprocessor opcode space (ARMv5 and higher)*/ - /* Coprocessor load/store and double register transfers */ + /* Extended coprocessor opcode space (ARMv5 and higher) + * Coprocessor load/store and double register transfers */ if ((opcode & 0x0e000000) == 0x0c000000) return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction); @@ -1691,17 +1785,19 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, return evaluate_cdp_mcr_mrc(opcode, address, instruction); /* Undefined instruction */ - if ((opcode & 0x0f000000) == 0x0f000000) - { + if ((opcode & 0x0f000000) == 0x0f000000) { instruction->type = ARM_UNDEFINED_INSTRUCTION; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", + address, + opcode); return ERROR_OK; } } /* catch opcodes with [27:25] = b000 */ - if ((opcode & 0x0e000000) == 0x00000000) - { + if ((opcode & 0x0e000000) == 0x00000000) { /* Multiplies, extra load/stores */ if ((opcode & 0x00000090) == 0x00000090) return evaluate_mul_and_extra_ld_st(opcode, address, instruction); @@ -1714,13 +1810,15 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, } /* catch opcodes with [27:25] = b001 */ - if ((opcode & 0x0e000000) == 0x02000000) - { + if ((opcode & 0x0e000000) == 0x02000000) { /* Undefined instruction */ - if ((opcode & 0x0fb00000) == 0x03000000) - { + if ((opcode & 0x0fb00000) == 0x03000000) { instruction->type = ARM_UNDEFINED_INSTRUCTION; - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode); + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", + address, + opcode); return ERROR_OK; } @@ -1733,15 +1831,13 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, } /* catch opcodes with [27:25] = b010 */ - if ((opcode & 0x0e000000) == 0x04000000) - { + if ((opcode & 0x0e000000) == 0x04000000) { /* Load/store immediate offset */ return evaluate_load_store(opcode, address, instruction); } /* catch opcodes with [27:25] = b011 */ - if ((opcode & 0x0e000000) == 0x06000000) - { + if ((opcode & 0x0e000000) == 0x06000000) { /* Load/store register offset */ if ((opcode & 0x00000010) == 0x00000000) return evaluate_load_store(opcode, address, instruction); @@ -1749,12 +1845,11 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, /* Architecturally Undefined instruction * ... don't expect these to ever be used */ - if ((opcode & 0x07f000f0) == 0x07f000f0) - { + if ((opcode & 0x07f000f0) == 0x07f000f0) { instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEF", - address, opcode); + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEF", + address, opcode); return ERROR_OK; } @@ -1763,29 +1858,25 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, } /* catch opcodes with [27:25] = b100 */ - if ((opcode & 0x0e000000) == 0x08000000) - { + if ((opcode & 0x0e000000) == 0x08000000) { /* Load/store multiple */ return evaluate_ldm_stm(opcode, address, instruction); } /* catch opcodes with [27:25] = b101 */ - if ((opcode & 0x0e000000) == 0x0a000000) - { + if ((opcode & 0x0e000000) == 0x0a000000) { /* Branch and branch with link */ return evaluate_b_bl(opcode, address, instruction); } /* catch opcodes with [27:25] = b110 */ - if ((opcode & 0x0e000000) == 0x0c000000) - { + if ((opcode & 0x0e000000) == 0x0c000000) { /* Coprocessor load/store and double register transfers */ return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction); } /* catch opcodes with [27:25] = b111 */ - if ((opcode & 0x0e000000) == 0x0e000000) - { + if ((opcode & 0x0e000000) == 0x0e000000) { /* Software interrupt */ if ((opcode & 0x0f000000) == 0x0f000000) return evaluate_swi(opcode, address, instruction); @@ -1805,7 +1896,7 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, } static int evaluate_b_bl_blx_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t offset = opcode & 0x7ff; uint32_t opc = (opcode >> 11) & 0x3; @@ -1818,8 +1909,7 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, target_address = address + 4 + (offset << 1); - switch (opc) - { + switch (opc) { /* unconditional branch */ case 0: instruction->type = ARM_B; @@ -1864,7 +1954,7 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, } static int evaluate_add_sub_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t Rd = (opcode >> 0) & 0x7; uint8_t Rn = (opcode >> 3) & 0x7; @@ -1873,13 +1963,10 @@ static int evaluate_add_sub_thumb(uint16_t opcode, uint32_t reg_imm = opcode & (1 << 10); char *mnemonic; - if (opc) - { + if (opc) { instruction->type = ARM_SUB; mnemonic = "SUBS"; - } - else - { + } else { /* REVISIT: if reg_imm == 0, display as "MOVS" */ instruction->type = ARM_ADD; mnemonic = "ADDS"; @@ -1889,28 +1976,25 @@ static int evaluate_add_sub_thumb(uint16_t opcode, instruction->info.data_proc.Rn = Rn; instruction->info.data_proc.S = 1; - if (reg_imm) - { - instruction->info.data_proc.variant = 0; /*immediate*/ + if (reg_imm) { + instruction->info.data_proc.variant = 0;/*immediate*/ instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%d", - address, opcode, mnemonic, Rd, Rn, Rm_imm); - } - else - { - instruction->info.data_proc.variant = 1; /*immediate shift*/ + "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%d", + address, opcode, mnemonic, Rd, Rn, Rm_imm); + } else { + instruction->info.data_proc.variant = 1;/*immediate shift*/ instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, r%i", - address, opcode, mnemonic, Rd, Rn, Rm_imm); + "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, r%i", + address, opcode, mnemonic, Rd, Rn, Rm_imm); } return ERROR_OK; } static int evaluate_shift_imm_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t Rd = (opcode >> 0) & 0x7; uint8_t Rm = (opcode >> 3) & 0x7; @@ -1918,8 +2002,7 @@ static int evaluate_shift_imm_thumb(uint16_t opcode, uint8_t opc = (opcode >> 11) & 0x3; char *mnemonic = NULL; - switch (opc) - { + switch (opc) { case 0: instruction->type = ARM_MOV; mnemonic = "LSLS"; @@ -1944,19 +2027,19 @@ static int evaluate_shift_imm_thumb(uint16_t opcode, instruction->info.data_proc.Rn = -1; instruction->info.data_proc.S = 1; - instruction->info.data_proc.variant = 1; /*immediate_shift*/ + instruction->info.data_proc.variant = 1;/*immediate_shift*/ instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm; instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%#2.2x" , + "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i, #%#2.2x", address, opcode, mnemonic, Rd, Rm, imm); return ERROR_OK; } static int evaluate_data_proc_imm_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t imm = opcode & 0xff; uint8_t Rd = (opcode >> 8) & 0x7; @@ -1966,11 +2049,10 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, instruction->info.data_proc.Rd = Rd; instruction->info.data_proc.Rn = Rd; instruction->info.data_proc.S = 1; - instruction->info.data_proc.variant = 0; /*immediate*/ + instruction->info.data_proc.variant = 0;/*immediate*/ instruction->info.data_proc.shifter_operand.immediate.immediate = imm; - switch (opc) - { + switch (opc) { case 0: instruction->type = ARM_MOV; mnemonic = "MOVS"; @@ -1999,9 +2081,9 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, } static int evaluate_data_proc_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { - uint8_t high_reg, op, Rm, Rd,H1,H2; + uint8_t high_reg, op, Rm, Rd, H1, H2; char *mnemonic = NULL; bool nop = false; @@ -2016,17 +2098,15 @@ static int evaluate_data_proc_thumb(uint16_t opcode, instruction->info.data_proc.Rd = Rd; instruction->info.data_proc.Rn = Rd; instruction->info.data_proc.S = (!high_reg || (instruction->type == ARM_CMP)); - instruction->info.data_proc.variant = 1 /*immediate shift*/; + instruction->info.data_proc.variant = 1 /*immediate shift*/; instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm; - if (high_reg) - { + if (high_reg) { Rd |= H1 << 3; Rm |= H2 << 3; op >>= 2; - switch (op) - { + switch (op) { case 0x0: instruction->type = ARM_ADD; mnemonic = "ADD"; @@ -2042,43 +2122,34 @@ static int evaluate_data_proc_thumb(uint16_t opcode, nop = true; break; case 0x3: - if ((opcode & 0x7) == 0x0) - { + if ((opcode & 0x7) == 0x0) { instruction->info.b_bl_bx_blx.reg_operand = Rm; - if (H1) - { + if (H1) { instruction->type = ARM_BLX; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \tBLX\tr%i", - address, opcode, Rm); - } - else - { + "0x%8.8" PRIx32 + " 0x%4.4x \tBLX\tr%i", + address, opcode, Rm); + } else { instruction->type = ARM_BX; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \tBX\tr%i", - address, opcode, Rm); + "0x%8.8" PRIx32 + " 0x%4.4x \tBX\tr%i", + address, opcode, Rm); } - } - else - { + } else { instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \t" - "UNDEFINED INSTRUCTION", - address, opcode); + "0x%8.8" PRIx32 + " 0x%4.4x \t" + "UNDEFINED INSTRUCTION", + address, opcode); } return ERROR_OK; break; } - } - else - { - switch (op) - { + } else { + switch (op) { case 0x0: instruction->type = ARM_AND; mnemonic = "ANDS"; @@ -2090,7 +2161,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode, case 0x2: instruction->type = ARM_MOV; mnemonic = "LSLS"; - instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 0; instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; @@ -2098,7 +2169,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode, case 0x3: instruction->type = ARM_MOV; mnemonic = "LSRS"; - instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 1; instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; @@ -2106,7 +2177,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode, case 0x4: instruction->type = ARM_MOV; mnemonic = "ASRS"; - instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 2; instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; @@ -2122,7 +2193,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode, case 0x7: instruction->type = ARM_MOV; mnemonic = "RORS"; - instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.variant = 2 /*register shift*/; instruction->info.data_proc.shifter_operand.register_shift.shift = 3; instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd; instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm; @@ -2134,7 +2205,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode, case 0x9: instruction->type = ARM_RSB; mnemonic = "RSBS"; - instruction->info.data_proc.variant = 0 /*immediate*/; + instruction->info.data_proc.variant = 0 /*immediate*/; instruction->info.data_proc.shifter_operand.immediate.immediate = 0; instruction->info.data_proc.Rn = Rm; break; @@ -2169,11 +2240,11 @@ static int evaluate_data_proc_thumb(uint16_t opcode, snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tNOP\t\t\t" "; (%s r%i, r%i)", - address, opcode, mnemonic, Rd, Rm); + address, opcode, mnemonic, Rd, Rm); else snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, r%i", - address, opcode, mnemonic, Rd, Rm); + address, opcode, mnemonic, Rd, Rm); return ERROR_OK; } @@ -2185,7 +2256,7 @@ static inline uint32_t thumb_alignpc4(uint32_t addr) } static int evaluate_load_literal_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t immediate; uint8_t Rd = (opcode >> 8) & 0x7; @@ -2196,21 +2267,21 @@ static int evaluate_load_literal_thumb(uint16_t opcode, instruction->info.load_store.Rd = Rd; instruction->info.load_store.Rn = 15 /*PC*/; - instruction->info.load_store.index_mode = 0; /*offset*/ - instruction->info.load_store.offset_mode = 0; /*immediate*/ + instruction->info.load_store.index_mode = 0; /*offset*/ + instruction->info.load_store.offset_mode = 0; /*immediate*/ instruction->info.load_store.offset.offset = immediate; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \t" - "LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8" PRIx32, - address, opcode, Rd, immediate, - thumb_alignpc4(address) + immediate); + "0x%8.8" PRIx32 " 0x%4.4x \t" + "LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8" PRIx32, + address, opcode, Rd, immediate, + thumb_alignpc4(address) + immediate); return ERROR_OK; } static int evaluate_load_store_reg_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint8_t Rd = (opcode >> 0) & 0x7; uint8_t Rn = (opcode >> 3) & 0x7; @@ -2218,8 +2289,7 @@ static int evaluate_load_store_reg_thumb(uint16_t opcode, uint8_t opc = (opcode >> 9) & 0x7; char *mnemonic = NULL; - switch (opc) - { + switch (opc) { case 0: instruction->type = ARM_STR; mnemonic = "STR"; @@ -2260,15 +2330,15 @@ static int evaluate_load_store_reg_thumb(uint16_t opcode, instruction->info.load_store.Rd = Rd; instruction->info.load_store.Rn = Rn; - instruction->info.load_store.index_mode = 0; /*offset*/ - instruction->info.load_store.offset_mode = 1; /*register*/ + instruction->info.load_store.index_mode = 0; /*offset*/ + instruction->info.load_store.offset_mode = 1; /*register*/ instruction->info.load_store.offset.reg.Rm = Rm; return ERROR_OK; } static int evaluate_load_store_imm_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t offset = (opcode >> 6) & 0x1f; uint8_t Rd = (opcode >> 0) & 0x7; @@ -2279,75 +2349,66 @@ static int evaluate_load_store_imm_thumb(uint16_t opcode, char suffix = ' '; uint32_t shift = 2; - if (L) - { + if (L) { instruction->type = ARM_LDR; mnemonic = "LDR"; - } - else - { + } else { instruction->type = ARM_STR; mnemonic = "STR"; } - if ((opcode&0xF000) == 0x8000) - { + if ((opcode&0xF000) == 0x8000) { suffix = 'H'; shift = 1; - } - else if (B) - { + } else if (B) { suffix = 'B'; shift = 0; } snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \t%s%c\tr%i, [r%i, #%#" PRIx32 "]", - address, opcode, mnemonic, suffix, Rd, Rn, offset << shift); + "0x%8.8" PRIx32 " 0x%4.4x \t%s%c\tr%i, [r%i, #%#" PRIx32 "]", + address, opcode, mnemonic, suffix, Rd, Rn, offset << shift); instruction->info.load_store.Rd = Rd; instruction->info.load_store.Rn = Rn; - instruction->info.load_store.index_mode = 0; /*offset*/ - instruction->info.load_store.offset_mode = 0; /*immediate*/ + instruction->info.load_store.index_mode = 0; /*offset*/ + instruction->info.load_store.offset_mode = 0; /*immediate*/ instruction->info.load_store.offset.offset = offset << shift; return ERROR_OK; } static int evaluate_load_store_stack_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t offset = opcode & 0xff; uint8_t Rd = (opcode >> 8) & 0x7; uint32_t L = opcode & (1 << 11); char *mnemonic; - if (L) - { + if (L) { instruction->type = ARM_LDR; mnemonic = "LDR"; - } - else - { + } else { instruction->type = ARM_STR; mnemonic = "STR"; } snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [SP, #%#" PRIx32 "]", - address, opcode, mnemonic, Rd, offset*4); + "0x%8.8" PRIx32 " 0x%4.4x \t%s\tr%i, [SP, #%#" PRIx32 "]", + address, opcode, mnemonic, Rd, offset*4); instruction->info.load_store.Rd = Rd; instruction->info.load_store.Rn = 13 /*SP*/; - instruction->info.load_store.index_mode = 0; /*offset*/ - instruction->info.load_store.offset_mode = 0; /*immediate*/ + instruction->info.load_store.index_mode = 0; /*offset*/ + instruction->info.load_store.offset_mode = 0; /*immediate*/ instruction->info.load_store.offset.offset = offset*4; return ERROR_OK; } static int evaluate_add_sp_pc_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t imm = opcode & 0xff; uint8_t Rd = (opcode >> 8) & 0x7; @@ -2357,22 +2418,19 @@ static int evaluate_add_sp_pc_thumb(uint16_t opcode, instruction->type = ARM_ADD; - if (SP) - { + if (SP) { reg_name = "SP"; Rn = 13; - } - else - { + } else { reg_name = "PC"; Rn = 15; } snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \tADD\tr%i, %s, #%#" PRIx32, - address, opcode, Rd, reg_name, imm * 4); + "0x%8.8" PRIx32 " 0x%4.4x \tADD\tr%i, %s, #%#" PRIx32, + address, opcode, Rd, reg_name, imm * 4); - instruction->info.data_proc.variant = 0 /* immediate */; + instruction->info.data_proc.variant = 0 /* immediate */; instruction->info.data_proc.Rd = Rd; instruction->info.data_proc.Rn = Rn; instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4; @@ -2381,20 +2439,17 @@ static int evaluate_add_sp_pc_thumb(uint16_t opcode, } static int evaluate_adjust_stack_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t imm = opcode & 0x7f; uint8_t opc = opcode & (1 << 7); char *mnemonic; - if (opc) - { + if (opc) { instruction->type = ARM_SUB; mnemonic = "SUB"; - } - else - { + } else { instruction->type = ARM_ADD; mnemonic = "ADD"; } @@ -2403,7 +2458,7 @@ static int evaluate_adjust_stack_thumb(uint16_t opcode, "0x%8.8" PRIx32 " 0x%4.4x \t%s\tSP, #%#" PRIx32, address, opcode, mnemonic, imm*4); - instruction->info.data_proc.variant = 0 /* immediate */; + instruction->info.data_proc.variant = 0 /* immediate */; instruction->info.data_proc.Rd = 13 /*SP*/; instruction->info.data_proc.Rn = 13 /*SP*/; instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4; @@ -2412,7 +2467,7 @@ static int evaluate_adjust_stack_thumb(uint16_t opcode, } static int evaluate_breakpoint_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t imm = opcode & 0xff; @@ -2426,7 +2481,7 @@ static int evaluate_breakpoint_thumb(uint16_t opcode, } static int evaluate_load_store_multiple_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t reg_list = opcode & 0xff; uint32_t L = opcode & (1 << 11); @@ -2443,53 +2498,46 @@ static int evaluate_load_store_multiple_thumb(uint16_t opcode, * The STMIA and LDMIA opcodes are used for other instructions. */ - if ((opcode & 0xf000) == 0xc000) - { /* generic load/store multiple */ + if ((opcode & 0xf000) == 0xc000) { /* generic load/store multiple */ char *wback = "!"; - if (L) - { + if (L) { instruction->type = ARM_LDM; mnemonic = "LDM"; if (opcode & (1 << Rn)) wback = ""; - } - else - { + } else { instruction->type = ARM_STM; mnemonic = "STM"; } snprintf(ptr_name, sizeof ptr_name, "r%i%s, ", Rn, wback); - } - else - { /* push/pop */ - Rn = 13; /* SP */ - if (L) - { + } else {/* push/pop */ + Rn = 13;/* SP */ + if (L) { instruction->type = ARM_LDM; mnemonic = "POP"; if (R) reg_list |= (1 << 15) /*PC*/; - } - else - { + } else { instruction->type = ARM_STM; mnemonic = "PUSH"; - addr_mode = 3; /*DB*/ + addr_mode = 3; /*DB*/ if (R) reg_list |= (1 << 14) /*LR*/; } } reg_names_p = reg_names; - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (reg_list & (1 << i)) - reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i); + reg_names_p += snprintf(reg_names_p, + (reg_names + 40 - reg_names_p), + "r%i, ", + i); } if (reg_names_p > reg_names) reg_names_p[-2] = '\0'; - else /* invalid op : no registers */ + else /* invalid op : no registers */ reg_names[0] = '\0'; snprintf(instruction->text, 128, @@ -2504,26 +2552,23 @@ static int evaluate_load_store_multiple_thumb(uint16_t opcode, } static int evaluate_cond_branch_thumb(uint16_t opcode, - uint32_t address, struct arm_instruction *instruction) + uint32_t address, struct arm_instruction *instruction) { uint32_t offset = opcode & 0xff; uint8_t cond = (opcode >> 8) & 0xf; uint32_t target_address; - if (cond == 0xf) - { + if (cond == 0xf) { instruction->type = ARM_SWI; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tSVC\t%#2.2" PRIx32, address, opcode, offset); return ERROR_OK; - } - else if (cond == 0xe) - { + } else if (cond == 0xe) { instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION", - address, opcode); + "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION", + address, opcode); return ERROR_OK; } @@ -2546,7 +2591,7 @@ static int evaluate_cond_branch_thumb(uint16_t opcode, } static int evaluate_cb_thumb(uint16_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { unsigned offset; @@ -2564,7 +2609,7 @@ static int evaluate_cb_thumb(uint16_t opcode, uint32_t address, } static int evaluate_extend_thumb(uint16_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { /* added in ARMv6 */ snprintf(instruction->text, 128, @@ -2578,7 +2623,7 @@ static int evaluate_extend_thumb(uint16_t opcode, uint32_t address, } static int evaluate_cps_thumb(uint16_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { /* added in ARMv6 */ if ((opcode & 0x0ff0) == 0x0650) @@ -2586,7 +2631,7 @@ static int evaluate_cps_thumb(uint16_t opcode, uint32_t address, "0x%8.8" PRIx32 " 0x%4.4x \tSETEND %s", address, opcode, (opcode & 0x80) ? "BE" : "LE"); - else /* ASSUME (opcode & 0x0fe0) == 0x0660 */ + else /* ASSUME (opcode & 0x0fe0) == 0x0660 */ snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c\t%s%s%s", address, opcode, @@ -2599,21 +2644,21 @@ static int evaluate_cps_thumb(uint16_t opcode, uint32_t address, } static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { char *suffix; /* added in ARMv6 */ switch ((opcode >> 6) & 3) { - case 0: - suffix = ""; - break; - case 1: - suffix = "16"; - break; - default: - suffix = "SH"; - break; + case 0: + suffix = ""; + break; + case 1: + suffix = "16"; + break; + default: + suffix = "SH"; + break; } snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tREV%s\tr%d, r%d", @@ -2624,29 +2669,29 @@ static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address, } static int evaluate_hint_thumb(uint16_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { char *hint; switch ((opcode >> 4) & 0x0f) { - case 0: - hint = "NOP"; - break; - case 1: - hint = "YIELD"; - break; - case 2: - hint = "WFE"; - break; - case 3: - hint = "WFI"; - break; - case 4: - hint = "SEV"; - break; - default: - hint = "HINT (UNRECOGNIZED)"; - break; + case 0: + hint = "NOP"; + break; + case 1: + hint = "YIELD"; + break; + case 2: + hint = "WFE"; + break; + case 3: + hint = "WFI"; + break; + case 4: + hint = "SEV"; + break; + default: + hint = "HINT (UNRECOGNIZED)"; + break; } snprintf(instruction->text, 128, @@ -2657,7 +2702,7 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address, } static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { unsigned cond = (opcode >> 4) & 0x0f; char *x = "", *y = "", *z = ""; @@ -2688,8 +2733,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct instruction->opcode = opcode; instruction->instruction_size = 2; - if ((opcode & 0xe000) == 0x0000) - { + if ((opcode & 0xe000) == 0x0000) { /* add/substract register or immediate */ if ((opcode & 0x1800) == 0x1800) return evaluate_add_sub_thumb(opcode, address, instruction); @@ -2700,118 +2744,94 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct /* Add/substract/compare/move immediate */ if ((opcode & 0xe000) == 0x2000) - { return evaluate_data_proc_imm_thumb(opcode, address, instruction); - } /* Data processing instructions */ if ((opcode & 0xf800) == 0x4000) - { return evaluate_data_proc_thumb(opcode, address, instruction); - } /* Load from literal pool */ if ((opcode & 0xf800) == 0x4800) - { return evaluate_load_literal_thumb(opcode, address, instruction); - } /* Load/Store register offset */ if ((opcode & 0xf000) == 0x5000) - { return evaluate_load_store_reg_thumb(opcode, address, instruction); - } /* Load/Store immediate offset */ if (((opcode & 0xe000) == 0x6000) - ||((opcode & 0xf000) == 0x8000)) - { + || ((opcode & 0xf000) == 0x8000)) return evaluate_load_store_imm_thumb(opcode, address, instruction); - } /* Load/Store from/to stack */ if ((opcode & 0xf000) == 0x9000) - { return evaluate_load_store_stack_thumb(opcode, address, instruction); - } /* Add to SP/PC */ if ((opcode & 0xf000) == 0xa000) - { return evaluate_add_sp_pc_thumb(opcode, address, instruction); - } /* Misc */ - if ((opcode & 0xf000) == 0xb000) - { + if ((opcode & 0xf000) == 0xb000) { switch ((opcode >> 8) & 0x0f) { - case 0x0: - return evaluate_adjust_stack_thumb(opcode, address, instruction); - case 0x1: - case 0x3: - case 0x9: - case 0xb: - return evaluate_cb_thumb(opcode, address, instruction); - case 0x2: - return evaluate_extend_thumb(opcode, address, instruction); - case 0x4: - case 0x5: - case 0xc: - case 0xd: - return evaluate_load_store_multiple_thumb(opcode, address, - instruction); - case 0x6: - return evaluate_cps_thumb(opcode, address, instruction); - case 0xa: - if ((opcode & 0x00c0) == 0x0080) - break; - return evaluate_byterev_thumb(opcode, address, instruction); - case 0xe: - return evaluate_breakpoint_thumb(opcode, address, instruction); - case 0xf: - if (opcode & 0x000f) - return evaluate_ifthen_thumb(opcode, address, - instruction); - else - return evaluate_hint_thumb(opcode, address, - instruction); + case 0x0: + return evaluate_adjust_stack_thumb(opcode, address, instruction); + case 0x1: + case 0x3: + case 0x9: + case 0xb: + return evaluate_cb_thumb(opcode, address, instruction); + case 0x2: + return evaluate_extend_thumb(opcode, address, instruction); + case 0x4: + case 0x5: + case 0xc: + case 0xd: + return evaluate_load_store_multiple_thumb(opcode, address, + instruction); + case 0x6: + return evaluate_cps_thumb(opcode, address, instruction); + case 0xa: + if ((opcode & 0x00c0) == 0x0080) + break; + return evaluate_byterev_thumb(opcode, address, instruction); + case 0xe: + return evaluate_breakpoint_thumb(opcode, address, instruction); + case 0xf: + if (opcode & 0x000f) + return evaluate_ifthen_thumb(opcode, address, + instruction); + else + return evaluate_hint_thumb(opcode, address, + instruction); } instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION", - address, opcode); + "0x%8.8" PRIx32 " 0x%4.4x \tUNDEFINED INSTRUCTION", + address, opcode); return ERROR_OK; } /* Load/Store multiple */ if ((opcode & 0xf000) == 0xc000) - { return evaluate_load_store_multiple_thumb(opcode, address, instruction); - } /* Conditional branch + SWI */ if ((opcode & 0xf000) == 0xd000) - { return evaluate_cond_branch_thumb(opcode, address, instruction); - } - if ((opcode & 0xe000) == 0xe000) - { + if ((opcode & 0xe000) == 0xe000) { /* Undefined instructions */ - if ((opcode & 0xf801) == 0xe801) - { + if ((opcode & 0xf801) == 0xe801) { instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%8.8x\t" "UNDEFINED INSTRUCTION", address, opcode); return ERROR_OK; - } - else - { /* Branch to offset */ + } else /* Branch to offset */ return evaluate_b_bl_blx_thumb(opcode, address, instruction); - } } LOG_ERROR("Thumb: should never reach this point (opcode=%04x)", opcode); @@ -2819,7 +2839,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct } static int t2ev_b_bl(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { unsigned offset; unsigned b21 = 1 << 21; @@ -2860,7 +2880,7 @@ static int t2ev_b_bl(uint32_t opcode, uint32_t address, } static int t2ev_cond_b(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { unsigned offset; unsigned b17 = 1 << 17; @@ -2902,54 +2922,54 @@ static const char *special_name(int number) char *special = "(RESERVED)"; switch (number) { - case 0: - special = "apsr"; - break; - case 1: - special = "iapsr"; - break; - case 2: - special = "eapsr"; - break; - case 3: - special = "xpsr"; - break; - case 5: - special = "ipsr"; - break; - case 6: - special = "epsr"; - break; - case 7: - special = "iepsr"; - break; - case 8: - special = "msp"; - break; - case 9: - special = "psp"; - break; - case 16: - special = "primask"; - break; - case 17: - special = "basepri"; - break; - case 18: - special = "basepri_max"; - break; - case 19: - special = "faultmask"; - break; - case 20: - special = "control"; - break; + case 0: + special = "apsr"; + break; + case 1: + special = "iapsr"; + break; + case 2: + special = "eapsr"; + break; + case 3: + special = "xpsr"; + break; + case 5: + special = "ipsr"; + break; + case 6: + special = "epsr"; + break; + case 7: + special = "iepsr"; + break; + case 8: + special = "msp"; + break; + case 9: + special = "psp"; + break; + case 16: + special = "primask"; + break; + case 17: + special = "basepri"; + break; + case 18: + special = "basepri_max"; + break; + case 19: + special = "faultmask"; + break; + case 20: + special = "control"; + break; } return special; } static int t2ev_hint(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { const char *mnemonic; @@ -2965,62 +2985,62 @@ static int t2ev_hint(uint32_t opcode, uint32_t address, } switch (opcode & 0x0f) { - case 0: - mnemonic = "NOP.W"; - break; - case 1: - mnemonic = "YIELD.W"; - break; - case 2: - mnemonic = "WFE.W"; - break; - case 3: - mnemonic = "WFI.W"; - break; - case 4: - mnemonic = "SEV.W"; - break; - default: - mnemonic = "HINT.W (UNRECOGNIZED)"; - break; + case 0: + mnemonic = "NOP.W"; + break; + case 1: + mnemonic = "YIELD.W"; + break; + case 2: + mnemonic = "WFE.W"; + break; + case 3: + mnemonic = "WFI.W"; + break; + case 4: + mnemonic = "SEV.W"; + break; + default: + mnemonic = "HINT.W (UNRECOGNIZED)"; + break; } strcpy(cp, mnemonic); return ERROR_OK; } static int t2ev_misc(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { const char *mnemonic; switch ((opcode >> 4) & 0x0f) { - case 0: - mnemonic = "LEAVEX"; - break; - case 1: - mnemonic = "ENTERX"; - break; - case 2: - mnemonic = "CLREX"; - break; - case 4: - mnemonic = "DSB"; - break; - case 5: - mnemonic = "DMB"; - break; - case 6: - mnemonic = "ISB"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + mnemonic = "LEAVEX"; + break; + case 1: + mnemonic = "ENTERX"; + break; + case 2: + mnemonic = "CLREX"; + break; + case 4: + mnemonic = "DSB"; + break; + case 5: + mnemonic = "DMB"; + break; + case 6: + mnemonic = "ISB"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } strcpy(cp, mnemonic); return ERROR_OK; } static int t2ev_b_misc(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { /* permanently undefined */ if ((opcode & 0x07f07000) == 0x07f02000) { @@ -3030,37 +3050,37 @@ static int t2ev_b_misc(uint32_t opcode, uint32_t address, } switch ((opcode >> 12) & 0x5) { - case 0x1: - case 0x5: - return t2ev_b_bl(opcode, address, instruction, cp); - case 0x4: - goto undef; - case 0: - if (((opcode >> 23) & 0x07) != 0x07) - return t2ev_cond_b(opcode, address, instruction, cp); - if (opcode & (1 << 26)) + case 0x1: + case 0x5: + return t2ev_b_bl(opcode, address, instruction, cp); + case 0x4: goto undef; - break; + case 0: + if (((opcode >> 23) & 0x07) != 0x07) + return t2ev_cond_b(opcode, address, instruction, cp); + if (opcode & (1 << 26)) + goto undef; + break; } switch ((opcode >> 20) & 0x7f) { - case 0x38: - case 0x39: - sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff), + case 0x38: + case 0x39: + sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff), (int) (opcode >> 16) & 0x0f); - return ERROR_OK; - case 0x3a: - return t2ev_hint(opcode, address, instruction, cp); - case 0x3b: - return t2ev_misc(opcode, address, instruction, cp); - case 0x3c: - sprintf(cp, "BXJ\tr%d", (int) (opcode >> 16) & 0x0f); - return ERROR_OK; - case 0x3e: - case 0x3f: - sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f, + return ERROR_OK; + case 0x3a: + return t2ev_hint(opcode, address, instruction, cp); + case 0x3b: + return t2ev_misc(opcode, address, instruction, cp); + case 0x3c: + sprintf(cp, "BXJ\tr%d", (int) (opcode >> 16) & 0x0f); + return ERROR_OK; + case 0x3e: + case 0x3f: + sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f, special_name(opcode & 0xff)); - return ERROR_OK; + return ERROR_OK; } undef: @@ -3068,7 +3088,7 @@ undef: } static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { char *mnemonic = NULL; int rn = (opcode >> 16) & 0xf; @@ -3088,123 +3108,123 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address, /* "Modified" immediates */ switch (func >> 1) { - case 0: - break; - case 2: - immed <<= 8; + case 0: + break; + case 2: + immed <<= 8; /* FALLTHROUGH */ - case 1: - immed += immed << 16; - break; - case 3: - immed += immed << 8; - immed += immed << 16; - break; - default: - immed |= 0x80; - immed = ror(immed, func); + case 1: + immed += immed << 16; + break; + case 3: + immed += immed << 8; + immed += immed << 16; + break; + default: + immed |= 0x80; + immed = ror(immed, func); } if (opcode & (1 << 20)) suffix = "S"; switch ((opcode >> 21) & 0xf) { - case 0: - if (rd == 0xf) { - instruction->type = ARM_TST; - mnemonic = "TST"; - one = true; - suffix = ""; - rd = rn; - } else { - instruction->type = ARM_AND; - mnemonic = "AND"; - } - break; - case 1: - instruction->type = ARM_BIC; - mnemonic = "BIC"; - break; - case 2: - if (rn == 0xf) { - instruction->type = ARM_MOV; - mnemonic = "MOV"; - one = true; + case 0: + if (rd == 0xf) { + instruction->type = ARM_TST; + mnemonic = "TST"; + one = true; + suffix = ""; + rd = rn; + } else { + instruction->type = ARM_AND; + mnemonic = "AND"; + } + break; + case 1: + instruction->type = ARM_BIC; + mnemonic = "BIC"; + break; + case 2: + if (rn == 0xf) { + instruction->type = ARM_MOV; + mnemonic = "MOV"; + one = true; + suffix2 = ".W"; + } else { + instruction->type = ARM_ORR; + mnemonic = "ORR"; + } + break; + case 3: + if (rn == 0xf) { + instruction->type = ARM_MVN; + mnemonic = "MVN"; + one = true; + } else { + /* instruction->type = ARM_ORN; */ + mnemonic = "ORN"; + } + break; + case 4: + if (rd == 0xf) { + instruction->type = ARM_TEQ; + mnemonic = "TEQ"; + one = true; + suffix = ""; + rd = rn; + } else { + instruction->type = ARM_EOR; + mnemonic = "EOR"; + } + break; + case 8: + if (rd == 0xf) { + instruction->type = ARM_CMN; + mnemonic = "CMN"; + one = true; + suffix = ""; + rd = rn; + } else { + instruction->type = ARM_ADD; + mnemonic = "ADD"; + suffix2 = ".W"; + } + break; + case 10: + instruction->type = ARM_ADC; + mnemonic = "ADC"; suffix2 = ".W"; - } else { - instruction->type = ARM_ORR; - mnemonic = "ORR"; - } - break; - case 3: - if (rn == 0xf) { - instruction->type = ARM_MVN; - mnemonic = "MVN"; - one = true; - } else { - // instruction->type = ARM_ORN; - mnemonic = "ORN"; - } - break; - case 4: - if (rd == 0xf) { - instruction->type = ARM_TEQ; - mnemonic = "TEQ"; - one = true; - suffix = ""; - rd = rn; - } else { - instruction->type = ARM_EOR; - mnemonic = "EOR"; - } - break; - case 8: - if (rd == 0xf) { - instruction->type = ARM_CMN; - mnemonic = "CMN"; - one = true; - suffix = ""; - rd = rn; - } else { - instruction->type = ARM_ADD; - mnemonic = "ADD"; + break; + case 11: + instruction->type = ARM_SBC; + mnemonic = "SBC"; + break; + case 13: + if (rd == 0xf) { + instruction->type = ARM_CMP; + mnemonic = "CMP"; + one = true; + suffix = ""; + rd = rn; + } else { + instruction->type = ARM_SUB; + mnemonic = "SUB"; + } suffix2 = ".W"; - } - break; - case 10: - instruction->type = ARM_ADC; - mnemonic = "ADC"; - suffix2 = ".W"; - break; - case 11: - instruction->type = ARM_SBC; - mnemonic = "SBC"; - break; - case 13: - if (rd == 0xf) { - instruction->type = ARM_CMP; - mnemonic = "CMP"; - one = true; - suffix = ""; - rd = rn; - } else { - instruction->type = ARM_SUB; - mnemonic = "SUB"; - } - suffix2 = ".W"; - break; - case 14: - instruction->type = ARM_RSB; - mnemonic = "RSB"; - suffix2 = ".W"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + break; + case 14: + instruction->type = ARM_RSB; + mnemonic = "RSB"; + suffix2 = ".W"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (one) sprintf(cp, "%s%s\tr%d, #%d\t; %#8.8x", - mnemonic, suffix2 ,rd, immed, immed); + mnemonic, suffix2, rd, immed, immed); else sprintf(cp, "%s%s%s\tr%d, r%d, #%d\t; %#8.8x", mnemonic, suffix, suffix2, @@ -3214,7 +3234,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address, } static int t2ev_data_immed(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { char *mnemonic = NULL; int rn = (opcode >> 16) & 0xf; @@ -3228,67 +3248,67 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address, immed |= (1 << 11); switch ((opcode >> 20) & 0x1f) { - case 0: - if (rn == 0xf) { - add = true; - goto do_adr; - } - mnemonic = "ADDW"; - break; - case 4: - immed |= (opcode >> 4) & 0xf000; - sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed); - return ERROR_OK; - case 0x0a: - if (rn == 0xf) - goto do_adr; - mnemonic = "SUBW"; - break; - case 0x0c: - /* move constant to top 16 bits of register */ - immed |= (opcode >> 4) & 0xf000; - sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed); - return ERROR_OK; - case 0x10: - case 0x12: - is_signed = true; - case 0x18: - case 0x1a: - /* signed/unsigned saturated add */ - immed = (opcode >> 6) & 0x03; - immed |= (opcode >> 10) & 0x1c; - sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t", + case 0: + if (rn == 0xf) { + add = true; + goto do_adr; + } + mnemonic = "ADDW"; + break; + case 4: + immed |= (opcode >> 4) & 0xf000; + sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed); + return ERROR_OK; + case 0x0a: + if (rn == 0xf) + goto do_adr; + mnemonic = "SUBW"; + break; + case 0x0c: + /* move constant to top 16 bits of register */ + immed |= (opcode >> 4) & 0xf000; + sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed); + return ERROR_OK; + case 0x10: + case 0x12: + is_signed = true; + case 0x18: + case 0x1a: + /* signed/unsigned saturated add */ + immed = (opcode >> 6) & 0x03; + immed |= (opcode >> 10) & 0x1c; + sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t", is_signed ? "S" : "U", rd, (int) (opcode & 0x1f) + is_signed, rn, (opcode & (1 << 21)) ? "ASR" : "LSL", immed ? immed : 32); - return ERROR_OK; - case 0x14: - is_signed = true; + return ERROR_OK; + case 0x14: + is_signed = true; /* FALLTHROUGH */ - case 0x1c: - /* signed/unsigned bitfield extract */ - immed = (opcode >> 6) & 0x03; - immed |= (opcode >> 10) & 0x1c; - sprintf(cp, "%sBFX\tr%d, r%d, #%d, #%d\t", + case 0x1c: + /* signed/unsigned bitfield extract */ + immed = (opcode >> 6) & 0x03; + immed |= (opcode >> 10) & 0x1c; + sprintf(cp, "%sBFX\tr%d, r%d, #%d, #%d\t", is_signed ? "S" : "U", rd, rn, immed, (int) (opcode & 0x1f) + 1); - return ERROR_OK; - case 0x16: - immed = (opcode >> 6) & 0x03; - immed |= (opcode >> 10) & 0x1c; - if (rn == 0xf) /* bitfield clear */ - sprintf(cp, "BFC\tr%d, #%d, #%d\t", - rd, immed, - (int) (opcode & 0x1f) + 1 - immed); - else /* bitfield insert */ - sprintf(cp, "BFI\tr%d, r%d, #%d, #%d\t", - rd, rn, immed, - (int) (opcode & 0x1f) + 1 - immed); - return ERROR_OK; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_OK; + case 0x16: + immed = (opcode >> 6) & 0x03; + immed |= (opcode >> 10) & 0x1c; + if (rn == 0xf) /* bitfield clear */ + sprintf(cp, "BFC\tr%d, #%d, #%d\t", + rd, immed, + (int) (opcode & 0x1f) + 1 - immed); + else /* bitfield insert */ + sprintf(cp, "BFI\tr%d, r%d, #%d, #%d\t", + rd, rn, immed, + (int) (opcode & 0x1f) + 1 - immed); + return ERROR_OK; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } sprintf(cp, "%s\tr%d, r%d, #%d\t; %#3.3x", mnemonic, @@ -3309,7 +3329,7 @@ do_adr: } static int t2ev_store_single(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { unsigned op = (opcode >> 20) & 0xf; char *size = ""; @@ -3326,39 +3346,39 @@ static int t2ev_store_single(uint32_t opcode, uint32_t address, if (opcode & 0x0800) op |= 1; switch (op) { - /* byte */ - case 0x8: - case 0x9: - size = "B"; - goto imm12; - case 0x1: - size = "B"; - goto imm8; - case 0x0: - size = "B"; - break; - /* halfword */ - case 0xa: - case 0xb: - size = "H"; - goto imm12; - case 0x3: - size = "H"; - goto imm8; - case 0x2: - size = "H"; - break; - /* word */ - case 0xc: - case 0xd: - goto imm12; - case 0x5: - goto imm8; - case 0x4: - break; - /* error */ - default: - return ERROR_COMMAND_SYNTAX_ERROR; + /* byte */ + case 0x8: + case 0x9: + size = "B"; + goto imm12; + case 0x1: + size = "B"; + goto imm8; + case 0x0: + size = "B"; + break; + /* halfword */ + case 0xa: + case 0xb: + size = "H"; + goto imm12; + case 0x3: + size = "H"; + goto imm8; + case 0x2: + size = "H"; + break; + /* word */ + case 0xc: + case 0xd: + goto imm12; + case 0x5: + goto imm8; + case 0x4: + break; + /* error */ + default: + return ERROR_COMMAND_SYNTAX_ERROR; } sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]", @@ -3376,12 +3396,12 @@ imm8: immed = opcode & 0x00ff; switch (opcode & 0x700) { - case 0x600: - suffix = "T"; - break; - case 0x000: - case 0x200: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0x600: + suffix = "T"; + break; + case 0x000: + case 0x200: + return ERROR_COMMAND_SYNTAX_ERROR; } /* two indexed modes will write back rn */ @@ -3402,74 +3422,74 @@ imm8: } static int t2ev_mul32(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int ra = (opcode >> 12) & 0xf; switch (opcode & 0x007000f0) { - case 0: - if (ra == 0xf) - sprintf(cp, "MUL\tr%d, r%d, r%d", - (int) (opcode >> 8) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - else - sprintf(cp, "MLA\tr%d, r%d, r%d, r%d", + case 0: + if (ra == 0xf) + sprintf(cp, "MUL\tr%d, r%d, r%d", + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf); + else + sprintf(cp, "MLA\tr%d, r%d, r%d, r%d", + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, ra); + break; + case 0x10: + sprintf(cp, "MLS\tr%d, r%d, r%d, r%d", (int) (opcode >> 8) & 0xf, (int) (opcode >> 16) & 0xf, (int) (opcode >> 0) & 0xf, ra); - break; - case 0x10: - sprintf(cp, "MLS\tr%d, r%d, r%d, r%d", - (int) (opcode >> 8) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, ra); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return ERROR_OK; } static int t2ev_mul64_div(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int op = (opcode >> 4) & 0xf; char *infix = "MUL"; op += (opcode >> 16) & 0x70; switch (op) { - case 0x40: - case 0x60: - infix = "MLA"; + case 0x40: + case 0x60: + infix = "MLA"; /* FALLTHROUGH */ - case 0: - case 0x20: - sprintf(cp, "%c%sL\tr%d, r%d, r%d, r%d", + case 0: + case 0x20: + sprintf(cp, "%c%sL\tr%d, r%d, r%d, r%d", (op & 0x20) ? 'U' : 'S', infix, (int) (opcode >> 12) & 0xf, (int) (opcode >> 8) & 0xf, (int) (opcode >> 16) & 0xf, (int) (opcode >> 0) & 0xf); - break; - case 0x1f: - case 0x3f: - sprintf(cp, "%cDIV\tr%d, r%d, r%d", + break; + case 0x1f: + case 0x3f: + sprintf(cp, "%cDIV\tr%d, r%d, r%d", (op & 0x20) ? 'U' : 'S', (int) (opcode >> 8) & 0xf, (int) (opcode >> 16) & 0xf, (int) (opcode >> 0) & 0xf); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return ERROR_OK; } static int t2ev_ldm_stm(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int rn = (opcode >> 16) & 0xf; int op = (opcode >> 22) & 0x6; @@ -3481,42 +3501,42 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address, op |= 1; switch (op) { - case 0: - mode = "DB"; + case 0: + mode = "DB"; /* FALL THROUGH */ - case 6: - sprintf(cp, "SRS%s\tsp%s, #%d", mode, + case 6: + sprintf(cp, "SRS%s\tsp%s, #%d", mode, t ? "!" : "", (unsigned) (opcode & 0x1f)); - return ERROR_OK; - case 1: - mode = "DB"; + return ERROR_OK; + case 1: + mode = "DB"; /* FALL THROUGH */ - case 7: - sprintf(cp, "RFE%s\tr%d%s", mode, + case 7: + sprintf(cp, "RFE%s\tr%d%s", mode, (unsigned) ((opcode >> 16) & 0xf), t ? "!" : ""); - return ERROR_OK; - case 2: - sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : ""); - break; - case 3: - if (rn == 13 && t) - sprintf(cp, "POP.W\t"); - else - sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : ""); - break; - case 4: - if (rn == 13 && t) - sprintf(cp, "PUSH.W\t"); - else - sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : ""); - break; - case 5: - sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : ""); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + return ERROR_OK; + case 2: + sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : ""); + break; + case 3: + if (rn == 13 && t) + sprintf(cp, "POP.W\t"); + else + sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : ""); + break; + case 4: + if (rn == 13 && t) + sprintf(cp, "PUSH.W\t"); + else + sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : ""); + break; + case 5: + sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : ""); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } cp = strchr(cp, 0); @@ -3536,7 +3556,7 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address, /* load/store dual or exclusive, table branch */ static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { unsigned op1op2 = (opcode >> 20) & 0x3; unsigned op3 = (opcode >> 4) & 0xf; @@ -3550,64 +3570,64 @@ static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address, op1op2 |= (opcode >> 21) & 0xc; switch (op1op2) { - case 0: - mnemonic = "STREX"; - goto strex; - case 1: - mnemonic = "LDREX"; - goto ldrex; - case 2: - case 6: - case 8: - case 10: - case 12: - case 14: - mnemonic = "STRD"; - goto immediate; - case 3: - case 7: - case 9: - case 11: - case 13: - case 15: - mnemonic = "LDRD"; - if (rn == 15) - goto literal; - else - goto immediate; - case 4: - switch (op3) { - case 4: - mnemonic = "STREXB"; - break; - case 5: - mnemonic = "STREXH"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } - rd = opcode & 0xf; - imm = 0; - goto strex; - case 5: - switch (op3) { case 0: - sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf); - return ERROR_OK; + mnemonic = "STREX"; + goto strex; case 1: - sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf); - return ERROR_OK; + mnemonic = "LDREX"; + goto ldrex; + case 2: + case 6: + case 8: + case 10: + case 12: + case 14: + mnemonic = "STRD"; + goto immediate; + case 3: + case 7: + case 9: + case 11: + case 13: + case 15: + mnemonic = "LDRD"; + if (rn == 15) + goto literal; + else + goto immediate; case 4: - mnemonic = "LDREXB"; - break; + switch (op3) { + case 4: + mnemonic = "STREXB"; + break; + case 5: + mnemonic = "STREXH"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + rd = opcode & 0xf; + imm = 0; + goto strex; case 5: - mnemonic = "LDREXH"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } - imm = 0; - goto ldrex; + switch (op3) { + case 0: + sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf); + return ERROR_OK; + case 1: + sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf); + return ERROR_OK; + case 4: + mnemonic = "LDREXB"; + break; + case 5: + mnemonic = "LDREXH"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + imm = 0; + goto ldrex; } return ERROR_COMMAND_SYNTAX_ERROR; @@ -3662,7 +3682,7 @@ literal: } static int t2ev_data_shift(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int op = (opcode >> 21) & 0xf; int rd = (opcode >> 8) & 0xf; @@ -3677,187 +3697,187 @@ static int t2ev_data_shift(uint32_t opcode, uint32_t address, suffix = "S"; switch (op) { - case 0: - if (rd == 0xf) { - if (!(opcode & (1 << 20))) - return ERROR_COMMAND_SYNTAX_ERROR; - instruction->type = ARM_TST; - mnemonic = "TST"; - suffix = ""; - goto two; - } - instruction->type = ARM_AND; - mnemonic = "AND"; - break; - case 1: - instruction->type = ARM_BIC; - mnemonic = "BIC"; - break; - case 2: - if (rn == 0xf) { - instruction->type = ARM_MOV; - switch (type) { - case 0: - if (immed == 0) { - sprintf(cp, "MOV%s.W\tr%d, r%d", - suffix, rd, - (int) (opcode & 0xf)); - return ERROR_OK; - } - mnemonic = "LSL"; - break; - case 1: - mnemonic = "LSR"; - break; - case 2: - mnemonic = "ASR"; - break; - default: - if (immed == 0) { - sprintf(cp, "RRX%s\tr%d, r%d", - suffix, rd, - (int) (opcode & 0xf)); - return ERROR_OK; + case 0: + if (rd == 0xf) { + if (!(opcode & (1 << 20))) + return ERROR_COMMAND_SYNTAX_ERROR; + instruction->type = ARM_TST; + mnemonic = "TST"; + suffix = ""; + goto two; + } + instruction->type = ARM_AND; + mnemonic = "AND"; + break; + case 1: + instruction->type = ARM_BIC; + mnemonic = "BIC"; + break; + case 2: + if (rn == 0xf) { + instruction->type = ARM_MOV; + switch (type) { + case 0: + if (immed == 0) { + sprintf(cp, "MOV%s.W\tr%d, r%d", + suffix, rd, + (int) (opcode & 0xf)); + return ERROR_OK; + } + mnemonic = "LSL"; + break; + case 1: + mnemonic = "LSR"; + break; + case 2: + mnemonic = "ASR"; + break; + default: + if (immed == 0) { + sprintf(cp, "RRX%s\tr%d, r%d", + suffix, rd, + (int) (opcode & 0xf)); + return ERROR_OK; + } + mnemonic = "ROR"; + break; } - mnemonic = "ROR"; - break; + goto immediate; + } else { + instruction->type = ARM_ORR; + mnemonic = "ORR"; } - goto immediate; - } else { - instruction->type = ARM_ORR; - mnemonic = "ORR"; - } - break; - case 3: - if (rn == 0xf) { - instruction->type = ARM_MVN; - mnemonic = "MVN"; - rn = rd; - goto two; - } else { - // instruction->type = ARM_ORN; - mnemonic = "ORN"; - } - break; - case 4: - if (rd == 0xf) { - if (!(opcode & (1 << 20))) - return ERROR_COMMAND_SYNTAX_ERROR; - instruction->type = ARM_TEQ; - mnemonic = "TEQ"; - suffix = ""; - goto two; - } - instruction->type = ARM_EOR; - mnemonic = "EOR"; - break; - case 8: - if (rd == 0xf) { - if (!(opcode & (1 << 20))) - return ERROR_COMMAND_SYNTAX_ERROR; - instruction->type = ARM_CMN; - mnemonic = "CMN"; - suffix = ""; - goto two; - } - instruction->type = ARM_ADD; - mnemonic = "ADD"; - break; - case 0xa: - instruction->type = ARM_ADC; - mnemonic = "ADC"; - break; - case 0xb: - instruction->type = ARM_SBC; - mnemonic = "SBC"; - break; - case 0xd: - if (rd == 0xf) { - if (!(opcode & (1 << 21))) - return ERROR_COMMAND_SYNTAX_ERROR; - instruction->type = ARM_CMP; - mnemonic = "CMP"; - suffix = ""; - goto two; - } - instruction->type = ARM_SUB; - mnemonic = "SUB"; - break; - case 0xe: - instruction->type = ARM_RSB; - mnemonic = "RSB"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + break; + case 3: + if (rn == 0xf) { + instruction->type = ARM_MVN; + mnemonic = "MVN"; + rn = rd; + goto two; + } else { + /* instruction->type = ARM_ORN; */ + mnemonic = "ORN"; + } + break; + case 4: + if (rd == 0xf) { + if (!(opcode & (1 << 20))) + return ERROR_COMMAND_SYNTAX_ERROR; + instruction->type = ARM_TEQ; + mnemonic = "TEQ"; + suffix = ""; + goto two; + } + instruction->type = ARM_EOR; + mnemonic = "EOR"; + break; + case 8: + if (rd == 0xf) { + if (!(opcode & (1 << 20))) + return ERROR_COMMAND_SYNTAX_ERROR; + instruction->type = ARM_CMN; + mnemonic = "CMN"; + suffix = ""; + goto two; + } + instruction->type = ARM_ADD; + mnemonic = "ADD"; + break; + case 0xa: + instruction->type = ARM_ADC; + mnemonic = "ADC"; + break; + case 0xb: + instruction->type = ARM_SBC; + mnemonic = "SBC"; + break; + case 0xd: + if (rd == 0xf) { + if (!(opcode & (1 << 21))) + return ERROR_COMMAND_SYNTAX_ERROR; + instruction->type = ARM_CMP; + mnemonic = "CMP"; + suffix = ""; + goto two; + } + instruction->type = ARM_SUB; + mnemonic = "SUB"; + break; + case 0xe: + instruction->type = ARM_RSB; + mnemonic = "RSB"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } sprintf(cp, "%s%s.W\tr%d, r%d, r%d", - mnemonic, suffix, rd, rn, (int) (opcode & 0xf)); + mnemonic, suffix, rd, rn, (int) (opcode & 0xf)); shift: cp = strchr(cp, 0); switch (type) { - case 0: - if (immed == 0) - return ERROR_OK; - suffix = "LSL"; - break; - case 1: - suffix = "LSR"; - if (immed == 32) - immed = 0; - break; - case 2: - suffix = "ASR"; - if (immed == 32) - immed = 0; - break; - case 3: - if (immed == 0) { - strcpy(cp, ", RRX"); - return ERROR_OK; - } - suffix = "ROR"; - break; + case 0: + if (immed == 0) + return ERROR_OK; + suffix = "LSL"; + break; + case 1: + suffix = "LSR"; + if (immed == 32) + immed = 0; + break; + case 2: + suffix = "ASR"; + if (immed == 32) + immed = 0; + break; + case 3: + if (immed == 0) { + strcpy(cp, ", RRX"); + return ERROR_OK; + } + suffix = "ROR"; + break; } sprintf(cp, ", %s #%d", suffix, immed ? immed : 32); return ERROR_OK; two: sprintf(cp, "%s%s.W\tr%d, r%d", - mnemonic, suffix, rn, (int) (opcode & 0xf)); + mnemonic, suffix, rn, (int) (opcode & 0xf)); goto shift; immediate: sprintf(cp, "%s%s.W\tr%d, r%d, #%d", - mnemonic, suffix, rd, - (int) (opcode & 0xf), immed ? immed : 32); + mnemonic, suffix, rd, + (int) (opcode & 0xf), immed ? immed : 32); return ERROR_OK; } static int t2ev_data_reg(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { char *mnemonic; - char * suffix = ""; + char *suffix = ""; if (((opcode >> 4) & 0xf) == 0) { switch ((opcode >> 21) & 0x7) { - case 0: - mnemonic = "LSL"; - break; - case 1: - mnemonic = "LSR"; - break; - case 2: - mnemonic = "ASR"; - break; - case 3: - mnemonic = "ROR"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + mnemonic = "LSL"; + break; + case 1: + mnemonic = "LSR"; + break; + case 2: + mnemonic = "ASR"; + break; + case 3: + mnemonic = "ROR"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } instruction->type = ARM_MOV; @@ -3871,66 +3891,66 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address, } else if (opcode & (1 << 7)) { switch ((opcode >> 20) & 0xf) { - case 0: - case 1: - case 4: - case 5: - switch ((opcode >> 4) & 0x3) { + case 0: case 1: - suffix = ", ROR #8"; - break; - case 2: - suffix = ", ROR #16"; - break; - case 3: - suffix = ", ROR #24"; - break; - } - sprintf(cp, "%cXT%c.W\tr%d, r%d%s", + case 4: + case 5: + switch ((opcode >> 4) & 0x3) { + case 1: + suffix = ", ROR #8"; + break; + case 2: + suffix = ", ROR #16"; + break; + case 3: + suffix = ", ROR #24"; + break; + } + sprintf(cp, "%cXT%c.W\tr%d, r%d%s", (opcode & (1 << 24)) ? 'U' : 'S', (opcode & (1 << 26)) ? 'B' : 'H', (int) (opcode >> 8) & 0xf, (int) (opcode >> 0) & 0xf, suffix); - break; - case 8: - case 9: - case 0xa: - case 0xb: - if (opcode & (1 << 6)) - return ERROR_COMMAND_SYNTAX_ERROR; - if (((opcode >> 12) & 0xf) != 0xf) - return ERROR_COMMAND_SYNTAX_ERROR; - if (!(opcode & (1 << 20))) - return ERROR_COMMAND_SYNTAX_ERROR; - - switch (((opcode >> 19) & 0x04) - | ((opcode >> 4) & 0x3)) { - case 0: - mnemonic = "REV.W"; - break; - case 1: - mnemonic = "REV16.W"; - break; - case 2: - mnemonic = "RBIT"; break; - case 3: - mnemonic = "REVSH.W"; - break; - case 4: - mnemonic = "CLZ"; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; - } - sprintf(cp, "%s\tr%d, r%d", + case 8: + case 9: + case 0xa: + case 0xb: + if (opcode & (1 << 6)) + return ERROR_COMMAND_SYNTAX_ERROR; + if (((opcode >> 12) & 0xf) != 0xf) + return ERROR_COMMAND_SYNTAX_ERROR; + if (!(opcode & (1 << 20))) + return ERROR_COMMAND_SYNTAX_ERROR; + + switch (((opcode >> 19) & 0x04) + | ((opcode >> 4) & 0x3)) { + case 0: + mnemonic = "REV.W"; + break; + case 1: + mnemonic = "REV16.W"; + break; + case 2: + mnemonic = "RBIT"; + break; + case 3: + mnemonic = "REVSH.W"; + break; + case 4: + mnemonic = "CLZ"; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + sprintf(cp, "%s\tr%d, r%d", mnemonic, (int) (opcode >> 8) & 0xf, (int) (opcode >> 0) & 0xf); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } } @@ -3938,7 +3958,7 @@ static int t2ev_data_reg(uint32_t opcode, uint32_t address, } static int t2ev_load_word(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int rn = (opcode >> 16) & 0xf; int immed; @@ -4012,7 +4032,7 @@ static int t2ev_load_word(uint32_t opcode, uint32_t address, } static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int rn = (opcode >> 16) & 0xf; int rt = (opcode >> 12) & 0xf; @@ -4022,176 +4042,176 @@ static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address, char *mnemonic; switch ((opcode >> 23) & 0x3) { - case 0: - if ((rn & rt) == 0xf) { + case 0: + if ((rn & rt) == 0xf) { pld_literal: - immed = opcode & 0xfff; - address = thumb_alignpc4(address); - if (opcode & (1 << 23)) - address += immed; - else - address -= immed; - sprintf(cp, "PLD\tr%d, %#8.8" PRIx32, - rt, address); - return ERROR_OK; - } - if (rn == 0x0f && rt != 0x0f) { + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "PLD\tr%d, %#8.8" PRIx32, + rt, address); + return ERROR_OK; + } + if (rn == 0x0f && rt != 0x0f) { ldrb_literal: - immed = opcode & 0xfff; - address = thumb_alignpc4(address); - if (opcode & (1 << 23)) - address += immed; - else - address -= immed; - sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32, - rt, address); - return ERROR_OK; - } - if (rn == 0x0f) - break; - if ((op2 & 0x3c) == 0x38) { - immed = opcode & 0xff; - sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x", - rt, rn, immed, immed); - return ERROR_OK; - } - if ((op2 & 0x3c) == 0x30) { - if (rt == 0x0f) { + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32, + rt, address); + return ERROR_OK; + } + if (rn == 0x0f) + break; + if ((op2 & 0x3c) == 0x38) { immed = opcode & 0xff; - immed = -immed; -preload_immediate: - p1 = (opcode & (1 << 21)) ? "W" : ""; - sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x", - p1, rn, immed, immed); + sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x", + rt, rn, immed, immed); return ERROR_OK; } - mnemonic = "LDRB"; + if ((op2 & 0x3c) == 0x30) { + if (rt == 0x0f) { + immed = opcode & 0xff; + immed = -immed; +preload_immediate: + p1 = (opcode & (1 << 21)) ? "W" : ""; + sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x", + p1, rn, immed, immed); + return ERROR_OK; + } + mnemonic = "LDRB"; ldrxb_immediate_t3: - immed = opcode & 0xff; - if (!(opcode & 0x200)) - immed = -immed; - - /* two indexed modes will write back rn */ - if (opcode & 0x100) { - if (opcode & 0x400) /* pre-indexed */ - p2 = "]!"; - else { /* post-indexed */ - p1 = "]"; - p2 = ""; + immed = opcode & 0xff; + if (!(opcode & 0x200)) + immed = -immed; + + /* two indexed modes will write back rn */ + if (opcode & 0x100) { + if (opcode & 0x400) /* pre-indexed */ + p2 = "]!"; + else { /* post-indexed */ + p1 = "]"; + p2 = ""; + } } - } ldrxb_immediate_t2: - sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x", - mnemonic, rt, rn, p1, - immed, p2, immed); - return ERROR_OK; - } - if ((op2 & 0x24) == 0x24) { - mnemonic = "LDRB"; - goto ldrxb_immediate_t3; - } - if (op2 == 0) { - int rm = opcode & 0xf; + sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x", + mnemonic, rt, rn, p1, + immed, p2, immed); + return ERROR_OK; + } + if ((op2 & 0x24) == 0x24) { + mnemonic = "LDRB"; + goto ldrxb_immediate_t3; + } + if (op2 == 0) { + int rm = opcode & 0xf; - if (rt == 0x0f) - sprintf(cp, "PLD\t"); - else - sprintf(cp, "LDRB.W\tr%d, ", rt); - immed = (opcode >> 4) & 0x3; - cp = strchr(cp, 0); - sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed); - return ERROR_OK; - } - break; - case 1: - if ((rn & rt) == 0xf) - goto pld_literal; - if (rt == 0xf) { - immed = opcode & 0xfff; - goto preload_immediate; - } - if (rn == 0x0f) - goto ldrb_literal; - mnemonic = "LDRB.W"; - immed = opcode & 0xfff; - goto ldrxb_immediate_t2; - case 2: - if ((rn & rt) == 0xf) { - immed = opcode & 0xfff; - address = thumb_alignpc4(address); - if (opcode & (1 << 23)) - address += immed; - else - address -= immed; - sprintf(cp, "PLI\t%#8.8" PRIx32, address); - return ERROR_OK; - } - if (rn == 0xf && rt != 0xf) { -ldrsb_literal: - immed = opcode & 0xfff; - address = thumb_alignpc4(address); - if (opcode & (1 << 23)) - address += immed; - else - address -= immed; - sprintf(cp, "LDRSB\t%#8.8" PRIx32, address); - return ERROR_OK; - } - if (rn == 0xf) + if (rt == 0x0f) + sprintf(cp, "PLD\t"); + else + sprintf(cp, "LDRB.W\tr%d, ", rt); + immed = (opcode >> 4) & 0x3; + cp = strchr(cp, 0); + sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed); + return ERROR_OK; + } break; - if ((op2 & 0x3c) == 0x38) { - immed = opcode & 0xff; - sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x", - rt, rn, immed, immed); - return ERROR_OK; - } - if ((op2 & 0x3c) == 0x30) { + case 1: + if ((rn & rt) == 0xf) + goto pld_literal; if (rt == 0xf) { + immed = opcode & 0xfff; + goto preload_immediate; + } + if (rn == 0x0f) + goto ldrb_literal; + mnemonic = "LDRB.W"; + immed = opcode & 0xfff; + goto ldrxb_immediate_t2; + case 2: + if ((rn & rt) == 0xf) { + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "PLI\t%#8.8" PRIx32, address); + return ERROR_OK; + } + if (rn == 0xf && rt != 0xf) { +ldrsb_literal: + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "LDRSB\t%#8.8" PRIx32, address); + return ERROR_OK; + } + if (rn == 0xf) + break; + if ((op2 & 0x3c) == 0x38) { immed = opcode & 0xff; - immed = -immed; // pli - sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x", - rn, immed, -immed); + sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x", + rt, rn, immed, immed); return ERROR_OK; } - mnemonic = "LDRSB"; - goto ldrxb_immediate_t3; - } - if ((op2 & 0x24) == 0x24) { - mnemonic = "LDRSB"; - goto ldrxb_immediate_t3; - } - if (op2 == 0) { - int rm = opcode & 0xf; + if ((op2 & 0x3c) == 0x30) { + if (rt == 0xf) { + immed = opcode & 0xff; + immed = -immed; /* pli */ + sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x", + rn, immed, -immed); + return ERROR_OK; + } + mnemonic = "LDRSB"; + goto ldrxb_immediate_t3; + } + if ((op2 & 0x24) == 0x24) { + mnemonic = "LDRSB"; + goto ldrxb_immediate_t3; + } + if (op2 == 0) { + int rm = opcode & 0xf; - if (rt == 0x0f) - sprintf(cp, "PLI\t"); - else - sprintf(cp, "LDRSB.W\tr%d, ", rt); - immed = (opcode >> 4) & 0x3; - cp = strchr(cp, 0); - sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed); - return ERROR_OK; - } - break; - case 3: - if (rt == 0xf) { + if (rt == 0x0f) + sprintf(cp, "PLI\t"); + else + sprintf(cp, "LDRSB.W\tr%d, ", rt); + immed = (opcode >> 4) & 0x3; + cp = strchr(cp, 0); + sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed); + return ERROR_OK; + } + break; + case 3: + if (rt == 0xf) { + immed = opcode & 0xfff; + sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x", + rn, immed, immed); + return ERROR_OK; + } + if (rn == 0xf) + goto ldrsb_literal; immed = opcode & 0xfff; - sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x", - rn, immed, immed); - return ERROR_OK; - } - if (rn == 0xf) - goto ldrsb_literal; - immed = opcode & 0xfff; - mnemonic = "LDRSB"; - goto ldrxb_immediate_t2; + mnemonic = "LDRSB"; + goto ldrxb_immediate_t2; } return ERROR_COMMAND_SYNTAX_ERROR; } static int t2ev_load_halfword(uint32_t opcode, uint32_t address, - struct arm_instruction *instruction, char *cp) + struct arm_instruction *instruction, char *cp) { int rn = (opcode >> 16) & 0xf; int rt = (opcode >> 12) & 0xf; @@ -4292,21 +4312,21 @@ int thumb2_opcode(struct target *target, uint32_t address, struct arm_instructio return retval; switch (op & 0xf800) { - case 0xf800: - case 0xf000: - case 0xe800: - /* 32-bit instructions */ - instruction->instruction_size = 4; - opcode = op << 16; - retval = target_read_u16(target, address + 2, &op); - if (retval != ERROR_OK) - return retval; - opcode |= op; - instruction->opcode = opcode; - break; - default: - /* 16-bit: Thumb1 + IT + CBZ/CBNZ + ... */ - return thumb_evaluate_opcode(op, address, instruction); + case 0xf800: + case 0xf000: + case 0xe800: + /* 32-bit instructions */ + instruction->instruction_size = 4; + opcode = op << 16; + retval = target_read_u16(target, address + 2, &op); + if (retval != ERROR_OK) + return retval; + opcode |= op; + instruction->opcode = opcode; + break; + default: + /* 16-bit: Thumb1 + IT + CBZ/CBNZ + ... */ + return thumb_evaluate_opcode(op, address, instruction); } snprintf(instruction->text, 128, @@ -4356,7 +4376,7 @@ int thumb2_opcode(struct target *target, uint32_t address, struct arm_instructio retval = t2ev_data_shift(opcode, address, instruction, cp); /* ARMv7-M: A5.3.12 Data processing (register) - * and A5.3.13 Miscellaneous operations + * and A5.3.13 Miscellaneous operations */ else if ((opcode & 0x1f000000) == 0x1a000000) retval = t2ev_data_reg(opcode, address, instruction, cp); @@ -4393,34 +4413,26 @@ int thumb2_opcode(struct target *target, uint32_t address, struct arm_instructio int arm_access_size(struct arm_instruction *instruction) { if ((instruction->type == ARM_LDRB) - || (instruction->type == ARM_LDRBT) - || (instruction->type == ARM_LDRSB) - || (instruction->type == ARM_STRB) - || (instruction->type == ARM_STRBT)) - { + || (instruction->type == ARM_LDRBT) + || (instruction->type == ARM_LDRSB) + || (instruction->type == ARM_STRB) + || (instruction->type == ARM_STRBT)) return 1; - } else if ((instruction->type == ARM_LDRH) - || (instruction->type == ARM_LDRSH) - || (instruction->type == ARM_STRH)) - { + || (instruction->type == ARM_LDRSH) + || (instruction->type == ARM_STRH)) return 2; - } else if ((instruction->type == ARM_LDR) - || (instruction->type == ARM_LDRT) - || (instruction->type == ARM_STR) - || (instruction->type == ARM_STRT)) - { + || (instruction->type == ARM_LDRT) + || (instruction->type == ARM_STR) + || (instruction->type == ARM_STRT)) return 4; - } else if ((instruction->type == ARM_LDRD) - || (instruction->type == ARM_STRD)) - { + || (instruction->type == ARM_STRD)) return 8; - } - else - { - LOG_ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type); + else { + LOG_ERROR("BUG: instruction type %i isn't a load/store instruction", + instruction->type); return 0; } } diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index 156c037..bdfdb03 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -17,13 +17,13 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM_DISASSEMBLER_H #define ARM_DISASSEMBLER_H #include <helper/types.h> -enum arm_instruction_type -{ +enum arm_instruction_type { ARM_UNKNOWN_INSTUCTION, /* Branch instructions */ @@ -120,14 +120,12 @@ enum arm_instruction_type ARM_UNDEFINED_INSTRUCTION = 0xffffffff, }; -struct arm_b_bl_bx_blx_instr -{ +struct arm_b_bl_bx_blx_instr { int reg_operand; uint32_t target_address; }; -union arm_shifter_operand -{ +union arm_shifter_operand { struct { uint32_t immediate; } immediate; @@ -143,8 +141,7 @@ union arm_shifter_operand } register_shift; }; -struct arm_data_proc_instr -{ +struct arm_data_proc_instr { int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */ uint8_t S; uint8_t Rn; @@ -152,15 +149,13 @@ struct arm_data_proc_instr union arm_shifter_operand shifter_operand; }; -struct arm_load_store_instr -{ +struct arm_load_store_instr { uint8_t Rd; uint8_t Rn; uint8_t U; int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */ int offset_mode; /* 0: immediate, 1: (scaled) register */ - union - { + union { uint32_t offset; struct { uint8_t Rm; @@ -170,8 +165,7 @@ struct arm_load_store_instr } offset; }; -struct arm_load_store_multiple_instr -{ +struct arm_load_store_multiple_instr { uint8_t Rn; uint32_t register_list; uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */ @@ -179,8 +173,7 @@ struct arm_load_store_multiple_instr uint8_t W; }; -struct arm_instruction -{ +struct arm_instruction { enum arm_instruction_type type; char text[128]; uint32_t opcode; diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 9f7af4e..b83d17a 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -51,8 +51,8 @@ /* Read coprocessor */ static int dpm_mrc(struct target *target, int cpnum, - uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, - uint32_t *value) + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t *value) { struct arm *arm = target_to_arm(target); struct arm_dpm *dpm = arm->dpm; @@ -63,8 +63,8 @@ static int dpm_mrc(struct target *target, int cpnum, return retval; LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, - (int) op1, (int) CRn, - (int) CRm, (int) op2); + (int) op1, (int) CRn, + (int) CRm, (int) op2); /* read coprocessor register into R0; return via DCC */ retval = dpm->instr_read_data_r0(dpm, @@ -76,8 +76,8 @@ static int dpm_mrc(struct target *target, int cpnum, } static int dpm_mcr(struct target *target, int cpnum, - uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, - uint32_t value) + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t value) { struct arm *arm = target_to_arm(target); struct arm_dpm *dpm = arm->dpm; @@ -88,8 +88,8 @@ static int dpm_mcr(struct target *target, int cpnum, return retval; LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, - (int) op1, (int) CRn, - (int) CRm, (int) op2); + (int) op1, (int) CRn, + (int) CRm, (int) op2); /* read DCC into r0; then write coprocessor register from R0 */ retval = dpm->instr_write_data_r0(dpm, @@ -139,44 +139,44 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) int retval; switch (regnum) { - case 0 ... 14: - /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ - retval = dpm->instr_read_data_dcc(dpm, + case 0 ... 14: + /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ + retval = dpm->instr_read_data_dcc(dpm, ARMV4_5_MCR(14, 0, regnum, 0, 5, 0), &value); - break; - case 15: /* PC */ - /* "MOV r0, pc"; then return via DCC */ - retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value); - - /* NOTE: this seems like a slightly awkward place to update - * this value ... but if the PC gets written (the only way - * to change what we compute), the arch spec says subsequent - * reads return values which are "unpredictable". So this - * is always right except in those broken-by-intent cases. - */ - switch (dpm->arm->core_state) { - case ARM_STATE_ARM: - value -= 8; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - value -= 4; break; - case ARM_STATE_JAZELLE: - /* core-specific ... ? */ - LOG_WARNING("Jazelle PC adjustment unknown"); + case 15:/* PC + * "MOV r0, pc"; then return via DCC */ + retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value); + + /* NOTE: this seems like a slightly awkward place to update + * this value ... but if the PC gets written (the only way + * to change what we compute), the arch spec says subsequent + * reads return values which are "unpredictable". So this + * is always right except in those broken-by-intent cases. + */ + switch (dpm->arm->core_state) { + case ARM_STATE_ARM: + value -= 8; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + value -= 4; + break; + case ARM_STATE_JAZELLE: + /* core-specific ... ? */ + LOG_WARNING("Jazelle PC adjustment unknown"); + break; + } break; - } - break; - default: - /* 16: "MRS r0, CPSR"; then return via DCC - * 17: "MRS r0, SPSR"; then return via DCC - */ - retval = dpm->instr_read_data_r0(dpm, + default: + /* 16: "MRS r0, CPSR"; then return via DCC + * 17: "MRS r0, SPSR"; then return via DCC + */ + retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, regnum & 1), &value); - break; + break; } if (retval == ERROR_OK) { @@ -196,30 +196,30 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) uint32_t value = buf_get_u32(r->value, 0, 32); switch (regnum) { - case 0 ... 14: - /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */ - retval = dpm->instr_write_data_dcc(dpm, + case 0 ... 14: + /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */ + retval = dpm->instr_write_data_dcc(dpm, ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value); - break; - case 15: /* PC */ - /* read r0 from DCC; then "MOV pc, r0" */ - retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value); - break; - default: - /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf" - * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf" - */ - retval = dpm->instr_write_data_r0(dpm, + break; + case 15:/* PC + * read r0 from DCC; then "MOV pc, r0" */ + retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value); + break; + default: + /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf" + * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf" + */ + retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, regnum & 1), value); - if (retval != ERROR_OK) - return retval; + if (retval != ERROR_OK) + return retval; - if (regnum == 16 && dpm->instr_cpsr_sync) - retval = dpm->instr_cpsr_sync(dpm); + if (regnum == 16 && dpm->instr_cpsr_sync) + retval = dpm->instr_cpsr_sync(dpm); - break; + break; } if (retval == ERROR_OK) { @@ -292,7 +292,7 @@ fail: * or running debugger code. */ static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp, - struct dpm_bpwp *xp, int *set_p) + struct dpm_bpwp *xp, int *set_p) { int retval = ERROR_OK; bool disable; @@ -325,10 +325,10 @@ static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp, if (retval != ERROR_OK) LOG_ERROR("%s: can't %s HW %spoint %d", - disable ? "disable" : "enable", - target_name(dpm->arm->target), - (xp->number < 16) ? "break" : "watch", - xp->number & 0xf); + disable ? "disable" : "enable", + target_name(dpm->arm->target), + (xp->number < 16) ? "break" : "watch", + xp->number & 0xf); done: return retval; } @@ -423,25 +423,24 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) /* cope with special cases */ switch (regnum) { - case 8 ... 12: - /* r8..r12 "anything but FIQ" case; - * we "know" core mode is accurate - * since we haven't changed it yet - */ - if (arm->core_mode == ARM_MODE_FIQ + case 8 ... 12: + /* r8..r12 "anything but FIQ" case; + * we "know" core mode is accurate + * since we haven't changed it yet + */ + if (arm->core_mode == ARM_MODE_FIQ && ARM_MODE_ANY - != mode) - tmode = ARM_MODE_USR; - break; - case 16: - /* SPSR */ - regnum++; - break; + != mode) + tmode = ARM_MODE_USR; + break; + case 16: + /* SPSR */ + regnum++; + break; } /* REVISIT error checks */ - if (tmode != ARM_MODE_ANY) - { + if (tmode != ARM_MODE_ANY) { retval = dpm_modeswitch(dpm, tmode); if (retval != ERROR_OK) goto done; @@ -490,34 +489,34 @@ done: * or MODE_ANY. */ static enum arm_mode dpm_mapmode(struct arm *arm, - unsigned num, enum arm_mode mode) + unsigned num, enum arm_mode mode) { enum arm_mode amode = arm->core_mode; /* don't switch if the mode is already correct */ if (amode == ARM_MODE_SYS) - amode = ARM_MODE_USR; + amode = ARM_MODE_USR; if (mode == amode) return ARM_MODE_ANY; switch (num) { - /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */ - case 0 ... 7: - case 15: - case 16: - break; - /* r8..r12 aren't shadowed for anything except FIQ */ - case 8 ... 12: - if (mode == ARM_MODE_FIQ) + /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */ + case 0 ... 7: + case 15: + case 16: + break; + /* r8..r12 aren't shadowed for anything except FIQ */ + case 8 ... 12: + if (mode == ARM_MODE_FIQ) + return mode; + break; + /* r13/sp, and r14/lr are always shadowed */ + case 13: + case 14: return mode; - break; - /* r13/sp, and r14/lr are always shadowed */ - case 13: - case 14: - return mode; - default: - LOG_WARNING("invalid register #%u", num); - break; + default: + LOG_WARNING("invalid register #%u", num); + break; } return ARM_MODE_ANY; } @@ -530,7 +529,7 @@ static enum arm_mode dpm_mapmode(struct arm *arm, */ static int arm_dpm_read_core_reg(struct target *target, struct reg *r, - int regnum, enum arm_mode mode) + int regnum, enum arm_mode mode) { struct arm_dpm *dpm = target_to_arm(target)->dpm; int retval; @@ -572,7 +571,7 @@ fail: } static int arm_dpm_write_core_reg(struct target *target, struct reg *r, - int regnum, enum arm_mode mode, uint32_t value) + int regnum, enum arm_mode mode, uint32_t value) { struct arm_dpm *dpm = target_to_arm(target)->dpm; int retval; @@ -693,7 +692,7 @@ done: */ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, - uint32_t addr, uint32_t length) + uint32_t addr, uint32_t length) { uint32_t control; @@ -710,26 +709,26 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, * v7 hardware, unaligned 4-byte ones too. */ switch (length) { - case 1: - control |= (1 << (addr & 3)) << 5; - break; - case 2: - /* require 2-byte alignment */ - if (!(addr & 1)) { - control |= (3 << (addr & 2)) << 5; + case 1: + control |= (1 << (addr & 3)) << 5; break; - } + case 2: + /* require 2-byte alignment */ + if (!(addr & 1)) { + control |= (3 << (addr & 2)) << 5; + break; + } /* FALL THROUGH */ - case 4: - /* require 4-byte alignment */ - if (!(addr & 3)) { - control |= 0xf << 5; - break; - } + case 4: + /* require 4-byte alignment */ + if (!(addr & 3)) { + control |= 0xf << 5; + break; + } /* FALL THROUGH */ - default: - LOG_ERROR("unsupported {break,watch}point length/alignment"); - return ERROR_COMMAND_SYNTAX_ERROR; + default: + LOG_ERROR("unsupported {break,watch}point length/alignment"); + return ERROR_COMMAND_SYNTAX_ERROR; } /* other shared control bits: @@ -743,7 +742,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, xp->dirty = true; LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d", - xp->address, control, xp->number); + xp->address, control, xp->number); /* hardware is updated in write_dirty_registers() */ return ERROR_OK; @@ -798,7 +797,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp) } static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, - struct watchpoint *wp) + struct watchpoint *wp) { int retval; struct dpm_wp *dwp = dpm->dwp + index_t; @@ -816,15 +815,15 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t, control = dwp->bpwp.control; switch (wp->rw) { - case WPT_READ: - control |= 1 << 3; - break; - case WPT_WRITE: - control |= 2 << 3; - break; - case WPT_ACCESS: - control |= 3 << 3; - break; + case WPT_READ: + control |= 1 << 3; + break; + case WPT_WRITE: + control |= 2 << 3; + break; + case WPT_ACCESS: + control |= 3 << 3; + break; } dwp->bpwp.control = control; @@ -874,16 +873,16 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp) void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) { switch (dpm->arm->core_state) { - case ARM_STATE_ARM: - addr -= 8; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - addr -= 4; - break; - case ARM_STATE_JAZELLE: - /* ?? */ - break; + case ARM_STATE_ARM: + addr -= 8; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + addr -= 4; + break; + case ARM_STATE_JAZELLE: + /* ?? */ + break; } dpm->wp_pc = addr; } @@ -902,25 +901,25 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) /* Examine debug reason */ switch (DSCR_ENTRY(dscr)) { - case 6: /* Data abort (v6 only) */ - case 7: /* Prefetch abort (v6 only) */ + case 6: /* Data abort (v6 only) */ + case 7: /* Prefetch abort (v6 only) */ /* FALL THROUGH -- assume a v6 core in abort mode */ - case 0: /* HALT request from debugger */ - case 4: /* EDBGRQ */ - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 1: /* HW breakpoint */ - case 3: /* SW BKPT */ - case 5: /* vector catch */ - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 2: /* asynch watchpoint */ - case 10: /* precise watchpoint */ - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - default: - target->debug_reason = DBG_REASON_UNDEFINED; - break; + case 0: /* HALT request from debugger */ + case 4: /* EDBGRQ */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 1: /* HW breakpoint */ + case 3: /* SW BKPT */ + case 5: /* vector catch */ + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 2: /* asynch watchpoint */ + case 10:/* precise watchpoint */ + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + default: + target->debug_reason = DBG_REASON_UNDEFINED; + break; } } @@ -984,7 +983,7 @@ int arm_dpm_setup(struct arm_dpm *dpm) } LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", - target_name(target), dpm->nbp, dpm->nwp); + target_name(target), dpm->nbp, dpm->nwp); /* REVISIT ... and some of those breakpoints could match * execution context IDs... diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index ba2e155..66b2b1d 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -126,7 +126,7 @@ struct arm_dpm { /** Recent value of DSCR. */ uint32_t dscr; - // FIXME -- read/write DCSR methods and symbols + /* FIXME -- read/write DCSR methods and symbols */ }; int arm_dpm_setup(struct arm_dpm *dpm); diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c index 3a552ee..22538ca 100644 --- a/src/target/arm_jtag.c +++ b/src/target/arm_jtag.c @@ -20,18 +20,19 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "arm_jtag.h" - #if 0 #define _ARM_JTAG_SCAN_N_CHECK_ #endif -int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state) +int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, + uint32_t new_instr, void *no_verify_capture, tap_state_t end_state) { struct jtag_tap *tap; tap = jtag_info->tap; @@ -44,10 +45,8 @@ int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, vo field.in_value = NULL; if (no_verify_capture == NULL) - { jtag_add_ir_scan(tap, &field, end_state); - } else - { + else { /* FIX!!!! this is a kludge!!! arm926ejs.c should reimplement this arm_jtag_set_instr to * have special verification code. */ @@ -63,13 +62,12 @@ int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, ta uint32_t values[1]; int num_bits[1]; - values[0]=new_scan_chain; - num_bits[0]=jtag_info->scann_size; + values[0] = new_scan_chain; + num_bits[0] = jtag_info->scann_size; - if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL, end_state)) != ERROR_OK) - { + retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL, end_state); + if (retval != ERROR_OK) return retval; - } jtag_add_dr_out(jtag_info->tap, 1, @@ -87,9 +85,7 @@ static int arm_jtag_reset_callback(enum jtag_event event, void *priv) struct arm_jtag *jtag_info = priv; if (event == JTAG_TRST_ASSERTED) - { jtag_info->cur_scan_chain = 0; - } return ERROR_OK; } diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h index e90abfe..d22deae 100644 --- a/src/target/arm_jtag.h +++ b/src/target/arm_jtag.h @@ -20,13 +20,13 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM_JTAG #define ARM_JTAG #include <jtag/jtag.h> -struct arm_jtag -{ +struct arm_jtag { struct jtag_tap *tap; uint32_t scann_size; @@ -39,53 +39,46 @@ struct arm_jtag int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state); + static inline int arm_jtag_set_instr(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture, tap_state_t end_state) { /* inline most common code path */ struct jtag_tap *tap; tap = jtag_info->tap; - assert (tap != NULL); + assert(tap != NULL); if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) - { return arm_jtag_set_instr_inner(jtag_info, new_instr, no_verify_capture, end_state); - } return ERROR_OK; } - int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state); static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state) { /* inline most common code path */ int retval = ERROR_OK; if (jtag_info->cur_scan_chain != new_scan_chain) - { return arm_jtag_scann_inner(jtag_info, new_scan_chain, end_state); - } return retval; } - int arm_jtag_setup_connection(struct arm_jtag *jtag_info); /* use this as a static so we can inline it in -O3 and refer to it via a pointer */ -static __inline__ void arm7flip32(jtag_callback_data_t arg) +static inline void arm7flip32(jtag_callback_data_t arg) { - uint8_t *in = (uint8_t *)arg; - *((uint32_t *)arg) = flip_u32(le_to_h_u32(in), 32); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)arg) = flip_u32(le_to_h_u32(in), 32); } -static __inline__ void arm_le_to_h_u32(jtag_callback_data_t arg) +static inline void arm_le_to_h_u32(jtag_callback_data_t arg) { - uint8_t *in = (uint8_t *)arg; - *((uint32_t *)arg) = le_to_h_u32(in); + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)arg) = le_to_h_u32(in); } - #endif /* ARM_JTAG */ - diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index 9a48e6d..12a9ca8 100755 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -90,8 +90,8 @@ * Rd: register to load * Rn: base register */ -#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) - +#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16)) + /* Load Register Halfword Immediate Post-Index * Rd: register to load * Rn: base register @@ -108,7 +108,7 @@ * Rd: register to store * Rn: base register */ -#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) +#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16)) /* Store register Halfword Immediate Post-Index * Rd: register to store diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c index fba580b..115c7d4 100644 --- a/src/target/arm_semihosting.c +++ b/src/target/arm_semihosting.c @@ -323,7 +323,7 @@ static int do_semihosting(struct target *target) if (l < s) result = -1; else { - retval = target_write_buffer(target, a, s, (void*)arg); + retval = target_write_buffer(target, a, s, (void *)arg); if (retval != ERROR_OK) return retval; result = 0; @@ -392,8 +392,7 @@ static int do_semihosting(struct target *target) /* REVISIT this looks wrong ... ARM11 and Cortex-A8 * should work this way at least sometimes. */ - if (is_arm7_9(target_to_arm7_9(target))) - { + if (is_arm7_9(target_to_arm7_9(target))) { uint32_t spsr; /* return value in R0 */ @@ -402,7 +401,7 @@ static int do_semihosting(struct target *target) /* LR --> PC */ buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32, - buf_get_u32(arm_reg_current(arm,14)->value, 0, 32)); + buf_get_u32(arm_reg_current(arm, 14)->value, 0, 32)); arm->core_cache->reg_list[15].dirty = 1; /* saved PSR --> current PSR */ @@ -418,9 +417,7 @@ static int do_semihosting(struct target *target) if (spsr & 0x20) arm->core_state = ARM_STATE_THUMB; - } - else - { + } else { /* resume execution, this will be pc+2 to skip over the * bkpt instruction */ @@ -454,8 +451,7 @@ int arm_semihosting(struct target *target, int *retval) if (!arm->is_semihosting) return 0; - if (is_arm7_9(target_to_arm7_9(target))) - { + if (is_arm7_9(target_to_arm7_9(target))) { if (arm->core_mode != ARM_MODE_SVC) return 0; @@ -510,9 +506,7 @@ int arm_semihosting(struct target *target, int *retval) if (insn != 0xEF123456) return 0; } - } - else if (is_armv7m(target_to_armv7m(target))) - { + } else if (is_armv7m(target_to_armv7m(target))) { uint16_t insn; if (target->debug_reason != DBG_REASON_BREAKPOINT) @@ -529,9 +523,7 @@ int arm_semihosting(struct target *target, int *retval) /* bkpt 0xAB */ if (insn != 0xBEAB) return 0; - } - else - { + } else { LOG_ERROR("Unsupported semi-hosting Target"); return 0; } diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index a0ffdde..215739d 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -32,51 +33,32 @@ #include "register.h" #include <helper/log.h> - static uint32_t arm_shift(uint8_t shift, uint32_t Rm, - uint32_t shift_amount, uint8_t *carry) + uint32_t shift_amount, uint8_t *carry) { uint32_t return_value = 0; shift_amount &= 0xff; - if (shift == 0x0) /* LSL */ - { - if ((shift_amount > 0) && (shift_amount <= 32)) - { + if (shift == 0x0) { /* LSL */ + if ((shift_amount > 0) && (shift_amount <= 32)) { return_value = Rm << shift_amount; *carry = Rm >> (32 - shift_amount); - } - else if (shift_amount > 32) - { + } else if (shift_amount > 32) { return_value = 0x0; *carry = 0x0; - } - else /* (shift_amount == 0) */ - { + } else /* (shift_amount == 0) */ return_value = Rm; - } - } - else if (shift == 0x1) /* LSR */ - { - if ((shift_amount > 0) && (shift_amount <= 32)) - { + } else if (shift == 0x1) { /* LSR */ + if ((shift_amount > 0) && (shift_amount <= 32)) { return_value = Rm >> shift_amount; *carry = (Rm >> (shift_amount - 1)) & 1; - } - else if (shift_amount > 32) - { + } else if (shift_amount > 32) { return_value = 0x0; *carry = 0x0; - } - else /* (shift_amount == 0) */ - { + } else /* (shift_amount == 0) */ return_value = Rm; - } - } - else if (shift == 0x2) /* ASR */ - { - if ((shift_amount > 0) && (shift_amount <= 32)) - { + } else if (shift == 0x2) { /* ASR */ + if ((shift_amount > 0) && (shift_amount <= 32)) { /* C right shifts of unsigned values are guaranteed to * be logical (shift in zeroes); simulate an arithmetic * shift (shift in signed-bit) by adding the sign bit @@ -85,40 +67,25 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm, return_value = Rm >> shift_amount; if (Rm & 0x80000000) return_value |= 0xffffffff << (32 - shift_amount); - } - else if (shift_amount > 32) - { - if (Rm & 0x80000000) - { + } else if (shift_amount > 32) { + if (Rm & 0x80000000) { return_value = 0xffffffff; *carry = 0x1; - } - else - { + } else { return_value = 0x0; *carry = 0x0; } - } - else /* (shift_amount == 0) */ - { + } else /* (shift_amount == 0) */ return_value = Rm; - } - } - else if (shift == 0x3) /* ROR */ - { + } else if (shift == 0x3) { /* ROR */ if (shift_amount == 0) - { return_value = Rm; - } - else - { + else { shift_amount = shift_amount % 32; return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount)); *carry = (return_value >> 31) & 0x1; } - } - else if (shift == 0x4) /* RRX */ - { + } else if (shift == 0x4) { /* RRX */ return_value = Rm >> 1; if (*carry) Rm |= 0x80000000; @@ -130,8 +97,8 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm, static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, - int variant, union arm_shifter_operand shifter_operand, - uint8_t *shifter_carry_out) + int variant, union arm_shifter_operand shifter_operand, + uint8_t *shifter_carry_out) { uint32_t return_value; int instruction_size; @@ -144,11 +111,8 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, *shifter_carry_out = sim->get_cpsr(sim, 29, 1); if (variant == 0) /* 32-bit immediate */ - { return_value = shifter_operand.immediate.immediate; - } - else if (variant == 1) /* immediate shift */ - { + else if (variant == 1) {/* immediate shift */ uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm); /* adjust RM in case the PC is being read */ @@ -158,9 +122,7 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out); - } - else if (variant == 2) /* register shift */ - { + } else if (variant == 2) { /* register shift */ uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm); uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs); @@ -170,9 +132,7 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out); - } - else - { + } else { LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2"); return_value = 0xffffffff; } @@ -182,8 +142,7 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, static int pass_condition(uint32_t cpsr, uint32_t opcode) { - switch ((opcode & 0xf0000000) >> 28) - { + switch ((opcode & 0xf0000000) >> 28) { case 0x0: /* EQ */ if (cpsr & 0x40000000) return 1; @@ -280,45 +239,35 @@ static int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode) * but the new pc is stored in the variable pointed at by the argument */ static int arm_simulate_step_core(struct target *target, - uint32_t *dry_run_pc, struct arm_sim_interface *sim) + uint32_t *dry_run_pc, struct arm_sim_interface *sim) { uint32_t current_pc = sim->get_reg(sim, 15); struct arm_instruction instruction; int instruction_size; int retval = ERROR_OK; - if (sim->get_state(sim) == ARM_STATE_ARM) - { + if (sim->get_state(sim) == ARM_STATE_ARM) { uint32_t opcode; /* get current instruction, and identify it */ - if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK) - { + retval = target_read_u32(target, current_pc, &opcode); + if (retval != ERROR_OK) return retval; - } - if ((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK) - { + retval = arm_evaluate_opcode(opcode, current_pc, &instruction); + if (retval != ERROR_OK) return retval; - } instruction_size = 4; /* check condition code (for all instructions) */ - if (!pass_condition(sim->get_cpsr(sim, 0, 32), opcode)) - { + if (!pass_condition(sim->get_cpsr(sim, 0, 32), opcode)) { if (dry_run_pc) - { *dry_run_pc = current_pc + instruction_size; - } else - { sim->set_reg(sim, 15, current_pc + instruction_size); - } return ERROR_OK; } - } - else - { + } else { uint16_t opcode; retval = target_read_u16(target, current_pc, &opcode); @@ -331,17 +280,12 @@ static int arm_simulate_step_core(struct target *target, /* check condition code (only for branch (1) instructions) */ if ((opcode & 0xf000) == 0xd000 - && !thumb_pass_branch_condition( - sim->get_cpsr(sim, 0, 32), opcode)) - { + && !thumb_pass_branch_condition( + sim->get_cpsr(sim, 0, 32), opcode)) { if (dry_run_pc) - { *dry_run_pc = current_pc + instruction_size; - } else - { sim->set_reg(sim, 15, current_pc + instruction_size); - } return ERROR_OK; } @@ -362,67 +306,44 @@ static int arm_simulate_step_core(struct target *target, /* examine instruction type */ /* branch instructions */ - if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX)) - { + if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX)) { uint32_t target_address; if (instruction.info.b_bl_bx_blx.reg_operand == -1) - { target_address = instruction.info.b_bl_bx_blx.target_address; - } - else - { - target_address = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand); + else { + target_address = sim->get_reg_mode(sim, + instruction.info.b_bl_bx_blx.reg_operand); if (instruction.info.b_bl_bx_blx.reg_operand == 15) - { target_address += 2 * instruction_size; - } } - if (dry_run_pc) - { + if (dry_run_pc) { *dry_run_pc = target_address & ~1; return ERROR_OK; - } - else - { + } else { if (instruction.type == ARM_B) - { sim->set_reg(sim, 15, target_address); - } - else if (instruction.type == ARM_BL) - { + else if (instruction.type == ARM_BL) { uint32_t old_pc = sim->get_reg(sim, 15); int T = (sim->get_state(sim) == ARM_STATE_THUMB); sim->set_reg_mode(sim, 14, old_pc + 4 + T); sim->set_reg(sim, 15, target_address); - } - else if (instruction.type == ARM_BX) - { + } else if (instruction.type == ARM_BX) { if (target_address & 0x1) - { sim->set_state(sim, ARM_STATE_THUMB); - } else - { sim->set_state(sim, ARM_STATE_ARM); - } sim->set_reg(sim, 15, target_address & 0xfffffffe); - } - else if (instruction.type == ARM_BLX) - { + } else if (instruction.type == ARM_BLX) { uint32_t old_pc = sim->get_reg(sim, 15); int T = (sim->get_state(sim) == ARM_STATE_THUMB); sim->set_reg_mode(sim, 14, old_pc + 4 + T); if (target_address & 0x1) - { sim->set_state(sim, ARM_STATE_THUMB); - } else - { sim->set_state(sim, ARM_STATE_ARM); - } sim->set_reg(sim, 15, target_address & 0xfffffffe); } @@ -431,8 +352,7 @@ static int arm_simulate_step_core(struct target *target, } /* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */ else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC)) - || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) - { + || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) { uint32_t Rd, Rn, shifter_operand; uint8_t C = sim->get_cpsr(sim, 29, 1); uint8_t carry_out; @@ -480,17 +400,14 @@ static int arm_simulate_step_core(struct target *target, else LOG_WARNING("unhandled instruction type"); - if (dry_run_pc) - { + if (dry_run_pc) { if (instruction.info.data_proc.Rd == 15) *dry_run_pc = Rd & ~1; else *dry_run_pc = current_pc + instruction_size; return ERROR_OK; - } - else - { + } else { if (instruction.info.data_proc.Rd == 15) { sim->set_reg_mode(sim, 15, Rd & ~1); if (Rd & 1) @@ -504,21 +421,15 @@ static int arm_simulate_step_core(struct target *target, } } /* compare instructions (CMP, CMN, TST, TEQ) */ - else if ((instruction.type >= ARM_TST) && (instruction.type <= ARM_CMN)) - { - if (dry_run_pc) - { + else if ((instruction.type >= ARM_TST) && (instruction.type <= ARM_CMN)) { + if (dry_run_pc) { *dry_run_pc = current_pc + instruction_size; return ERROR_OK; - } - else - { + } else LOG_WARNING("no updating of flags yet"); - } } /* load register instructions */ - else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) - { + else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) { uint32_t load_address = 0, modified_address = 0, load_value = 0; uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn); @@ -526,15 +437,12 @@ static int arm_simulate_step_core(struct target *target, if (instruction.info.load_store.Rn == 15) Rn += 2 * instruction_size; - if (instruction.info.load_store.offset_mode == 0) - { + if (instruction.info.load_store.offset_mode == 0) { if (instruction.info.load_store.U) modified_address = Rn + instruction.info.load_store.offset.offset; else modified_address = Rn - instruction.info.load_store.offset.offset; - } - else if (instruction.info.load_store.offset_mode == 1) - { + } else if (instruction.info.load_store.offset_mode == 1) { uint32_t offset; uint32_t Rm = sim->get_reg_mode(sim, instruction.info.load_store.offset.reg.Rm); @@ -548,31 +456,23 @@ static int arm_simulate_step_core(struct target *target, modified_address = Rn + offset; else modified_address = Rn - offset; - } - else - { + } else LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)"); - } - if (instruction.info.load_store.index_mode == 0) - { + if (instruction.info.load_store.index_mode == 0) { /* offset mode * we load from the modified address, but don't change * the base address register */ load_address = modified_address; modified_address = Rn; - } - else if (instruction.info.load_store.index_mode == 1) - { + } else if (instruction.info.load_store.index_mode == 1) { /* pre-indexed mode * we load from the modified address, and write it * back to the base address register */ load_address = modified_address; - } - else if (instruction.info.load_store.index_mode == 2) - { + } else if (instruction.info.load_store.index_mode == 2) { /* post-indexed mode * we load from the unmodified address, and write the * modified address back @@ -580,28 +480,24 @@ static int arm_simulate_step_core(struct target *target, load_address = Rn; } - if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) - { + if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) { retval = target_read_u32(target, load_address, &load_value); if (retval != ERROR_OK) return retval; } - if (dry_run_pc) - { + if (dry_run_pc) { if (instruction.info.load_store.Rd == 15) *dry_run_pc = load_value & ~1; else *dry_run_pc = current_pc + instruction_size; return ERROR_OK; - } - else - { + } else { if ((instruction.info.load_store.index_mode == 1) || (instruction.info.load_store.index_mode == 2)) - { - sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address); - } + sim->set_reg_mode(sim, + instruction.info.load_store.Rn, + modified_address); if (instruction.info.load_store.Rd == 15) { sim->set_reg_mode(sim, 15, load_value & ~1); @@ -615,84 +511,68 @@ static int arm_simulate_step_core(struct target *target, } } /* load multiple instruction */ - else if (instruction.type == ARM_LDM) - { + else if (instruction.type == ARM_LDM) { int i; uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn); uint32_t load_values[16]; int bits_set = 0; - for (i = 0; i < 16; i++) - { + for (i = 0; i < 16; i++) { if (instruction.info.load_store_multiple.register_list & (1 << i)) bits_set++; } - switch (instruction.info.load_store_multiple.addressing_mode) - { - case 0: /* Increment after */ + switch (instruction.info.load_store_multiple.addressing_mode) { + case 0: /* Increment after */ Rn = Rn; break; - case 1: /* Increment before */ + case 1: /* Increment before */ Rn = Rn + 4; break; - case 2: /* Decrement after */ + case 2: /* Decrement after */ Rn = Rn - (bits_set * 4) + 4; break; - case 3: /* Decrement before */ + case 3: /* Decrement before */ Rn = Rn - (bits_set * 4); break; } - for (i = 0; i < 16; i++) - { - if (instruction.info.load_store_multiple.register_list & (1 << i)) - { + for (i = 0; i < 16; i++) { + if (instruction.info.load_store_multiple.register_list & (1 << i)) { if ((!dry_run_pc) || (i == 15)) - { target_read_u32(target, Rn, &load_values[i]); - } Rn += 4; } } - if (dry_run_pc) - { - if (instruction.info.load_store_multiple.register_list & 0x8000) - { + if (dry_run_pc) { + if (instruction.info.load_store_multiple.register_list & 0x8000) { *dry_run_pc = load_values[15] & ~1; return ERROR_OK; } - } - else - { + } else { int update_cpsr = 0; - if (instruction.info.load_store_multiple.S) - { + if (instruction.info.load_store_multiple.S) { if (instruction.info.load_store_multiple.register_list & 0x8000) update_cpsr = 1; } - for (i = 0; i < 16; i++) - { - if (instruction.info.load_store_multiple.register_list & (1 << i)) - { + for (i = 0; i < 16; i++) { + if (instruction.info.load_store_multiple.register_list & (1 << i)) { if (i == 15) { uint32_t val = load_values[i]; - sim->set_reg_mode(sim, i, val & ~1); - if (val & 1) - sim->set_state(sim, ARM_STATE_THUMB); - else - sim->set_state(sim, ARM_STATE_ARM); - } else { + sim->set_reg_mode(sim, i, val & ~1); + if (val & 1) + sim->set_state(sim, ARM_STATE_THUMB); + else + sim->set_state(sim, ARM_STATE_ARM); + } else sim->set_reg_mode(sim, i, load_values[i]); - } } } - if (update_cpsr) - { + if (update_cpsr) { uint32_t spsr = sim->get_reg_mode(sim, 16); sim->set_reg(sim, ARMV4_5_CPSR, spsr); } @@ -701,51 +581,44 @@ static int arm_simulate_step_core(struct target *target, if (instruction.info.load_store_multiple.W) sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn); + if (instruction.info.load_store_multiple.register_list & 0x8000) return ERROR_OK; } } /* store multiple instruction */ - else if (instruction.type == ARM_STM) - { + else if (instruction.type == ARM_STM) { int i; - if (dry_run_pc) - { + if (dry_run_pc) { /* STM wont affect PC (advance by instruction size */ - } - else - { + } else { uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn); int bits_set = 0; - for (i = 0; i < 16; i++) - { + for (i = 0; i < 16; i++) { if (instruction.info.load_store_multiple.register_list & (1 << i)) bits_set++; } - switch (instruction.info.load_store_multiple.addressing_mode) - { - case 0: /* Increment after */ + switch (instruction.info.load_store_multiple.addressing_mode) { + case 0: /* Increment after */ Rn = Rn; break; - case 1: /* Increment before */ + case 1: /* Increment before */ Rn = Rn + 4; break; - case 2: /* Decrement after */ + case 2: /* Decrement after */ Rn = Rn - (bits_set * 4) + 4; break; - case 3: /* Decrement before */ + case 3: /* Decrement before */ Rn = Rn - (bits_set * 4); break; } - for (i = 0; i < 16; i++) - { - if (instruction.info.load_store_multiple.register_list & (1 << i)) - { + for (i = 0; i < 16; i++) { + if (instruction.info.load_store_multiple.register_list & (1 << i)) { target_write_u32(target, Rn, sim->get_reg_mode(sim, i)); Rn += 4; } @@ -757,22 +630,17 @@ static int arm_simulate_step_core(struct target *target, instruction.info.load_store_multiple.Rn, Rn); } - } - else if (!dry_run_pc) - { + } else if (!dry_run_pc) { /* the instruction wasn't handled, but we're supposed to simulate it */ LOG_ERROR("Unimplemented instruction, could not simulate it."); return ERROR_FAIL; } - if (dry_run_pc) - { + if (dry_run_pc) { *dry_run_pc = current_pc + instruction_size; return ERROR_OK; - } - else - { + } else { sim->set_reg(sim, 15, current_pc + instruction_size); return ERROR_OK; } @@ -806,7 +674,7 @@ static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_ struct arm *arm = (struct arm *)sim->user_data; buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, - arm->core_mode, reg).value, 0, 32, value); + arm->core_mode, reg).value, 0, 32, value); } static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) @@ -830,7 +698,6 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode arm->core_state = mode; } - static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim) { struct arm *arm = (struct arm *)sim->user_data; @@ -838,8 +705,6 @@ static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim) return arm->core_mode; } - - int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) { struct arm *arm = target_to_arm(target); @@ -857,4 +722,3 @@ int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) return arm_simulate_step_core(target, dry_run_pc, &sim); } - diff --git a/src/target/arm_simulator.h b/src/target/arm_simulator.h index b332a17..3a7ac13 100644 --- a/src/target/arm_simulator.h +++ b/src/target/arm_simulator.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARM_SIMULATOR_H #define ARM_SIMULATOR_H @@ -24,8 +25,7 @@ struct target; -struct arm_sim_interface -{ +struct arm_sim_interface { void *user_data; uint32_t (*get_reg)(struct arm_sim_interface *sim, int reg); void (*set_reg)(struct arm_sim_interface *sim, int reg, uint32_t value); diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 949ced4..11b6be6 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -36,10 +37,9 @@ #include "algorithm.h" #include "register.h" - /* offsets into armv4_5 core register cache */ enum { -// ARMV4_5_CPSR = 31, +/* ARMV4_5_CPSR = 31, */ ARMV4_5_SPSR_FIQ = 32, ARMV4_5_SPSR_IRQ = 33, ARMV4_5_SPSR_SVC = 34, @@ -167,27 +167,27 @@ bool is_arm_mode(unsigned psr_mode) int arm_mode_to_number(enum arm_mode mode) { switch (mode) { - case ARM_MODE_ANY: + case ARM_MODE_ANY: /* map MODE_ANY to user mode */ - case ARM_MODE_USR: - return 0; - case ARM_MODE_FIQ: - return 1; - case ARM_MODE_IRQ: - return 2; - case ARM_MODE_SVC: - return 3; - case ARM_MODE_ABT: - return 4; - case ARM_MODE_UND: - return 5; - case ARM_MODE_SYS: - return 6; - case ARM_MODE_MON: - return 7; - default: - LOG_ERROR("invalid mode value encountered %d", mode); - return -1; + case ARM_MODE_USR: + return 0; + case ARM_MODE_FIQ: + return 1; + case ARM_MODE_IRQ: + return 2; + case ARM_MODE_SVC: + return 3; + case ARM_MODE_ABT: + return 4; + case ARM_MODE_UND: + return 5; + case ARM_MODE_SYS: + return 6; + case ARM_MODE_MON: + return 7; + default: + LOG_ERROR("invalid mode value encountered %d", mode); + return -1; } } @@ -195,30 +195,29 @@ int arm_mode_to_number(enum arm_mode mode) enum arm_mode armv4_5_number_to_mode(int number) { switch (number) { - case 0: - return ARM_MODE_USR; - case 1: - return ARM_MODE_FIQ; - case 2: - return ARM_MODE_IRQ; - case 3: - return ARM_MODE_SVC; - case 4: - return ARM_MODE_ABT; - case 5: - return ARM_MODE_UND; - case 6: - return ARM_MODE_SYS; - case 7: - return ARM_MODE_MON; - default: - LOG_ERROR("mode index out of bounds %d", number); - return ARM_MODE_ANY; + case 0: + return ARM_MODE_USR; + case 1: + return ARM_MODE_FIQ; + case 2: + return ARM_MODE_IRQ; + case 3: + return ARM_MODE_SVC; + case 4: + return ARM_MODE_ABT; + case 5: + return ARM_MODE_UND; + case 6: + return ARM_MODE_SYS; + case 7: + return ARM_MODE_MON; + default: + LOG_ERROR("mode index out of bounds %d", number); + return ARM_MODE_ANY; } } -static const char *arm_state_strings[] = -{ +static const char *arm_state_strings[] = { "ARM", "Thumb", "Jazelle", "ThumbEE", }; @@ -312,8 +311,7 @@ static const struct { /* map core mode (USR, FIQ, ...) and register number to * indices into the register cache */ -const int armv4_5_core_reg_map[8][17] = -{ +const int armv4_5_core_reg_map[8][17] = { { /* USR */ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31 }, @@ -371,8 +369,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->map = &armv4_5_core_reg_map[num][0]; arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS) - ? NULL - : arm->core_cache->reg_list + arm->map[16]; + ? NULL + : arm->core_cache->reg_list + arm->map[16]; /* Older ARMs won't have the J bit */ enum arm_state state; @@ -393,8 +391,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr) arm->core_state = state; LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, - arm_mode_name(mode), - arm_state_strings[arm->core_state]); + arm_mode_name(mode), + arm_state_strings[arm->core_state]); } /** @@ -437,8 +435,7 @@ static const uint8_t arm_gdb_dummy_fp_value[12]; * Modern ARM cores use Vector Floating Point (VFP), if they * have any floating point support. VFP is not FPA-compatible. */ -struct reg arm_gdb_dummy_fp_reg = -{ +struct reg arm_gdb_dummy_fp_reg = { .name = "GDB dummy FPA register", .value = (uint8_t *) arm_gdb_dummy_fp_value, .valid = 1, @@ -451,8 +448,7 @@ static const uint8_t arm_gdb_dummy_fps_value[4]; * Dummy FPA status registers are required to support GDB on ARM. * Register packets require an obsolete FPA status register. */ -struct reg arm_gdb_dummy_fps_reg = -{ +struct reg arm_gdb_dummy_fps_reg = { .name = "GDB dummy FPA status register", .value = (uint8_t *) arm_gdb_dummy_fps_value, .valid = 1, @@ -473,8 +469,7 @@ static int armv4_5_get_core_reg(struct reg *reg) struct arm_reg *reg_arch_info = reg->arch_info; struct target *target = reg_arch_info->target; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -496,8 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) struct arm *armv4_5_target = target_to_arm(target); uint32_t value = buf_get_u32(buf, 0, 32); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -514,12 +508,12 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) * it won't hurt since CPSR is always flushed anyway. */ if (armv4_5_target->core_mode != - (enum arm_mode)(value & 0x1f)) { + (enum arm_mode)(value & 0x1f)) { LOG_DEBUG("changing ARM core mode to '%s'", - arm_mode_name(value & 0x1f)); + arm_mode_name(value & 0x1f)); value &= ~((1 << 24) | (1 << 5)); armv4_5_target->write_core_reg(target, reg, - 16, ARM_MODE_ANY, value); + 16, ARM_MODE_ANY, value); } } else { buf_set_u32(reg->value, 0, 32, value); @@ -555,11 +549,10 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) cache->reg_list = reg_list; cache->num_regs = 0; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { /* Skip registers this core doesn't expose */ if (arm_core_regs[i].mode == ARM_MODE_MON - && arm->core_type != ARM_MODE_MON) + && arm->core_type != ARM_MODE_MON) continue; /* REVISIT handle Cortex-M, which only shadows R13/SP */ @@ -588,26 +581,25 @@ int arm_arch_state(struct target *target) { struct arm *arm = target_to_arm(target); - if (arm->common_magic != ARM_COMMON_MAGIC) - { + if (arm->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARM target"); return ERROR_FAIL; } LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", - arm_state_strings[arm->core_state], - debug_reason_name(target), - arm_mode_name(arm->core_mode), - buf_get_u32(arm->cpsr->value, 0, 32), - buf_get_u32(arm->pc->value, 0, 32), - arm->is_semihosting ? ", semihosting" : ""); + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", + arm_state_strings[arm->core_state], + debug_reason_name(target), + arm_mode_name(arm->core_mode), + buf_get_u32(arm->cpsr->value, 0, 32), + buf_get_u32(arm->pc->value, 0, 32), + arm->is_semihosting ? ", semihosting" : ""); return ERROR_OK; } #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \ - cache->reg_list[armv4_5_core_reg_map[mode][num]] + (cache->reg_list[armv4_5_core_reg_map[mode][num]]) COMMAND_HANDLER(handle_armv4_5_reg_command) { @@ -615,33 +607,30 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) struct arm *arm = target_to_arm(target); struct reg *regs; - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "error: target must be halted for register accesses"); return ERROR_FAIL; } - if (arm->core_type != ARM_MODE_ANY) - { - command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd"); + if (arm->core_type != ARM_MODE_ANY) { + command_print(CMD_CTX, + "Microcontroller Profile not supported - use standard reg cmd"); return ERROR_OK; } - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } if (!arm->full_context) { command_print(CMD_CTX, "error: target doesn't support %s", - CMD_NAME); + CMD_NAME); return ERROR_FAIL; } @@ -654,26 +643,26 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* label this bank of registers (or shadows) */ switch (arm_mode_data[mode].psr) { - case ARM_MODE_SYS: - continue; - case ARM_MODE_USR: - name = "System and User"; - sep = ""; - break; - case ARM_MODE_MON: - if (arm->core_type != ARM_MODE_MON) + case ARM_MODE_SYS: continue; + case ARM_MODE_USR: + name = "System and User"; + sep = ""; + break; + case ARM_MODE_MON: + if (arm->core_type != ARM_MODE_MON) + continue; /* FALLTHROUGH */ - default: - name = arm_mode_data[mode].name; - shadow = "shadow "; - break; + default: + name = arm_mode_data[mode].name; + shadow = "shadow "; + break; } command_print(CMD_CTX, "%s%s mode %sregisters", - sep, name, shadow); + sep, name, shadow); /* display N rows of up to 4 registers each */ - for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) { + for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) { char output[80]; int output_len = 0; @@ -693,8 +682,8 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) value = buf_get_u32(reg->value, 0, 32); output_len += snprintf(output + output_len, sizeof(output) - output_len, - "%8s: %8.8" PRIx32 " ", - reg->name, value); + "%8s: %8.8" PRIx32 " ", + reg->name, value); } command_print(CMD_CTX, "%s", output); } @@ -708,29 +697,22 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command) struct target *target = get_current_target(CMD_CTX); struct arm *arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (arm->core_type == ARM_MODE_THREAD) - { + if (arm->core_type == ARM_MODE_THREAD) { /* armv7m not supported */ command_print(CMD_CTX, "Unsupported Command"); return ERROR_OK; } - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { if (strcmp(CMD_ARGV[0], "arm") == 0) - { arm->core_state = ARM_STATE_ARM; - } if (strcmp(CMD_ARGV[0], "thumb") == 0) - { arm->core_state = ARM_STATE_THUMB; - } } command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]); @@ -758,35 +740,34 @@ COMMAND_HANDLER(handle_arm_disassemble_command) return ERROR_FAIL; } - if (arm->core_type == ARM_MODE_THREAD) - { + if (arm->core_type == ARM_MODE_THREAD) { /* armv7m is always thumb mode */ thumb = 1; } switch (CMD_ARGC) { - case 3: - if (strcmp(CMD_ARGV[2], "thumb") != 0) - goto usage; - thumb = 1; + case 3: + if (strcmp(CMD_ARGV[2], "thumb") != 0) + goto usage; + thumb = 1; /* FALL THROUGH */ - case 2: - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); + case 2: + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); /* FALL THROUGH */ - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); - if (address & 0x01) { - if (!thumb) { - command_print(CMD_CTX, "Disassemble as Thumb"); - thumb = 1; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); + if (address & 0x01) { + if (!thumb) { + command_print(CMD_CTX, "Disassemble as Thumb"); + thumb = 1; + } + address &= ~1; } - address &= ~1; - } - break; - default: + break; + default: usage: - count = 0; - retval = ERROR_COMMAND_SYNTAX_ERROR; + count = 0; + retval = ERROR_COMMAND_SYNTAX_ERROR; } while (count-- > 0) { @@ -819,7 +800,7 @@ usage: return retval; } -static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { struct command_context *context; struct target *target; @@ -827,7 +808,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) int retval; context = current_command_context(interp); - assert( context != NULL); + assert(context != NULL); target = get_current_target(context); if (target == NULL) { @@ -868,7 +849,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return retval; if (l & ~0xf) { LOG_ERROR("%s: %s %d out of range", __func__, - "coprocessor", (int) l); + "coprocessor", (int) l); return JIM_ERR; } cpnum = l; @@ -878,7 +859,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return retval; if (l & ~0x7) { LOG_ERROR("%s: %s %d out of range", __func__, - "op1", (int) l); + "op1", (int) l); return JIM_ERR; } op1 = l; @@ -888,7 +869,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return retval; if (l & ~0xf) { LOG_ERROR("%s: %s %d out of range", __func__, - "CRn", (int) l); + "CRn", (int) l); return JIM_ERR; } CRn = l; @@ -898,7 +879,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return retval; if (l & ~0xf) { LOG_ERROR("%s: %s %d out of range", __func__, - "CRm", (int) l); + "CRm", (int) l); return JIM_ERR; } CRm = l; @@ -908,7 +889,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return retval; if (l & ~0x7) { LOG_ERROR("%s: %s %d out of range", __func__, - "op2", (int) l); + "op2", (int) l); return JIM_ERR; } op2 = l; @@ -925,19 +906,18 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv) */ if (argc == 7) { retval = Jim_GetLong(interp, argv[6], &l); - if (retval != JIM_OK) { + if (retval != JIM_OK) return retval; - } value = l; /* NOTE: parameters reordered! */ - // ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) + /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */ retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value); if (retval != ERROR_OK) return JIM_ERR; } else { /* NOTE: parameters reordered! */ - // ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) + /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */ retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value); if (retval != ERROR_OK) return JIM_ERR; @@ -964,20 +944,17 @@ COMMAND_HANDLER(handle_arm_semihosting_command) return ERROR_FAIL; } - if (!arm->setup_semihosting) - { + if (!arm->setup_semihosting) { command_print(CMD_CTX, "semihosting not supported for current target"); return ERROR_FAIL; } - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { int semihosting; COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -992,8 +969,8 @@ COMMAND_HANDLER(handle_arm_semihosting_command) } command_print(CMD_CTX, "semihosting is %s", - arm->is_semihosting - ? "enabled" : "disabled"); + arm->is_semihosting + ? "enabled" : "disabled"); return ERROR_OK; } @@ -1055,19 +1032,18 @@ const struct command_registration arm_command_handlers[] = { }; int arm_get_gdb_reg_list(struct target *target, - struct reg **reg_list[], int *reg_list_size) + struct reg **reg_list[], int *reg_list_size) { struct arm *arm = target_to_arm(target); int i; - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } *reg_list_size = 26; - *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); for (i = 0; i < 16; i++) (*reg_list)[i] = arm_reg_current(arm, i); @@ -1082,30 +1058,31 @@ int arm_get_gdb_reg_list(struct target *target, } /* wait for execution to complete and check exit point */ -static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) +static int armv4_5_run_algorithm_completion(struct target *target, + uint32_t exit_point, + int timeout_ms, + void *arch_info) { int retval; struct arm *arm = target_to_arm(target); - if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) - { + retval = target_wait_state(target, TARGET_HALTED, timeout_ms); + if (retval != ERROR_OK) return retval; - } - if (target->state != TARGET_HALTED) - { - if ((retval = target_halt(target)) != ERROR_OK) + if (target->state != TARGET_HALTED) { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) - { + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval != ERROR_OK) return retval; - } return ERROR_TARGET_TIMEOUT; } /* fast exit: ARMv5+ code can use BKPT */ - if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) - { - LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", + if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) { + LOG_WARNING( + "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", buf_get_u32(arm->pc->value, 0, 32)); return ERROR_TARGET_TIMEOUT; } @@ -1114,12 +1091,12 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit } int armv4_5_run_algorithm_inner(struct target *target, - int num_mem_params, struct mem_param *mem_params, - int num_reg_params, struct reg_param *reg_params, - uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info, - int (*run_it)(struct target *target, uint32_t exit_point, - int timeout_ms, void *arch_info)) + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info, + int (*run_it)(struct target *target, uint32_t exit_point, + int timeout_ms, void *arch_info)) { struct arm *arm = target_to_arm(target); struct arm_algorithm *arm_algorithm_info = arch_info; @@ -1132,27 +1109,23 @@ int armv4_5_run_algorithm_inner(struct target *target, LOG_DEBUG("Running algorithm"); - if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) - { + if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("current target isn't an ARMV4/5 target"); return ERROR_TARGET_INVALID; } - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } /* armv5 and later can terminate with BKPT instruction; less overhead */ - if (!exit_point && arm->is_armv4) - { + if (!exit_point && arm->is_armv4) { LOG_ERROR("ARMv4 target needs HW breakpoint location"); return ERROR_FAIL; } @@ -1160,46 +1133,41 @@ int armv4_5_run_algorithm_inner(struct target *target, /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure; * they'll be restored later. */ - for (i = 0; i <= 16; i++) - { + for (i = 0; i <= 16; i++) { struct reg *r; r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i); if (!r->valid) arm->read_core_reg(target, r, i, - arm_algorithm_info->core_mode); + arm_algorithm_info->core_mode); context[i] = buf_get_u32(r->value, 0, 32); } cpsr = buf_get_u32(arm->cpsr->value, 0, 32); - for (i = 0; i < num_mem_params; i++) - { - if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) - { + for (i = 0; i < num_mem_params; i++) { + retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) return retval; - } } - for (i = 0; i < num_reg_params; i++) - { + for (i = 0; i < num_reg_params; i++) { struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + if (reg->size != reg_params[i].size) { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } - if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK) - { + retval = armv4_5_set_core_reg(reg, reg_params[i].value); + if (retval != ERROR_OK) return retval; - } } arm->core_state = arm_algorithm_info->core_state; @@ -1207,35 +1175,33 @@ int armv4_5_run_algorithm_inner(struct target *target, exit_breakpoint_size = 4; else if (arm->core_state == ARM_STATE_THUMB) exit_breakpoint_size = 2; - else - { + else { LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); return ERROR_COMMAND_SYNTAX_ERROR; } - if (arm_algorithm_info->core_mode != ARM_MODE_ANY) - { + if (arm_algorithm_info->core_mode != ARM_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", - arm_algorithm_info->core_mode); + arm_algorithm_info->core_mode); buf_set_u32(arm->cpsr->value, 0, 5, - arm_algorithm_info->core_mode); + arm_algorithm_info->core_mode); arm->cpsr->dirty = 1; arm->cpsr->valid = 1; } /* terminate using a hardware or (ARMv5+) software breakpoint */ - if (exit_point && (retval = breakpoint_add(target, exit_point, - exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) - { - LOG_ERROR("can't add HW breakpoint to terminate algorithm"); - return ERROR_TARGET_FAILURE; + if (exit_point) { + retval = breakpoint_add(target, exit_point, + exit_breakpoint_size, BKPT_HARD); + if (retval != ERROR_OK) { + LOG_ERROR("can't add HW breakpoint to terminate algorithm"); + return ERROR_TARGET_FAILURE; + } } - if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) - { + retval = target_resume(target, 0, entry_point, 1, 1); + if (retval != ERROR_OK) return retval; - } - int retvaltemp; retval = run_it(target, exit_point, timeout_ms, arch_info); if (exit_point) @@ -1244,31 +1210,32 @@ int armv4_5_run_algorithm_inner(struct target *target, if (retval != ERROR_OK) return retval; - for (i = 0; i < num_mem_params; i++) - { - if (mem_params[i].direction != PARAM_OUT) - if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) - { - retval = retvaltemp; - } + for (i = 0; i < num_mem_params; i++) { + if (mem_params[i].direction != PARAM_OUT) { + int retvaltemp = target_read_buffer(target, mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retvaltemp != ERROR_OK) + retval = retvaltemp; + } } - for (i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { + for (i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction != PARAM_OUT) { - struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { + struct reg *reg = register_get_by_name(arm->core_cache, + reg_params[i].reg_name, + 0); + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); retval = ERROR_COMMAND_SYNTAX_ERROR; continue; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + if (reg->size != reg_params[i].size) { + LOG_ERROR( + "BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); retval = ERROR_COMMAND_SYNTAX_ERROR; continue; } @@ -1278,20 +1245,20 @@ int armv4_5_run_algorithm_inner(struct target *target, } /* restore everything we saved before (17 or 18 registers) */ - for (i = 0; i <= 16; i++) - { + for (i = 0; i <= 16; i++) { uint32_t regvalue; regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32); - if (regvalue != context[i]) - { + if (regvalue != context[i]) { LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", - ARMV4_5_CORE_REG_MODE(arm->core_cache, - arm_algorithm_info->core_mode, i).name, context[i]); + ARMV4_5_CORE_REG_MODE(arm->core_cache, + arm_algorithm_info->core_mode, i).name, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, - arm_algorithm_info->core_mode, i).value, 0, 32, context[i]); - ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).valid = 1; - ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).dirty = 1; + arm_algorithm_info->core_mode, i).value, 0, 32, context[i]); + ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, + i).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, + i).dirty = 1; } } @@ -1303,9 +1270,26 @@ int armv4_5_run_algorithm_inner(struct target *target, return retval; } -int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) +int armv4_5_run_algorithm(struct target *target, + int num_mem_params, + struct mem_param *mem_params, + int num_reg_params, + struct reg_param *reg_params, + uint32_t entry_point, + uint32_t exit_point, + int timeout_ms, + void *arch_info) { - return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion); + return armv4_5_run_algorithm_inner(target, + num_mem_params, + mem_params, + num_reg_params, + reg_params, + entry_point, + exit_point, + timeout_ms, + arch_info, + armv4_5_run_algorithm_completion); } /** @@ -1313,7 +1297,7 @@ int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_ * */ int arm_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *checksum) + uint32_t address, uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; struct arm_algorithm armv4_5_info; @@ -1414,7 +1398,7 @@ int arm_checksum_memory(struct target *target, * */ int arm_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *blank) + uint32_t address, uint32_t count, uint32_t *blank) { struct working_area *check_algorithm; struct reg_param reg_params[3]; @@ -1444,7 +1428,7 @@ int arm_blank_check_memory(struct target *target, for (i = 0; i < ARRAY_SIZE(check_code); i++) { retval = target_write_u32(target, check_algorithm->address - + i * sizeof(uint32_t), + + i * sizeof(uint32_t), check_code[i]); if (retval != ERROR_OK) return retval; @@ -1506,18 +1490,18 @@ static int arm_full_context(struct target *target) } static int arm_default_mrc(struct target *target, int cpnum, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, - uint32_t *value) + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { LOG_ERROR("%s doesn't implement MRC", target_type_name(target)); return ERROR_FAIL; } static int arm_default_mcr(struct target *target, int cpnum, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, - uint32_t value) + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { LOG_ERROR("%s doesn't implement MCR", target_type_name(target)); return ERROR_FAIL; diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index bacdb72..f63f5af 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARMV4_5_H #define ARMV4_5_H @@ -42,7 +43,7 @@ enum arm_mode armv4_5_number_to_mode(int number); extern const int armv4_5_core_reg_map[8][17]; #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \ - cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]] + (cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]) /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */ enum { ARMV4_5_CPSR = 31, }; diff --git a/src/target/armv4_5_cache.c b/src/target/armv4_5_cache.c index dcbcef3..d231950 100644 --- a/src/target/armv4_5_cache.c +++ b/src/target/armv4_5_cache.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -37,16 +38,13 @@ int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common len = (cache_type_reg & 0x3000) >> 12; multiplier = 2 + M; - if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */ - { + if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */ { /* cache is present */ cache->d_u_size.linelen = 1 << (len + 3); cache->d_u_size.associativity = multiplier << (assoc - 1); cache->d_u_size.nsets = 1 << (size + 6 - assoc - len); cache->d_u_size.cachesize = multiplier << (size + 8); - } - else - { + } else { /* cache is absent */ cache->d_u_size.linelen = -1; cache->d_u_size.associativity = -1; @@ -54,43 +52,35 @@ int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common cache->d_u_size.cachesize = -1; } - if (cache->separate) - { + if (cache->separate) { size = (cache_type_reg & 0x1c0) >> 6; assoc = (cache_type_reg & 0x38) >> 3; M = (cache_type_reg & 0x4) >> 2; len = (cache_type_reg & 0x3); multiplier = 2 + M; - if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */ - { + if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */ { /* cache is present */ cache->i_size.linelen = 1 << (len + 3); cache->i_size.associativity = multiplier << (assoc - 1); cache->i_size.nsets = 1 << (size + 6 - assoc - len); cache->i_size.cachesize = multiplier << (size + 8); - } - else - { + } else { /* cache is absent */ cache->i_size.linelen = -1; cache->i_size.associativity = -1; cache->i_size.nsets = -1; cache->i_size.cachesize = -1; } - } - else - { + } else cache->i_size = cache->d_u_size; - } return ERROR_OK; } int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx, struct armv4_5_cache_common *armv4_5_cache) { - if (armv4_5_cache->ctype == -1) - { + if (armv4_5_cache->ctype == -1) { command_print(cmd_ctx, "cache not yet identified"); return ERROR_OK; } diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h index c529b45..fc5e2c7 100644 --- a/src/target/armv4_5_cache.h +++ b/src/target/armv4_5_cache.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARMV4_5_CACHE_H #define ARMV4_5_CACHE_H @@ -24,16 +25,14 @@ struct command_context; -struct armv4_5_cachesize -{ +struct armv4_5_cachesize { int linelen; int associativity; int nsets; int cachesize; }; -struct armv4_5_cache_common -{ +struct armv4_5_cache_common { int ctype; /* specify supported cache operations */ int separate; /* separate caches or unified cache */ struct armv4_5_cachesize d_u_size; /* data cache */ @@ -50,8 +49,7 @@ int armv4_5_cache_state(uint32_t cp15_control_reg, int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx, struct armv4_5_cache_common *armv4_5_cache); -enum -{ +enum { ARMV4_5_D_U_CACHE_ENABLED = 0x4, ARMV4_5_I_CACHE_ENABLED = 0x1000, ARMV4_5_WRITE_BUFFER_ENABLED = 0x8, diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c index 5415e83..c8dc560 100644 --- a/src/target/armv4_5_mmu.c +++ b/src/target/armv4_5_mmu.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -25,8 +26,8 @@ #include "target.h" #include "armv4_5_mmu.h" - -int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val) +int armv4_5_mmu_translate_va(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val) { uint32_t first_lvl_descriptor = 0x0; uint32_t second_lvl_descriptor = 0x0; @@ -34,62 +35,55 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a int retval; retval = armv4_5_mmu->get_ttb(target, &ttb); if (retval != ERROR_OK) - return retval; + return retval; retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), - 4, 1, (uint8_t*)&first_lvl_descriptor); + 4, 1, (uint8_t *)&first_lvl_descriptor); if (retval != ERROR_OK) - return retval; - first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor); + return retval; + first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor); LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor); - if ((first_lvl_descriptor & 0x3) == 0) - { + if ((first_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } - if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) - { + if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } - if ((first_lvl_descriptor & 0x3) == 2) - { + if ((first_lvl_descriptor & 0x3) == 2) { /* section descriptor */ *cb = (first_lvl_descriptor & 0xc) >> 2; *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff); return ERROR_OK; } - if ((first_lvl_descriptor & 0x3) == 1) - { + if ((first_lvl_descriptor & 0x3) == 1) { /* coarse page table */ retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), - 4, 1, (uint8_t*)&second_lvl_descriptor); + 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; - } - else if ((first_lvl_descriptor & 0x3) == 3) - { + } else if ((first_lvl_descriptor & 0x3) == 3) { /* fine page table */ retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8), - 4, 1, (uint8_t*)&second_lvl_descriptor); + 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; } - second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor); + second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor); LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor); - if ((second_lvl_descriptor & 0x3) == 0) - { + if ((second_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } @@ -97,22 +91,19 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a /* cacheable/bufferable is always specified in bits 3-2 */ *cb = (second_lvl_descriptor & 0xc) >> 2; - if ((second_lvl_descriptor & 0x3) == 1) - { + if ((second_lvl_descriptor & 0x3) == 1) { /* large page descriptor */ *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff); return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 2) - { + if ((second_lvl_descriptor & 0x3) == 2) { /* small page descriptor */ *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff); return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 3) - { + if ((second_lvl_descriptor & 0x3) == 3) { /* tiny page descriptor */ *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff); return ERROR_OK; @@ -123,7 +114,9 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a return ERROR_TARGET_TRANSLATION_FAULT; } -int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int armv4_5_mmu_read_physical(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -132,24 +125,26 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common * /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; retval = armv4_5_mmu->read_memory(target, address, size, count, buffer); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* reenable MMU / cache */ retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; return retval; } -int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) +int armv4_5_mmu_write_physical(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; @@ -158,18 +153,18 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common /* disable MMU and data (or unified) cache */ retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; retval = armv4_5_mmu->write_memory(target, address, size, count, buffer); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* reenable MMU / cache */ retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled, armv4_5_mmu->armv4_5_cache.d_u_cache_enabled, armv4_5_mmu->armv4_5_cache.i_cache_enabled); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; return retval; diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h index 937a90e..412be6b 100644 --- a/src/target/armv4_5_mmu.h +++ b/src/target/armv4_5_mmu.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARMV4_5_MMU_H #define ARMV4_5_MMU_H @@ -24,8 +25,7 @@ struct target; -struct armv4_5_mmu_common -{ +struct armv4_5_mmu_common { int (*get_ttb)(struct target *target, uint32_t *result); int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer); @@ -48,8 +48,7 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer); -enum -{ +enum { ARMV4_5_MMU_ENABLED = 0x1, ARMV4_5_ALIGNMENT_CHECK = 0x2, ARMV4_5_MMU_S_BIT = 0x100, diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 2ef370b..48fdf8b 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -18,6 +18,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -79,9 +80,9 @@ static void armv7a_show_fault_registers(struct target *target) goto done; LOG_USER("Data fault registers DFSR: %8.8" PRIx32 - ", DFAR: %8.8" PRIx32, dfsr, dfar); + ", DFAR: %8.8" PRIx32, dfsr, dfar); LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32 - ", IFAR: %8.8" PRIx32, ifsr, ifar); + ", IFAR: %8.8" PRIx32, ifsr, ifar); done: /* (void) */ dpm->finish(dpm); @@ -93,29 +94,28 @@ static int armv7a_read_ttbcr(struct target *target) struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t ttbcr; int retval = dpm->prepare(dpm); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/ retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 0, 0, 2, 0, 2), &ttbcr); - if (retval!=ERROR_OK) goto done; - armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7)!=0)? 1: 0; - armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 -((ttbcr & 0x7))); + if (retval != ERROR_OK) + goto done; + armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0; + armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7))); #if 0 - LOG_INFO("ttb1 %s ,ttb0_mask %x", - armv7a->armv7a_mmu.ttbr1_used ? "used":"not used", - armv7a->armv7a_mmu.ttbr0_mask); + LOG_INFO("ttb1 %s ,ttb0_mask %x", + armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used", + armv7a->armv7a_mmu.ttbr0_mask); #endif - if (armv7a->armv7a_mmu.ttbr1_used == 1) - { + if (armv7a->armv7a_mmu.ttbr1_used == 1) { LOG_INFO("SVC access above %x", - (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)); + (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)); armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask; - } - else - { + } else { /* fix me , default is hard coded LINUX border */ - armv7a->armv7a_mmu.os_border = 0xc0000000; + armv7a->armv7a_mmu.os_border = 0xc0000000; } done: dpm->finish(dpm); @@ -131,11 +131,11 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) int retval; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; - uint32_t ttb = 0; /* default ttb0 */ - if (armv7a->armv7a_mmu.ttbr1_used == -1) armv7a_read_ttbcr(target); + uint32_t ttb = 0; /* default ttb0 */ + if (armv7a->armv7a_mmu.ttbr1_used == -1) + armv7a_read_ttbcr(target); if ((armv7a->armv7a_mmu.ttbr1_used) && - (va > (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask))) - { + (va > (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask))) { /* select ttb 1 */ ttb = 1; } @@ -151,74 +151,65 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) return retval; retval = armv7a->armv7a_mmu.read_physical_memory(target, (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18), - 4, 1, (uint8_t*)&first_lvl_descriptor); + 4, 1, (uint8_t *)&first_lvl_descriptor); if (retval != ERROR_OK) return retval; - first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*) + first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *) &first_lvl_descriptor); /* reuse armv4_5 piece of code, specific armv7a changes may come later */ LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor); - if ((first_lvl_descriptor & 0x3) == 0) - { + if ((first_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } - if ((first_lvl_descriptor & 0x3) == 2) - { + if ((first_lvl_descriptor & 0x3) == 2) { /* section descriptor */ *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff); return ERROR_OK; } - if ((first_lvl_descriptor & 0x3) == 1) - { + if ((first_lvl_descriptor & 0x3) == 1) { /* coarse page table */ retval = armv7a->armv7a_mmu.read_physical_memory(target, (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10), - 4, 1, (uint8_t*)&second_lvl_descriptor); + 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; - } - else if ((first_lvl_descriptor & 0x3) == 3) - { + } else if ((first_lvl_descriptor & 0x3) == 3) { /* fine page table */ retval = armv7a->armv7a_mmu.read_physical_memory(target, (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8), - 4, 1, (uint8_t*)&second_lvl_descriptor); + 4, 1, (uint8_t *)&second_lvl_descriptor); if (retval != ERROR_OK) return retval; } - second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*) + second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *) &second_lvl_descriptor); LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor); - if ((second_lvl_descriptor & 0x3) == 0) - { + if ((second_lvl_descriptor & 0x3) == 0) { LOG_ERROR("Address translation failure"); return ERROR_TARGET_TRANSLATION_FAULT; } - if ((second_lvl_descriptor & 0x3) == 1) - { + if ((second_lvl_descriptor & 0x3) == 1) { /* large page descriptor */ *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff); return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 2) - { + if ((second_lvl_descriptor & 0x3) == 2) { /* small page descriptor */ *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff); return ERROR_OK; } - if ((second_lvl_descriptor & 0x3) == 3) - { + if ((second_lvl_descriptor & 0x3) == 3) { *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff); return ERROR_OK; } @@ -231,69 +222,80 @@ done: return retval; } - /* V7 method VA TO PA */ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, - uint32_t *val, int meminfo) + uint32_t *val, int meminfo) { int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t virt = va & ~0xfff; - uint32_t NOS,NS,INNER,OUTER; + uint32_t NOS, NS, INNER, OUTER; *val = 0xdeadbeef; retval = dpm->prepare(dpm); if (retval != ERROR_OK) goto done; - /* mmu must be enable in order to get a correct translation */ - /* use VA to PA CP15 register for conversion */ + /* mmu must be enable in order to get a correct translation + * use VA to PA CP15 register for conversion */ retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 8, 0), virt); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 0, 0, 7, 4, 0), val); /* decode memory attribute */ - NOS = (*val >> 10) & 1; /* Not Outer shareable */ - NS = (*val >> 9) & 1; /* Non secure */ + NOS = (*val >> 10) & 1; /* Not Outer shareable */ + NS = (*val >> 9) & 1; /* Non secure */ INNER = (*val >> 4) & 0x7; OUTER = (*val >> 2) & 0x3; - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; *val = (*val & ~0xfff) + (va & 0xfff); if (*val == va) LOG_WARNING("virt = phys : MMU disable !!"); - if (meminfo) - { + if (meminfo) { LOG_INFO("%x : %x %s outer shareable %s secured", - va, *val, - NOS == 1 ? "not" : " ", - NS == 1 ? "not" :""); + va, *val, + NOS == 1 ? "not" : " ", + NS == 1 ? "not" : ""); switch (OUTER) { - case 0 : LOG_INFO("outer: Non-Cacheable"); - break; - case 1 : LOG_INFO("outer: Write-Back, Write-Allocate"); - break; - case 2 : LOG_INFO("outer: Write-Through, No Write-Allocate"); - break; - case 3 : LOG_INFO("outer: Write-Back, no Write-Allocate"); - break; + case 0: + LOG_INFO("outer: Non-Cacheable"); + break; + case 1: + LOG_INFO("outer: Write-Back, Write-Allocate"); + break; + case 2: + LOG_INFO("outer: Write-Through, No Write-Allocate"); + break; + case 3: + LOG_INFO("outer: Write-Back, no Write-Allocate"); + break; } switch (INNER) { - case 0 : LOG_INFO("inner: Non-Cacheable"); - break; - case 1 : LOG_INFO("inner: Strongly-ordered"); - break; - case 3 : LOG_INFO("inner: Device"); - break; - case 5 : LOG_INFO("inner: Write-Back, Write-Allocate"); - break; - case 6 : LOG_INFO("inner: Write-Through"); - break; - case 7 : LOG_INFO("inner: Write-Back, no Write-Allocate"); - - default: LOG_INFO("inner: %x ???",INNER); + case 0: + LOG_INFO("inner: Non-Cacheable"); + break; + case 1: + LOG_INFO("inner: Strongly-ordered"); + break; + case 3: + LOG_INFO("inner: Device"); + break; + case 5: + LOG_INFO("inner: Write-Back, Write-Allocate"); + break; + case 6: + LOG_INFO("inner: Write-Through"); + break; + case 7: + LOG_INFO("inner: Write-Back, no Write-Allocate"); + + default: + LOG_INFO("inner: %x ???", INNER); } } @@ -304,27 +306,26 @@ done: } static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx, - struct armv7a_cache_common *armv7a_cache) + struct armv7a_cache_common *armv7a_cache) { - if (armv7a_cache->ctype == -1) - { + if (armv7a_cache->ctype == -1) { command_print(cmd_ctx, "cache not yet identified"); return ERROR_OK; } command_print(cmd_ctx, - "D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", - armv7a_cache->d_u_size.linelen, - armv7a_cache->d_u_size.associativity, - armv7a_cache->d_u_size.nsets, - armv7a_cache->d_u_size.cachesize); + "D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + armv7a_cache->d_u_size.linelen, + armv7a_cache->d_u_size.associativity, + armv7a_cache->d_u_size.nsets, + armv7a_cache->d_u_size.cachesize); command_print(cmd_ctx, - "I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", - armv7a_cache->i_size.linelen, - armv7a_cache->i_size.associativity, - armv7a_cache->i_size.nsets, - armv7a_cache->i_size.cachesize); + "I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + armv7a_cache->i_size.linelen, + armv7a_cache->i_size.associativity, + armv7a_cache->i_size.nsets, + armv7a_cache->i_size.cachesize); return ERROR_OK; } @@ -338,28 +339,29 @@ static int _armv7a_flush_all_data(struct target *target) int32_t c_way, c_index = d_u_size->index; int retval; /* check that cache data is on at target halt */ - if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) - { + if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { LOG_INFO("flushed not performed :cache not on at target halt"); return ERROR_OK; } retval = dpm->prepare(dpm); - if (retval != ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; do { c_way = d_u_size->way; do { uint32_t value = (c_index << d_u_size->index_shift) | (c_way << d_u_size->way_shift); /* DCCISW */ - //LOG_INFO ("%d %d %x",c_way,c_index,value); + /* LOG_INFO ("%d %d %x",c_way,c_index,value); */ retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 14, 2), value); - if (retval!= ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; c_way -= 1; - } while (c_way >=0); + } while (c_way >= 0); c_index -= 1; - } while (c_index >=0); + } while (c_index >= 0); return retval; done: LOG_ERROR("flushed failed"); @@ -367,89 +369,85 @@ done: return retval; } -static int armv7a_flush_all_data( struct target * target) +static int armv7a_flush_all_data(struct target *target) { int retval = ERROR_FAIL; /* check that armv7a_cache is correctly identify */ struct armv7a_common *armv7a = target_to_armv7a(target); - if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) - { + if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) { LOG_ERROR("trying to flush un-identified cache"); return retval; } - if (target->smp) - { + if (target->smp) { /* look if all the other target have been flushed in order to flush level * 2 */ struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - if ((curr->state == TARGET_HALTED)) - { LOG_INFO("Wait flushing data l1 on core %d",curr->coreid); + if ((curr->state == TARGET_HALTED)) { + LOG_INFO("Wait flushing data l1 on core %d", curr->coreid); retval = _armv7a_flush_all_data(curr); } head = head->next; } - } - else retval = _armv7a_flush_all_data(target); + } else + retval = _armv7a_flush_all_data(target); return retval; } - /* L2 is not specific to armv7a a specific file is needed */ -static int armv7a_l2x_flush_all_data(struct target * target) +static int armv7a_l2x_flush_all_data(struct target *target) { -#define L2X0_CLEAN_INV_WAY 0x7FC +#define L2X0_CLEAN_INV_WAY 0x7FC int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache*) + struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) (armv7a->armv7a_mmu.armv7a_cache.l2_cache); uint32_t base = l2x_cache->base; uint32_t l2_way = l2x_cache->way; - uint32_t l2_way_val = (1<<l2_way) -1; + uint32_t l2_way_val = (1 << l2_way) - 1; retval = armv7a_flush_all_data(target); - if (retval!=ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; retval = target->type->write_phys_memory(target, (uint32_t)(base+(uint32_t)L2X0_CLEAN_INV_WAY), (uint32_t)4, (uint32_t)1, - (uint8_t*)&l2_way_val); + (uint8_t *)&l2_way_val); return retval; } static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx, - struct armv7a_cache_common *armv7a_cache) + struct armv7a_cache_common *armv7a_cache) { - struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache*) - (armv7a_cache->l2_cache); + struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *) + (armv7a_cache->l2_cache); - if (armv7a_cache->ctype == -1) - { + if (armv7a_cache->ctype == -1) { command_print(cmd_ctx, "cache not yet identified"); return ERROR_OK; } command_print(cmd_ctx, - "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", armv7a_cache->d_u_size.linelen, armv7a_cache->d_u_size.associativity, armv7a_cache->d_u_size.nsets, armv7a_cache->d_u_size.cachesize); command_print(cmd_ctx, - "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", + "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes", armv7a_cache->i_size.linelen, armv7a_cache->i_size.associativity, armv7a_cache->i_size.nsets, armv7a_cache->i_size.cachesize); - command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways", - l2x_cache->base, l2x_cache->way); + command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways", + l2x_cache->base, l2x_cache->way); return ERROR_OK; @@ -469,34 +467,28 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t /*LOG_INFO("cache l2 initialized base %x way %d", l2x_cache->base,l2x_cache->way);*/ if (armv7a->armv7a_mmu.armv7a_cache.l2_cache) - { LOG_INFO("cache l2 already initialized\n"); - } - armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void*) l2x_cache; + armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache; /* initialize l1 / l2x cache function */ armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = armv7a_l2x_flush_all_data; armv7a->armv7a_mmu.armv7a_cache.display_cache_info = armv7a_handle_l2x_cache_info_command; - /* initialize all target in this cluster (smp target)*/ - /* l2 cache must be configured after smp declaration */ - while(head != (struct target_list*)NULL) - { + /* initialize all target in this cluster (smp target) + * l2 cache must be configured after smp declaration */ + while (head != (struct target_list *)NULL) { curr = head->target; - if (curr != target) - { + if (curr != target) { armv7a = target_to_armv7a(curr); if (armv7a->armv7a_mmu.armv7a_cache.l2_cache) - { LOG_ERROR("smp target : cache l2 already initialized\n"); - } - armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void*) l2x_cache; + armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache; armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = armv7a_l2x_flush_all_data; armv7a->armv7a_mmu.armv7a_cache.display_cache_info = armv7a_handle_l2x_cache_info_command; } - head = head -> next; + head = head->next; } return JIM_OK; } @@ -504,33 +496,29 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t COMMAND_HANDLER(handle_cache_l2x) { struct target *target = get_current_target(CMD_CTX); - uint32_t base, way; -switch (CMD_ARGC) { - case 0: - return ERROR_COMMAND_SYNTAX_ERROR; - break; - case 2: - //command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); - - - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way); - - /* AP address is in bits 31:24 of DP_SELECT */ - armv7a_l2x_cache_init(target, base, way); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + uint32_t base, way; + switch (CMD_ARGC) { + case 0: + return ERROR_COMMAND_SYNTAX_ERROR; + break; + case 2: + /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */ + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way); + + /* AP address is in bits 31:24 of DP_SELECT */ + armv7a_l2x_cache_init(target, base, way); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } -return ERROR_OK; + return ERROR_OK; } - int armv7a_handle_cache_info_command(struct command_context *cmd_ctx, - struct armv7a_cache_common *armv7a_cache) + struct armv7a_cache_common *armv7a_cache) { - if (armv7a_cache->ctype == -1) - { + if (armv7a_cache->ctype == -1) { command_print(cmd_ctx, "cache not yet identified"); return ERROR_OK; } @@ -540,35 +528,34 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx, return ERROR_OK; } - /* retrieve core id cluster id */ static int armv7a_read_mpidr(struct target *target) { - int retval = ERROR_FAIL; + int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; - uint32_t mpidr; + uint32_t mpidr; retval = dpm->prepare(dpm); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/ retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 0, 0, 0, 0, 5), &mpidr); - if (retval!=ERROR_OK) goto done; - if (mpidr & 1<<31) - { + if (retval != ERROR_OK) + goto done; + if (mpidr & 1<<31) { armv7a->multi_processor_system = (mpidr >> 30) & 1; armv7a->cluster_id = (mpidr >> 8) & 0xf; armv7a->cpu_id = mpidr & 0x3; LOG_INFO("%s cluster %x core %x %s", target->cmd_name, - armv7a->cluster_id, - armv7a->cpu_id, - armv7a->multi_processor_system == 0 ? "multi core": "mono core"); + armv7a->cluster_id, + armv7a->cpu_id, + armv7a->multi_processor_system == 0 ? "multi core" : "mono core"); - } - else - LOG_ERROR("mpdir not in multiprocessor format"); + } else + LOG_ERROR("mpdir not in multiprocessor format"); done: dpm->finish(dpm); @@ -577,138 +564,149 @@ done: } - int armv7a_identify_cache(struct target *target) { /* read cache descriptor */ int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm_dpm *dpm = armv7a->arm.dpm; - uint32_t cache_selected,clidr; + uint32_t cache_selected, clidr; uint32_t cache_i_reg, cache_d_reg; struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); armv7a_read_ttbcr(target); retval = dpm->prepare(dpm); - if (retval!=ERROR_OK) goto done; - /* retrieve CLIDR */ - /* mrc p15, 1, r0, c0, c0, 1 @ read clidr */ + if (retval != ERROR_OK) + goto done; + /* retrieve CLIDR + * mrc p15, 1, r0, c0, c0, 1 @ read clidr */ retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 1, 0, 0, 0, 1), &clidr); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; clidr = (clidr & 0x7000000) >> 23; - LOG_INFO("number of cache level %d",clidr /2 ); - if ((clidr /2) > 1) - { - // FIXME not supported present in cortex A8 and later - // in cortex A7, A15 + LOG_INFO("number of cache level %d", clidr / 2); + if ((clidr / 2) > 1) { + /* FIXME not supported present in cortex A8 and later */ + /* in cortex A7, A15 */ LOG_ERROR("cache l2 present :not supported"); } - /* retrieve selected cache */ - /* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */ + /* retrieve selected cache + * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */ retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 2, 0, 0, 0, 0), &cache_selected); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; retval = armv7a->arm.mrc(target, 15, 2, 0, /* op1, op2 */ 0, 0, /* CRn, CRm */ &cache_selected); - if (retval!=ERROR_OK) goto done; - /* select instruction cache*/ - /* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */ - /* [0] : 1 instruction cache selection , 0 data cache selection */ + if (retval != ERROR_OK) + goto done; + /* select instruction cache + * MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR + * [0] : 1 instruction cache selection , 0 data cache selection */ retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MRC(15, 2, 0, 0, 0, 0), 1); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; - /* read CCSIDR*/ - /* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR */ - /* [2:0] line size 001 eight word per line */ - /* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */ + /* read CCSIDR + * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR + * [2:0] line size 001 eight word per line + * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */ retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 1, 0, 0, 0, 0), &cache_i_reg); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; /* select data cache*/ retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MRC(15, 2, 0, 0, 0, 0), 0); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRC(15, 1, 0, 0, 0, 0), &cache_d_reg); - if (retval!=ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; /* restore selected cache */ dpm->instr_write_data_r0(dpm, - ARMV4_5_MRC(15, 2, 0, 0, 0, 0), - cache_selected); + ARMV4_5_MRC(15, 2, 0, 0, 0, 0), + cache_selected); - if (retval != ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; dpm->finish(dpm); - // put fake type + /* put fake type */ cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7); cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8; cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff; - cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) +1; + cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1; /* compute info for set way operation on cache */ cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4; - cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff; - cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff); - cache->d_u_size.way_shift = cache->d_u_size.way+1; + cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff; + cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff); + cache->d_u_size.way_shift = cache->d_u_size.way + 1; { - int i=0; - while(((cache->d_u_size.way_shift >> i) & 1)!=1) i++; + int i = 0; + while (((cache->d_u_size.way_shift >> i) & 1) != 1) + i++; cache->d_u_size.way_shift = 32-i; } - /*LOG_INFO("data cache index %d << %d, way %d << %d", +#if 0 + LOG_INFO("data cache index %d << %d, way %d << %d", cache->d_u_size.index, cache->d_u_size.index_shift, - cache->d_u_size.way, cache->d_u_size.way_shift); + cache->d_u_size.way, + cache->d_u_size.way_shift); LOG_INFO("data cache %d bytes %d KBytes asso %d ways", cache->d_u_size.linelen, cache->d_u_size.cachesize, - cache->d_u_size.associativity - );*/ + cache->d_u_size.associativity); +#endif cache->i_size.linelen = 16 << (cache_i_reg & 0x7); - cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) +1; + cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1; cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff; cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8; /* compute info for set way operation on cache */ cache->i_size.index_shift = (cache_i_reg & 0x7) + 4; - cache->i_size.index = (cache_i_reg >> 13) & 0x7fff; - cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff); - cache->i_size.way_shift = cache->i_size.way+1; + cache->i_size.index = (cache_i_reg >> 13) & 0x7fff; + cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff); + cache->i_size.way_shift = cache->i_size.way + 1; { - int i=0; - while(((cache->i_size.way_shift >> i) & 1)!=1) i++; + int i = 0; + while (((cache->i_size.way_shift >> i) & 1) != 1) + i++; cache->i_size.way_shift = 32-i; } - /*LOG_INFO("instruction cache index %d << %d, way %d << %d", +#if 0 + LOG_INFO("instruction cache index %d << %d, way %d << %d", cache->i_size.index, cache->i_size.index_shift, - cache->i_size.way, cache->i_size.way_shift); + cache->i_size.way, cache->i_size.way_shift); LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways", cache->i_size.linelen, cache->i_size.cachesize, - cache->i_size.associativity - );*/ + cache->i_size.associativity); +#endif /* if no l2 cache initialize l1 data cache flush function function */ - if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) - { + if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) { armv7a->armv7a_mmu.armv7a_cache.display_cache_info = armv7a_handle_inner_cache_info_command; armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = armv7a_flush_all_data; } - armv7a->armv7a_mmu.armv7a_cache.ctype = 0; + armv7a->armv7a_mmu.armv7a_cache.ctype = 0; done: dpm->finish(dpm); @@ -717,8 +715,6 @@ done: } - - int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a) { struct arm *arm = &armv7a->arm; @@ -726,27 +722,25 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a) target->arch_info = &armv7a->arm; /* target is useful in all function arm v4 5 compatible */ armv7a->arm.target = target; - armv7a->arm.common_magic = ARM_COMMON_MAGIC; + armv7a->arm.common_magic = ARM_COMMON_MAGIC; armv7a->common_magic = ARMV7_COMMON_MAGIC; armv7a->armv7a_mmu.armv7a_cache.l2_cache = NULL; armv7a->armv7a_mmu.armv7a_cache.ctype = -1; armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL; - armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL; + armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL; return ERROR_OK; } int armv7a_arch_state(struct target *target) { - static const char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *arm = &armv7a->arm; - if (armv7a->common_magic != ARMV7_COMMON_MAGIC) - { + if (armv7a->common_magic != ARMV7_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv7A target"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -754,15 +748,15 @@ int armv7a_arch_state(struct target *target) arm_arch_state(target); LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", - state[armv7a->armv7a_mmu.mmu_enabled], - state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], - state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); + state[armv7a->armv7a_mmu.mmu_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], + state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) armv7a->dpm.wp_pc); + (unsigned) armv7a->dpm.wp_pc); return ERROR_OK; } @@ -776,7 +770,7 @@ static const struct command_registration l2_cache_commands[] = { "", .usage = "[base_addr] [number_of_way]", }, - COMMAND_REGISTRATION_DONE + COMMAND_REGISTRATION_DONE }; @@ -801,4 +795,3 @@ const struct command_registration armv7a_command_handlers[] = { }, COMMAND_REGISTRATION_DONE }; - diff --git a/src/target/armv7a.h b/src/target/armv7a.h index bfc0e70..176de53 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARMV7A_H #define ARMV7A_H @@ -25,12 +26,10 @@ #include "armv4_5_cache.h" #include "arm_dpm.h" -enum -{ +enum { ARM_PC = 15, ARM_CPSR = 16 -} -; +}; #define ARMV7_COMMON_MAGIC 0x0A450999 @@ -49,8 +48,7 @@ struct armv7a_l2x_cache { uint32_t way; }; -struct armv7a_cachesize -{ +struct armv7a_cachesize { uint32_t level_num; /* cache dimensionning */ uint32_t linelen; @@ -64,38 +62,32 @@ struct armv7a_cachesize uint32_t way_shift; }; - -struct armv7a_cache_common -{ +struct armv7a_cache_common { int ctype; struct armv7a_cachesize d_u_size; /* data cache */ - struct armv7a_cachesize i_size; /* instruction cache */ + struct armv7a_cachesize i_size; /* instruction cache */ int i_cache_enabled; int d_u_cache_enabled; /* l2 external unified cache if some */ void *l2_cache; - int (*flush_all_data_cache)(struct target *target); - int (*display_cache_info)(struct command_context *cmd_ctx, + int (*flush_all_data_cache)(struct target *target); + int (*display_cache_info)(struct command_context *cmd_ctx, struct armv7a_cache_common *armv7a_cache); }; - -struct armv7a_mmu_common -{ - /* following field mmu working way */ +struct armv7a_mmu_common { + /* following field mmu working way */ int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */ uint32_t ttbr0_mask;/* masked to be used */ uint32_t os_border; - int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); + int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer); struct armv7a_cache_common armv7a_cache; uint32_t mmu_enabled; }; - - -struct armv7a_common -{ +struct armv7a_common { struct arm arm; int common_magic; struct reg_cache *core_cache; @@ -124,8 +116,7 @@ struct armv7a_common static inline struct armv7a_common * target_to_armv7a(struct target *target) { - return container_of(target->arch_info, struct armv7a_common, - arm); + return container_of(target->arch_info, struct armv7a_common, arm); } /* register offsets from armv7a.debug_base */ @@ -169,7 +160,7 @@ int armv7a_arch_state(struct target *target); int armv7a_identify_cache(struct target *target); int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a); int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, - uint32_t *val,int meminfo); + uint32_t *val, int meminfo); int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val); int armv7a_handle_cache_info_command(struct command_context *cmd_ctx, diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 6c1732e..258653e 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -30,6 +30,7 @@ * ARM DDI 0405C (September 2008) * * * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -39,19 +40,16 @@ #include "algorithm.h" #include "register.h" - #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */ -char *armv7m_mode_strings[] = -{ +char *armv7m_mode_strings[] = { "Thread", "Thread (User)", "Handler", }; -static char *armv7m_exception_strings[] = -{ +static char *armv7m_exception_strings[] = { "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "SVCall", @@ -79,8 +77,7 @@ const int armv7m_msp_reg_map[17] = { #ifdef ARMV7_GDB_HACKS uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0}; -struct reg armv7m_gdb_dummy_cpsr_reg = -{ +struct reg armv7m_gdb_dummy_cpsr_reg = { .name = "GDB dummy cpsr register", .value = armv7m_gdb_dummy_cpsr_value, .dirty = 0, @@ -133,7 +130,7 @@ static const struct { { ARMV7M_CONTROL, "control", 2 }, }; -#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) +#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) /** * Restores target context using the cache of core registers set up @@ -149,12 +146,9 @@ int armv7m_restore_context(struct target *target) if (armv7m->pre_restore_context) armv7m->pre_restore_context(target); - for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) - { + for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { if (armv7m->core_cache->reg_list[i].dirty) - { armv7m->write_core_reg(target, i); - } } return ERROR_OK; @@ -189,9 +183,7 @@ static int armv7m_get_core_reg(struct reg *reg) struct armv7m_common *armv7m = target_to_armv7m(target); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } retval = armv7m->read_core_reg(target, armv7m_reg->num); @@ -205,9 +197,7 @@ static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf) uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; @@ -220,14 +210,17 @@ static int armv7m_read_core_reg(struct target *target, unsigned num) { uint32_t reg_value; int retval; - struct armv7m_core_reg * armv7m_core_reg; + struct armv7m_core_reg *armv7m_core_reg; struct armv7m_common *armv7m = target_to_armv7m(target); if (num >= ARMV7M_NUM_REGS) return ERROR_COMMAND_SYNTAX_ERROR; armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; - retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®_value); + retval = armv7m->load_core_reg_u32(target, + armv7m_core_reg->type, + armv7m_core_reg->num, + ®_value); buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value); armv7m->core_cache->reg_list[num].valid = 1; armv7m->core_cache->reg_list[num].dirty = 0; @@ -247,14 +240,16 @@ static int armv7m_write_core_reg(struct target *target, unsigned num) reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; - retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value); - if (retval != ERROR_OK) - { + retval = armv7m->store_core_reg_u32(target, + armv7m_core_reg->type, + armv7m_core_reg->num, + reg_value); + if (retval != ERROR_OK) { LOG_ERROR("JTAG failure"); armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid; return ERROR_JTAG_DEVICE_ERROR; } - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value); armv7m->core_cache->reg_list[num].valid = 1; armv7m->core_cache->reg_list[num].dirty = 0; @@ -273,7 +268,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int int i; *reg_list_size = 26; - *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); /* * GDB register packet format for ARM: @@ -283,9 +278,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int * - CPSR */ for (i = 0; i < 16; i++) - { (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; - } for (i = 16; i < 24; i++) (*reg_list)[i] = &arm_gdb_dummy_fp_reg; @@ -297,7 +290,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int /* ARMV7M is always in thumb mode, try to make GDB understand this * if it does not support this arch */ - *((char*)armv7m->arm.pc->value) |= 1; + *((char *)armv7m->arm.pc->value) |= 1; #else (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR]; #endif @@ -345,60 +338,60 @@ int armv7m_start_algorithm(struct target *target, /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint * at the exit point */ - if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) - { + if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { LOG_ERROR("current target isn't an ARMV7M target"); return ERROR_TARGET_INVALID; } - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - /* refresh core register cache */ - /* Not needed if core register cache is always consistent with target process state */ - for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) - { + /* refresh core register cache + * Not needed if core register cache is always consistent with target process state */ + for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); - armv7m_algorithm_info->context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); + armv7m_algorithm_info->context[i] = buf_get_u32( + armv7m->core_cache->reg_list[i].value, + 0, + 32); } - for (int i = 0; i < num_mem_params; i++) - { - // TODO: Write only out params - if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) + for (int i = 0; i < num_mem_params; i++) { + /* TODO: Write only out params */ + retval = target_write_buffer(target, mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) return retval; } - for (int i = 0; i < num_reg_params; i++) - { - struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); -// uint32_t regvalue; + for (int i = 0; i < num_reg_params; i++) { + struct reg *reg = + register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); +/* uint32_t regvalue; */ - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + if (reg->size != reg_params[i].size) { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } -// regvalue = buf_get_u32(reg_params[i].value, 0, 32); +/* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */ armv7m_set_core_reg(reg, reg_params[i].value); } - if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) - { + if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, - 0, 1, armv7m_algorithm_info->core_mode); + 0, 1, armv7m_algorithm_info->core_mode); armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } @@ -424,58 +417,58 @@ int armv7m_wait_algorithm(struct target *target, /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint * at the exit point */ - if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) - { + if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { LOG_ERROR("current target isn't an ARMV7M target"); return ERROR_TARGET_INVALID; } retval = target_wait_state(target, TARGET_HALTED, timeout_ms); /* If the target fails to halt due to the breakpoint, force a halt */ - if (retval != ERROR_OK || target->state != TARGET_HALTED) - { - if ((retval = target_halt(target)) != ERROR_OK) + if (retval != ERROR_OK || target->state != TARGET_HALTED) { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) - { + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval != ERROR_OK) return retval; - } return ERROR_TARGET_TIMEOUT; } armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); - if (exit_point && (pc != exit_point)) - { - LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32 , pc, exit_point); + if (exit_point && (pc != exit_point)) { + LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32, + pc, + exit_point); return ERROR_TARGET_TIMEOUT; } /* Read memory values to mem_params[] */ - for (int i = 0; i < num_mem_params; i++) - { - if (mem_params[i].direction != PARAM_OUT) - if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) - { + for (int i = 0; i < num_mem_params; i++) { + if (mem_params[i].direction != PARAM_OUT) { + retval = target_read_buffer(target, mem_params[i].address, + mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) return retval; - } + } } /* Copy core register values to reg_params[] */ - for (int i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { - struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); + for (int i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction != PARAM_OUT) { + struct reg *reg = register_get_by_name(armv7m->core_cache, + reg_params[i].reg_name, + 0); - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + if (reg->size != reg_params[i].size) { + LOG_ERROR( + "BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -483,16 +476,15 @@ int armv7m_wait_algorithm(struct target *target, } } - for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) - { + for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { uint32_t regvalue; regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); - if (regvalue != armv7m_algorithm_info->context[i]) - { + if (regvalue != armv7m_algorithm_info->context[i]) { LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, - armv7m->core_cache->reg_list[i].name, armv7m_algorithm_info->context[i]); + armv7m->core_cache->reg_list[i].name, + armv7m_algorithm_info->context[i]); buf_set_u32(armv7m->core_cache->reg_list[i].value, - 0, 32, armv7m_algorithm_info->context[i]); + 0, 32, armv7m_algorithm_info->context[i]); armv7m->core_cache->reg_list[i].valid = 1; armv7m->core_cache->reg_list[i].dirty = 1; } @@ -555,8 +547,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target) (*cache_p) = cache; armv7m->core_cache = cache; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { arch_info[i].num = armv7m_regs[i].id; arch_info[i].target = target; arch_info[i].armv7m_common = armv7m; @@ -603,7 +594,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m) /** Generates a CRC32 checksum of a memory region. */ int armv7m_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* checksum) + uint32_t address, uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; struct armv7m_algorithm armv7m_info; @@ -618,27 +609,27 @@ int armv7m_checksum_memory(struct target *target, 0x460B, /* mov r3, r1 */ 0xF04F, 0x0400, /* mov r4, #0 */ 0xE013, /* b ncomp */ - /* nbyte: */ + /* nbyte: */ 0x5D11, /* ldrb r1, [r2, r4] */ 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */ 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */ 0xF04F, 0x0500, /* mov r5, #0 */ - /* loop: */ + /* loop: */ 0x2800, /* cmp r0, #0 */ 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */ 0xF105, 0x0501, /* add r5, r5, #1 */ 0x4630, /* mov r0, r6 */ 0xBFB8, /* it lt */ 0xEA86, 0x0007, /* eor r0, r6, r7 */ - 0x2D08, /* cmp r5, #8 */ + 0x2D08, /* cmp r5, #8 */ 0xD1F4, /* bne loop */ 0xF104, 0x0401, /* add r4, r4, #1 */ - /* ncomp: */ + /* ncomp: */ 0x429C, /* cmp r4, r3 */ 0xD1E9, /* bne nbyte */ - 0xBE00, /* bkpt #0 */ + 0xBE00, /* bkpt #0 */ 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */ }; @@ -650,7 +641,9 @@ int armv7m_checksum_memory(struct target *target, /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++) { - retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i]); + retval = target_write_u16(target, + crc_algorithm->address + i*sizeof(uint16_t), + cortex_m3_crc_code[i]); if (retval != ERROR_OK) goto cleanup; } @@ -667,8 +660,8 @@ int armv7m_checksum_memory(struct target *target, int timeout = 20000 * (1 + (count / (1024 * 1024))); retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, - crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6), - timeout, &armv7m_info); + crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6), + timeout, &armv7m_info); if (retval == ERROR_OK) *checksum = buf_get_u32(reg_params[0].value, 0, 32); @@ -686,7 +679,7 @@ cleanup: /** Checks whether a memory region is zeroed. */ int armv7m_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* blank) + uint32_t address, uint32_t count, uint32_t *blank) { struct working_area *erase_check_algorithm; struct reg_param reg_params[3]; @@ -694,25 +687,25 @@ int armv7m_blank_check_memory(struct target *target, int retval; uint32_t i; - static const uint16_t erase_check_code[] = - { + static const uint16_t erase_check_code[] = { /* loop: */ 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */ 0xEA02, 0x0203, /* and r2, r2, r3 */ 0x3901, /* subs r1, r1, #1 */ 0xD1F9, /* bne loop */ - 0xBE00, /* bkpt #0 */ + 0xBE00, /* bkpt #0 */ }; /* make sure we have a working area */ - if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) - { + if (target_alloc_working_area(target, sizeof(erase_check_code), + &erase_check_algorithm) != ERROR_OK) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) - target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]); + target_write_u16(target, + erase_check_algorithm->address + i*sizeof(uint16_t), + erase_check_code[i]); armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; armv7m_info.core_mode = ARMV7M_MODE_ANY; @@ -726,9 +719,15 @@ int armv7m_blank_check_memory(struct target *target, init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); buf_set_u32(reg_params[2].value, 0, 32, 0xff); - retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address, - erase_check_algorithm->address + (sizeof(erase_check_code) - 2), - 10000, &armv7m_info); + retval = target_run_algorithm(target, + 0, + NULL, + 3, + reg_params, + erase_check_algorithm->address, + erase_check_algorithm->address + (sizeof(erase_check_code) - 2), + 10000, + &armv7m_info); if (retval == ERROR_OK) *blank = buf_get_u32(reg_params[2].value, 0, 32); @@ -753,16 +752,13 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) * then we have to manually step over it, otherwise * the core will break again */ - if (target->debug_reason == DBG_REASON_BREAKPOINT) - { + if (target->debug_reason == DBG_REASON_BREAKPOINT) { uint16_t op; uint32_t pc = buf_get_u32(r->value, 0, 32); pc &= ~1; - if (target_read_u16(target, pc, &op) == ERROR_OK) - { - if ((op & 0xFF00) == 0xBE00) - { + if (target_read_u16(target, pc, &op) == ERROR_OK) { + if ((op & 0xFF00) == 0xBE00) { pc = buf_get_u32(r->value, 0, 32) + 2; buf_set_u32(r->value, 0, 32, pc); r->dirty = true; @@ -773,9 +769,8 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found) } } - if (inst_found) { + if (inst_found) *inst_found = result; - } return ERROR_OK; } diff --git a/src/target/armv7m.h b/src/target/armv7m.h index aef6b76..cee2b60 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ARMV7M_COMMON_H #define ARMV7M_COMMON_H @@ -39,9 +40,7 @@ extern uint8_t armv7m_gdb_dummy_cpsr_value[]; extern struct reg armv7m_gdb_dummy_cpsr_reg; #endif - -enum armv7m_mode -{ +enum armv7m_mode { ARMV7M_MODE_THREAD = 0, ARMV7M_MODE_USER_THREAD = 1, ARMV7M_MODE_HANDLER = 2, @@ -52,8 +51,7 @@ extern char *armv7m_mode_strings[]; extern const int armv7m_psp_reg_map[]; extern const int armv7m_msp_reg_map[]; -enum armv7m_regtype -{ +enum armv7m_regtype { ARMV7M_REGISTER_CORE_GP, ARMV7M_REGISTER_CORE_SP, ARMV7M_REGISTER_MEMMAP @@ -62,8 +60,7 @@ enum armv7m_regtype char *armv7m_exception_string(int number); /* offsets into armv7m core register cache */ -enum -{ +enum { /* for convenience, the first set of indices match * the Cortex-M3 DCRSR selectors */ @@ -100,8 +97,7 @@ enum #define ARMV7M_COMMON_MAGIC 0x2A452A45 -struct armv7m_common -{ +struct armv7m_common { struct arm arm; int common_magic; @@ -139,17 +135,15 @@ static inline bool is_armv7m(struct armv7m_common *armv7m) return armv7m->common_magic == ARMV7M_COMMON_MAGIC; } -struct armv7m_algorithm -{ +struct armv7m_algorithm { int common_magic; enum armv7m_mode core_mode; - uint32_t context[ARMV7M_CONTROL + 1]; //ARMV7M_NUM_REGS + uint32_t context[ARMV7M_CONTROL + 1]; /* ARMV7M_NUM_REGS */ }; -struct armv7m_core_reg -{ +struct armv7m_core_reg { uint32_t num; enum armv7m_regtype type; struct target *target; @@ -189,9 +183,9 @@ int armv7m_invalidate_core_regs(struct target *target); int armv7m_restore_context(struct target *target); int armv7m_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* checksum); + uint32_t address, uint32_t count, uint32_t *checksum); int armv7m_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* blank); + uint32_t address, uint32_t count, uint32_t *blank); int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found); diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index 635fe46..c8f0f8e 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -19,6 +19,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -34,15 +35,13 @@ #include "avr32_regs.h" #include "avr32_ap7k.h" -static char* avr32_core_reg_list[] = -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", +static char *avr32_core_reg_list[] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "sr" }; -static struct avr32_core_reg - avr32_core_reg_list_arch_info[AVR32NUMCOREREGS] = -{ +static struct avr32_core_reg + avr32_core_reg_list_arch_info[AVR32NUMCOREREGS] = { {0, NULL, NULL}, {1, NULL, NULL}, {2, NULL, NULL}, @@ -75,12 +74,9 @@ int avr32_ap7k_save_context(struct target *target) if (retval != ERROR_OK) return retval; - for (i = 0; i < AVR32NUMCOREREGS; i++) - { + for (i = 0; i < AVR32NUMCOREREGS; i++) { if (!ap7k->core_cache->reg_list[i].valid) - { avr32_read_core_reg(target, i); - } } return ERROR_OK; @@ -93,12 +89,9 @@ int avr32_ap7k_restore_context(struct target *target) /* get pointers to arch-specific information */ struct avr32_ap7k_common *ap7k = target_to_ap7k(target); - for (i = 0; i < AVR32NUMCOREREGS; i++) - { + for (i = 0; i < AVR32NUMCOREREGS; i++) { if (ap7k->core_cache->reg_list[i].dirty) - { avr32_write_core_reg(target, i); - } } /* write core regs */ @@ -137,7 +130,7 @@ static int avr32_write_core_reg(struct target *target, int num) reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32); ap7k->core_regs[num] = reg_value; - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value); + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value); ap7k->core_cache->reg_list[num].valid = 1; ap7k->core_cache->reg_list[num].dirty = 0; @@ -151,9 +144,7 @@ static int avr32_get_core_reg(struct reg *reg) struct target *target = avr32_reg->target; if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } retval = avr32_read_core_reg(target, avr32_reg->num); @@ -167,9 +158,7 @@ static int avr32_set_core_reg(struct reg *reg, uint8_t *buf) uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; @@ -190,7 +179,7 @@ static struct reg_cache *avr32_build_reg_cache(struct target *target) struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = malloc(sizeof(struct reg) * num_regs); - struct avr32_core_reg *arch_info = + struct avr32_core_reg *arch_info = malloc(sizeof(struct avr32_core_reg) * num_regs); int i; @@ -202,8 +191,7 @@ static struct reg_cache *avr32_build_reg_cache(struct target *target) (*cache_p) = cache; ap7k->core_cache = cache; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { arch_info[i] = avr32_core_reg_list_arch_info[i]; arch_info[i].target = target; arch_info[i].avr32_common = ap7k; @@ -253,31 +241,26 @@ static int avr32_ap7k_poll(struct target *target) return retval; /* check for processor halted */ - if (ds & OCDREG_DS_DBA) - { - if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) - { + if (ds & OCDREG_DS_DBA) { + if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { target->state = TARGET_HALTED; - if ((retval = avr32_ap7k_debug_entry(target)) != ERROR_OK) + retval = avr32_ap7k_debug_entry(target); + if (retval != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } - else if (target->state == TARGET_DEBUG_RUNNING) - { + } else if (target->state == TARGET_DEBUG_RUNNING) { target->state = TARGET_HALTED; - if ((retval = avr32_ap7k_debug_entry(target)) != ERROR_OK) + retval = avr32_ap7k_debug_entry(target); + if (retval != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - } - else - { + } else target->state = TARGET_RUNNING; - } return ERROR_OK; @@ -288,28 +271,21 @@ static int avr32_ap7k_halt(struct target *target) struct avr32_ap7k_common *ap7k = target_to_ap7k(target); LOG_DEBUG("target->state: %s", - target_state_name(target)); + target_state_name(target)); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - { LOG_WARNING("target was in unknown state when halt was requested"); - } - if (target->state == TARGET_RESET) - { - if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) - { + if (target->state == TARGET_RESET) { + if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; - } - else - { + } else { target->debug_reason = DBG_REASON_DBGRQ; return ERROR_OK; @@ -345,21 +321,19 @@ static int avr32_ap7k_soft_reset_halt(struct target *target) } static int avr32_ap7k_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) + uint32_t address, int handle_breakpoints, int debug_execution) { struct avr32_ap7k_common *ap7k = target_to_ap7k(target); struct breakpoint *breakpoint = NULL; uint32_t resume_pc; int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!debug_execution) - { + if (!debug_execution) { target_free_all_working_areas(target); /* avr32_ap7k_enable_breakpoints(target); @@ -368,24 +342,21 @@ static int avr32_ap7k_resume(struct target *target, int current, } /* current = 1: continue on current pc, otherwise continue at <address> */ - if (!current) - { + if (!current) { #if 0 if (retval != ERROR_OK) return retval; #endif } - resume_pc = - buf_get_u32(ap7k->core_cache->reg_list[AVR32_REG_PC].value, 0, 32); + resume_pc = buf_get_u32(ap7k->core_cache->reg_list[AVR32_REG_PC].value, 0, 32); avr32_ap7k_restore_context(target); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); #if 0 avr32_ap7k_unset_breakpoint(target, breakpoint); @@ -418,14 +389,11 @@ static int avr32_ap7k_resume(struct target *target, int current, /* registers are now invalid */ register_cache_invalidate(ap7k->core_cache); - if (!debug_execution) - { + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc); @@ -435,7 +403,7 @@ static int avr32_ap7k_resume(struct target *target, int current, } static int avr32_ap7k_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + uint32_t address, int handle_breakpoints) { LOG_ERROR("%s: implement me", __func__); @@ -450,7 +418,7 @@ static int avr32_ap7k_add_breakpoint(struct target *target, struct breakpoint *b } static int avr32_ap7k_remove_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { LOG_ERROR("%s: implement me", __func__); @@ -465,7 +433,7 @@ static int avr32_ap7k_add_watchpoint(struct target *target, struct watchpoint *w } static int avr32_ap7k_remove_watchpoint(struct target *target, - struct watchpoint *watchpoint) + struct watchpoint *watchpoint) { LOG_ERROR("%s: implement me", __func__); @@ -473,14 +441,16 @@ static int avr32_ap7k_remove_watchpoint(struct target *target, } static int avr32_ap7k_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { struct avr32_ap7k_common *ap7k = target_to_ap7k(target); - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + address, + size, + count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -492,33 +462,36 @@ static int avr32_ap7k_read_memory(struct target *target, uint32_t address, if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - switch (size) - { - case 4: - return avr32_jtag_read_memory32(&ap7k->jtag, address, count, (uint32_t*)(void *)buffer); - break; - case 2: - return avr32_jtag_read_memory16(&ap7k->jtag, address, count, (uint16_t*)(void *)buffer); - break; - case 1: - return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer); - break; - default: - break; + switch (size) { + case 4: + return avr32_jtag_read_memory32(&ap7k->jtag, address, count, + (uint32_t *)(void *)buffer); + break; + case 2: + return avr32_jtag_read_memory16(&ap7k->jtag, address, count, + (uint16_t *)(void *)buffer); + break; + case 1: + return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer); + break; + default: + break; } return ERROR_OK; } static int avr32_ap7k_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { struct avr32_ap7k_common *ap7k = target_to_ap7k(target); - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + address, + size, + count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -530,26 +503,27 @@ static int avr32_ap7k_write_memory(struct target *target, uint32_t address, if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - switch (size) - { - case 4: - return avr32_jtag_write_memory32(&ap7k->jtag, address, count, (uint32_t*)(void *)buffer); - break; - case 2: - return avr32_jtag_write_memory16(&ap7k->jtag, address, count, (uint16_t*)(void *)buffer); - break; - case 1: - return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer); - break; - default: - break; + switch (size) { + case 4: + return avr32_jtag_write_memory32(&ap7k->jtag, address, count, + (uint32_t *)(void *)buffer); + break; + case 2: + return avr32_jtag_write_memory16(&ap7k->jtag, address, count, + (uint16_t *)(void *)buffer); + break; + case 1: + return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer); + break; + default: + break; } return ERROR_OK; } static int avr32_ap7k_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { struct avr32_ap7k_common *ap7k = target_to_ap7k(target); @@ -561,7 +535,7 @@ static int avr32_ap7k_init_target(struct command_context *cmd_ctx, static int avr32_ap7k_target_create(struct target *target, Jim_Interp *interp) { struct avr32_ap7k_common *ap7k = calloc(1, sizeof(struct - avr32_ap7k_common)); + avr32_ap7k_common)); ap7k->common_magic = AP7k_COMMON_MAGIC; target->arch_info = ap7k; @@ -574,21 +548,18 @@ static int avr32_ap7k_examine(struct target *target) uint32_t devid, ds; struct avr32_ap7k_common *ap7k = target_to_ap7k(target); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { target_set_examined(target); avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DID, &devid); LOG_INFO("device id: %08x", devid); - avr32_ocd_setbits(&ap7k->jtag, AVR32_OCDREG_DC,OCDREG_DC_DBE); + avr32_ocd_setbits(&ap7k->jtag, AVR32_OCDREG_DC, OCDREG_DC_DBE); avr32_jtag_nexus_read(&ap7k->jtag, AVR32_OCDREG_DS, &ds); /* check for processor halted */ - if (ds & OCDREG_DS_DBA) - { + if (ds & OCDREG_DS_DBA) { LOG_INFO("target is halted"); target->state = TARGET_HALTED; - } - else + } else target->state = TARGET_RUNNING; } @@ -596,7 +567,7 @@ static int avr32_ap7k_examine(struct target *target) } static int avr32_ap7k_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { LOG_ERROR("%s: implement me", __func__); @@ -609,31 +580,28 @@ int avr32_ap7k_arch_state(struct target *target) struct avr32_ap7k_common *ap7k = target_to_ap7k(target); LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "", - debug_reason_name(target), ap7k->jtag.dpc); + debug_reason_name(target), ap7k->jtag.dpc); - return ERROR_OK; + return ERROR_OK; } int avr32_ap7k_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { #if 0 - /* get pointers to arch-specific information */ - int i; - - /* include floating point registers */ - *reg_list_size = AVR32NUMCOREREGS + AVR32NUMFPREGS; - *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); - - for (i = 0; i < AVR32NUMCOREREGS; i++) - { - (*reg_list)[i] = &mips32->core_cache->reg_list[i]; - } - - /* add dummy floating points regs */ - for (i = AVR32NUMCOREREGS; i < (AVR32NUMCOREREGS + AVR32NUMFPREGS); i++) - { - (*reg_list)[i] = &avr32_ap7k_gdb_dummy_fp_reg; - } + /* get pointers to arch-specific information */ + int i; + + /* include floating point registers */ + *reg_list_size = AVR32NUMCOREREGS + AVR32NUMFPREGS; + *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); + + for (i = 0; i < AVR32NUMCOREREGS; i++) + (*reg_list)[i] = &mips32->core_cache->reg_list[i]; + + /* add dummy floating points regs */ + for (i = AVR32NUMCOREREGS; i < (AVR32NUMCOREREGS + AVR32NUMFPREGS); i++) + (*reg_list)[i] = &avr32_ap7k_gdb_dummy_fp_reg; + #endif LOG_ERROR("%s: implement me", __func__); @@ -642,8 +610,7 @@ int avr32_ap7k_get_gdb_reg_list(struct target *target, struct reg **reg_list[], -struct target_type avr32_ap7k_target = -{ +struct target_type avr32_ap7k_target = { .name = "avr32_ap7k", .poll = avr32_ap7k_poll, @@ -664,10 +631,10 @@ struct target_type avr32_ap7k_target = .read_memory = avr32_ap7k_read_memory, .write_memory = avr32_ap7k_write_memory, .bulk_write_memory = avr32_ap7k_bulk_write_memory, - // .checksum_memory = avr32_ap7k_checksum_memory, - // .blank_check_memory = avr32_ap7k_blank_check_memory, + /* .checksum_memory = avr32_ap7k_checksum_memory, */ + /* .blank_check_memory = avr32_ap7k_blank_check_memory, */ - // .run_algorithm = avr32_ap7k_run_algorithm, + /* .run_algorithm = avr32_ap7k_run_algorithm, */ .add_breakpoint = avr32_ap7k_add_breakpoint, .remove_breakpoint = avr32_ap7k_remove_breakpoint, diff --git a/src/target/avr32_ap7k.h b/src/target/avr32_ap7k.h index d08254b..0b5b281 100644 --- a/src/target/avr32_ap7k.h +++ b/src/target/avr32_ap7k.h @@ -25,8 +25,7 @@ struct target; #define AP7k_COMMON_MAGIC 0x4150374b -struct avr32_ap7k_common -{ +struct avr32_ap7k_common { int common_magic; struct avr32_jtag jtag; struct reg_cache *core_cache; @@ -36,11 +35,10 @@ struct avr32_ap7k_common static inline struct avr32_ap7k_common * target_to_ap7k(struct target *target) { - return (struct avr32_ap7k_common*)target->arch_info; + return (struct avr32_ap7k_common *)target->arch_info; } -struct avr32_core_reg -{ +struct avr32_core_reg { uint32_t num; struct target *target; struct avr32_ap7k_common *avr32_common; diff --git a/src/target/avr32_jtag.c b/src/target/avr32_jtag.c index b6b5e37..c88f44e 100644 --- a/src/target/avr32_jtag.c +++ b/src/target/avr32_jtag.c @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -34,8 +35,7 @@ static int avr32_jtag_set_instr(struct avr32_jtag *jtag_info, int new_instr) if (tap == NULL) return ERROR_FAIL; - if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) - { + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) { do { struct scan_field field; uint8_t t[4]; @@ -47,8 +47,7 @@ static int avr32_jtag_set_instr(struct avr32_jtag *jtag_info, int new_instr) field.in_value = ret; jtag_add_ir_scan(tap, &field, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: setting address failed", __func__); return ERROR_FAIL; } @@ -59,7 +58,7 @@ static int avr32_jtag_set_instr(struct avr32_jtag *jtag_info, int new_instr) return ERROR_OK; } -int avr32_jtag_nexus_set_address(struct avr32_jtag *jtag_info, +int avr32_jtag_nexus_set_address(struct avr32_jtag *jtag_info, uint32_t addr, int mode) { struct scan_field fields[2]; @@ -85,19 +84,18 @@ int avr32_jtag_nexus_set_address(struct avr32_jtag *jtag_info, fields[1].out_value = addr_buf; jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: setting address failed", __func__); return ERROR_FAIL; } busy = buf_get_u32(busy_buf, 6, 1); - } while(busy); + } while (busy); return ERROR_OK; } -int avr32_jtag_nexus_read_data(struct avr32_jtag *jtag_info, +int avr32_jtag_nexus_read_data(struct avr32_jtag *jtag_info, uint32_t *pdata) { @@ -121,8 +119,7 @@ int avr32_jtag_nexus_read_data(struct avr32_jtag *jtag_info, jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: reading data failed", __func__); return ERROR_FAIL; } @@ -135,8 +132,7 @@ int avr32_jtag_nexus_read_data(struct avr32_jtag *jtag_info, return ERROR_OK; } - -int avr32_jtag_nexus_write_data(struct avr32_jtag *jtag_info, +int avr32_jtag_nexus_write_data(struct avr32_jtag *jtag_info, uint32_t data) { @@ -163,8 +159,7 @@ int avr32_jtag_nexus_write_data(struct avr32_jtag *jtag_info, jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: reading data failed", __func__); return ERROR_FAIL; } @@ -176,9 +171,6 @@ int avr32_jtag_nexus_write_data(struct avr32_jtag *jtag_info, return ERROR_OK; } - - - int avr32_jtag_nexus_read(struct avr32_jtag *jtag_info, uint32_t addr, uint32_t *value) { @@ -228,18 +220,17 @@ int avr32_jtag_mwa_set_address(struct avr32_jtag *jtag_info, int slave, fields[1].out_value = slave_buf; jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: setting address failed", __func__); return ERROR_FAIL; } busy = buf_get_u32(busy_buf, 1, 1); - } while(busy); + } while (busy); return ERROR_OK; } -int avr32_jtag_mwa_read_data(struct avr32_jtag *jtag_info, +int avr32_jtag_mwa_read_data(struct avr32_jtag *jtag_info, uint32_t *pdata) { @@ -263,8 +254,7 @@ int avr32_jtag_mwa_read_data(struct avr32_jtag *jtag_info, jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: reading data failed", __func__); return ERROR_FAIL; } @@ -277,7 +267,7 @@ int avr32_jtag_mwa_read_data(struct avr32_jtag *jtag_info, return ERROR_OK; } -int avr32_jtag_mwa_write_data(struct avr32_jtag *jtag_info, +int avr32_jtag_mwa_write_data(struct avr32_jtag *jtag_info, uint32_t data) { @@ -304,8 +294,7 @@ int avr32_jtag_mwa_write_data(struct avr32_jtag *jtag_info, jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE); - if (jtag_execute_queue() != ERROR_OK) - { + if (jtag_execute_queue() != ERROR_OK) { LOG_ERROR("%s: reading data failed", __func__); return ERROR_FAIL; } @@ -316,8 +305,6 @@ int avr32_jtag_mwa_write_data(struct avr32_jtag *jtag_info, return ERROR_OK; } - - int avr32_jtag_mwa_read(struct avr32_jtag *jtag_info, int slave, uint32_t addr, uint32_t *value) { diff --git a/src/target/avr32_jtag.h b/src/target/avr32_jtag.h index 00f8330..d04ddda 100644 --- a/src/target/avr32_jtag.h +++ b/src/target/avr32_jtag.h @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef AVR32_JTAG #define AVR32_JTAG @@ -81,8 +82,7 @@ #define MTSR(sysreg, reg) (0xe3b00002 | ((reg) << 16) | sysreg) #define MFSR(reg, sysreg) (0xe1b00002 | ((reg) << 16) | sysreg) -struct avr32_jtag -{ +struct avr32_jtag { struct jtag_tap *tap; uint32_t dpc; /* Debug PC value */ }; @@ -97,11 +97,9 @@ int avr32_jtag_mwa_read(struct avr32_jtag *jtag_info, int slave, int avr32_jtag_mwa_write(struct avr32_jtag *jtag_info, int slave, uint32_t addr, uint32_t value); - int avr32_ocd_setbits(struct avr32_jtag *jtag, int reg, uint32_t bits); int avr32_ocd_clearbits(struct avr32_jtag *jtag, int reg, uint32_t bits); int avr32_jtag_exec(struct avr32_jtag *jtag_info, uint32_t inst); #endif /* AVR32_JTAG */ - diff --git a/src/target/avr32_mem.c b/src/target/avr32_mem.c index 9c78c10..3275b6d 100644 --- a/src/target/avr32_mem.c +++ b/src/target/avr32_mem.c @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -25,14 +26,13 @@ #include "avr32_jtag.h" #include "avr32_mem.h" -int avr32_jtag_read_memory32(struct avr32_jtag *jtag_info, - uint32_t addr, int count, uint32_t *buffer) +int avr32_jtag_read_memory32(struct avr32_jtag *jtag_info, + uint32_t addr, int count, uint32_t *buffer) { int i, retval; uint32_t data; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, addr + i*4, &data); @@ -40,14 +40,14 @@ int avr32_jtag_read_memory32(struct avr32_jtag *jtag_info, return retval; /* XXX: Assume AVR32 is BE */ - buffer[i] = be_to_h_u32((uint8_t*)&data); + buffer[i] = be_to_h_u32((uint8_t *)&data); } return ERROR_OK; } -int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, - uint32_t addr, int count, uint16_t *buffer) +int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, + uint32_t addr, int count, uint16_t *buffer) { int i, retval; uint32_t data; @@ -55,8 +55,7 @@ int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, i = 0; /* any unaligned half-words? */ - if (addr & 3) - { + if (addr & 3) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, addr + i*2, &data); @@ -64,14 +63,13 @@ int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, return retval; /* XXX: Assume AVR32 is BE */ - data = be_to_h_u32((uint8_t*)&data); + data = be_to_h_u32((uint8_t *)&data); buffer[i] = (data >> 16) & 0xffff; i++; } /* read all complete words */ - for (; i < (count & ~1); i+=2) - { + for (; i < (count & ~1); i += 2) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, addr + i*2, &data); @@ -79,14 +77,13 @@ int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, return retval; /* XXX: Assume AVR32 is BE */ - data = be_to_h_u32((uint8_t*)&data); + data = be_to_h_u32((uint8_t *)&data); buffer[i] = data & 0xffff; buffer[i+1] = (data >> 16) & 0xffff; } /* last halfword */ - if (i < count) - { + if (i < count) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, addr + i*2, &data); @@ -94,73 +91,68 @@ int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, return retval; /* XXX: Assume AVR32 is BE */ - data = be_to_h_u32((uint8_t*)&data); + data = be_to_h_u32((uint8_t *)&data); buffer[i] = data & 0xffff; } return ERROR_OK; } -int avr32_jtag_read_memory8(struct avr32_jtag *jtag_info, - uint32_t addr, int count, uint8_t *buffer) +int avr32_jtag_read_memory8(struct avr32_jtag *jtag_info, + uint32_t addr, int count, uint8_t *buffer) { int i, j, retval; uint8_t data[4]; i = 0; /* Do we have non-aligned bytes? */ - if (addr & 3) - { + if (addr & 3) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, - addr + i, (uint32_t*)(void *)data); + addr + i, (uint32_t *)(void *)data); if (retval != ERROR_OK) return retval; - for (j = addr & 3; (j < 4) && (i < count); j++, i++) - buffer[i] = data[3-j]; + for (j = addr & 3; (j < 4) && (i < count); j++, i++) + buffer[i] = data[3-j]; } - /* read all complete words */ - for (; i < (count & ~3); i+=4) - { + for (; i < (count & ~3); i += 4) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, - addr + i, (uint32_t*)(void *)data); + addr + i, (uint32_t *)(void *)data); if (retval != ERROR_OK) return retval; for (j = 0; j < 4; j++) - buffer[i+j] = data[3-j]; + buffer[i+j] = data[3-j]; } /* remaining bytes */ - if (i < count) - { + if (i < count) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, - addr + i, (uint32_t*)(void *)data); + addr + i, (uint32_t *)(void *)data); if (retval != ERROR_OK) return retval; - for (j = 0; i + j < count; j++) - buffer[i+j] = data[3-j]; + for (j = 0; i + j < count; j++) + buffer[i+j] = data[3-j]; } return ERROR_OK; } -int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info, - uint32_t addr, int count, const uint32_t *buffer) +int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info, + uint32_t addr, int count, const uint32_t *buffer) { int i, retval; uint32_t data; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { /* XXX: Assume AVR32 is BE */ - h_u32_to_be((uint8_t*)&data, buffer[i]); + h_u32_to_be((uint8_t *)&data, buffer[i]); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr + i*4, data); @@ -172,8 +164,8 @@ int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info, return ERROR_OK; } -int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, - uint32_t addr, int count, const uint16_t *buffer) +int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, + uint32_t addr, int count, const uint16_t *buffer) { int i, retval; uint32_t data; @@ -185,7 +177,7 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, * Do we have any non-aligned half-words? */ if (addr & 3) { - /* + /* * mwa_read will read whole world, no nead to fiddle * with address. It will be truncated in set_addr */ @@ -195,9 +187,9 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, if (retval != ERROR_OK) return retval; - data = be_to_h_u32((uint8_t*)&data); + data = be_to_h_u32((uint8_t *)&data); data = (buffer[i] << 16) | (data & 0xffff); - h_u32_to_be((uint8_t*)&data_out, data); + h_u32_to_be((uint8_t *)&data_out, data); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr, data_out); @@ -208,13 +200,11 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, i++; } - /* write all complete words */ - for (; i < (count & ~1); i+=2) - { + for (; i < (count & ~1); i += 2) { /* XXX: Assume AVR32 is BE */ data = (buffer[i+1] << 16) | buffer[i]; - h_u32_to_be((uint8_t*)&data_out, data); + h_u32_to_be((uint8_t *)&data_out, data); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr + i*2, data_out); @@ -224,18 +214,17 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, } /* last halfword */ - if (i < count) - { + if (i < count) { retval = avr32_jtag_mwa_read(jtag_info, SLAVE_HSB_UNCACHED, addr + i*2, &data); if (retval != ERROR_OK) return retval; - data = be_to_h_u32((uint8_t*)&data); + data = be_to_h_u32((uint8_t *)&data); data &= ~0xffff; data |= buffer[i]; - h_u32_to_be((uint8_t*)&data_out, data); + h_u32_to_be((uint8_t *)&data_out, data); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr + i*2, data_out); @@ -247,8 +236,8 @@ int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, return ERROR_OK; } -int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, - uint32_t addr, int count, const uint8_t *buffer) +int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, + uint32_t addr, int count, const uint8_t *buffer) { int i, j, retval; uint32_t data; @@ -260,7 +249,7 @@ int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, * Do we have any non-aligned bytes? */ if (addr & 3) { - /* + /* * mwa_read will read whole world, no nead to fiddle * with address. It will be truncated in set_addr */ @@ -270,14 +259,13 @@ int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, if (retval != ERROR_OK) return retval; - data = be_to_h_u32((uint8_t*)&data); - for (j = addr & 3; (j < 4) && (i < count); j++, i++) - { + data = be_to_h_u32((uint8_t *)&data); + for (j = addr & 3; (j < 4) && (i < count); j++, i++) { data &= ~(0xff << j*8); data |= (buffer[i] << j*8); } - h_u32_to_be((uint8_t*)&data_out, data); + h_u32_to_be((uint8_t *)&data_out, data); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr, data_out); @@ -287,14 +275,13 @@ int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, /* write all complete words */ - for (; i < (count & ~3); i+=4) - { + for (; i < (count & ~3); i += 4) { data = 0; for (j = 0; j < 4; j++) data |= (buffer[j+i] << j*8); - h_u32_to_be((uint8_t*)&data_out, data); + h_u32_to_be((uint8_t *)&data_out, data); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr + i, data_out); @@ -313,14 +300,13 @@ int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, if (retval != ERROR_OK) return retval; - data = be_to_h_u32((uint8_t*)&data); - for (j = 0; i < count; j++, i++) - { + data = be_to_h_u32((uint8_t *)&data); + for (j = 0; i < count; j++, i++) { data &= ~(0xff << j*8); data |= (buffer[j+i] << j*8); } - h_u32_to_be((uint8_t*)&data_out, data); + h_u32_to_be((uint8_t *)&data_out, data); retval = avr32_jtag_mwa_write(jtag_info, SLAVE_HSB_UNCACHED, addr+i, data_out); diff --git a/src/target/avr32_mem.h b/src/target/avr32_mem.h index 58d51bb..a85137e 100644 --- a/src/target/avr32_mem.h +++ b/src/target/avr32_mem.h @@ -16,22 +16,22 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef AVR32_MEM #define AVR32_MEM -int avr32_jtag_read_memory32(struct avr32_jtag *jtag_info, +int avr32_jtag_read_memory32(struct avr32_jtag *jtag_info, uint32_t addr, int count, uint32_t *buffer); -int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, +int avr32_jtag_read_memory16(struct avr32_jtag *jtag_info, uint32_t addr, int count, uint16_t *buffer); -int avr32_jtag_read_memory8(struct avr32_jtag *jtag_info, +int avr32_jtag_read_memory8(struct avr32_jtag *jtag_info, uint32_t addr, int count, uint8_t *buffer); -int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info, +int avr32_jtag_write_memory32(struct avr32_jtag *jtag_info, uint32_t addr, int count, const uint32_t *buffer); -int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, +int avr32_jtag_write_memory16(struct avr32_jtag *jtag_info, uint32_t addr, int count, const uint16_t *buffer); -int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, +int avr32_jtag_write_memory8(struct avr32_jtag *jtag_info, uint32_t addr, int count, const uint8_t *buffer); #endif /* AVR32_MEM */ - diff --git a/src/target/avr32_regs.c b/src/target/avr32_regs.c index e3761ad..c9581d7 100644 --- a/src/target/avr32_regs.c +++ b/src/target/avr32_regs.c @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -25,7 +26,7 @@ #include "avr32_jtag.h" #include "avr32_regs.h" -static int avr32_jtag_read_reg(struct avr32_jtag *jtag_info, int reg, +static int avr32_jtag_read_reg(struct avr32_jtag *jtag_info, int reg, uint32_t *val) { int retval; @@ -36,27 +37,27 @@ static int avr32_jtag_read_reg(struct avr32_jtag *jtag_info, int reg, return retval; do { - retval = avr32_jtag_nexus_read(jtag_info, + retval = avr32_jtag_nexus_read(jtag_info, AVR32_OCDREG_DCSR, &dcsr); if (retval != ERROR_OK) return retval; } while (!(dcsr & OCDREG_DCSR_CPUD)); - retval = avr32_jtag_nexus_read(jtag_info, + retval = avr32_jtag_nexus_read(jtag_info, AVR32_OCDREG_DCCPU, val); return retval; } -static int avr32_jtag_write_reg(struct avr32_jtag *jtag_info, int reg, +static int avr32_jtag_write_reg(struct avr32_jtag *jtag_info, int reg, uint32_t val) { int retval; uint32_t dcsr; /* Restore Status reg */ - retval = avr32_jtag_nexus_write(jtag_info, + retval = avr32_jtag_nexus_write(jtag_info, AVR32_OCDREG_DCEMU, val); if (retval != ERROR_OK) return retval; @@ -65,7 +66,7 @@ static int avr32_jtag_write_reg(struct avr32_jtag *jtag_info, int reg, if (retval != ERROR_OK) return retval; do { - retval = avr32_jtag_nexus_read(jtag_info, + retval = avr32_jtag_nexus_read(jtag_info, AVR32_OCDREG_DCSR, &dcsr); } while (!(dcsr & OCDREG_DCSR_EMUD) && (retval == ERROR_OK)); @@ -79,7 +80,7 @@ int avr32_jtag_read_regs(struct avr32_jtag *jtag_info, uint32_t *regs) int i, retval; /* read core registers */ - for (i = 0; i < AVR32NUMCOREREGS - 1; i++) + for (i = 0; i < AVR32NUMCOREREGS - 1; i++) avr32_jtag_read_reg(jtag_info, i, regs + i); /* read status register */ @@ -108,7 +109,7 @@ int avr32_jtag_write_regs(struct avr32_jtag *jtag_info, uint32_t *regs) /* * And now the rest of registers */ - for (i = 0; i < AVR32NUMCOREREGS - 1; i++) + for (i = 0; i < AVR32NUMCOREREGS - 1; i++) avr32_jtag_write_reg(jtag_info, i, regs[i]); return ERROR_OK; diff --git a/src/target/avr32_regs.h b/src/target/avr32_regs.h index 01ea3ed..0c59673 100644 --- a/src/target/avr32_regs.h +++ b/src/target/avr32_regs.h @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef AVR32_REGS #define AVR32_REGS @@ -43,4 +44,3 @@ int avr32_jtag_read_regs(struct avr32_jtag *jtag_info, uint32_t *regs); int avr32_jtag_write_regs(struct avr32_jtag *jtag_info, uint32_t *regs); #endif /* AVR32_REGS */ - diff --git a/src/target/avrt.c b/src/target/avrt.c index 1ddf24d..3f4f8d7 100644 --- a/src/target/avrt.c +++ b/src/target/avrt.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -25,7 +26,6 @@ #include "target.h" #include "target_type.h" - #define AVR_JTAG_INS_LEN 4 /* forward declarations */ @@ -35,8 +35,10 @@ static int avr_init_target(struct command_context *cmd_ctx, struct target *targe static int avr_arch_state(struct target *target); static int avr_poll(struct target *target); static int avr_halt(struct target *target); -static int avr_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -static int avr_step(struct target *target, int current, uint32_t address, int handle_breakpoints); +static int avr_resume(struct target *target, int current, uint32_t address, + int handle_breakpoints, int debug_execution); +static int avr_step(struct target *target, int current, uint32_t address, + int handle_breakpoints); static int avr_assert_reset(struct target *target); static int avr_deassert_reset(struct target *target); @@ -48,8 +50,7 @@ static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, i static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti); static int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *ir_in, uint32_t ir_out, int dr_len, int rti); -struct target_type avr_target = -{ +struct target_type avr_target = { .name = "avr", .poll = avr_poll, @@ -96,43 +97,41 @@ static int avr_target_create(struct target *target, Jim_Interp *interp) static int avr_init_target(struct command_context *cmd_ctx, struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int avr_arch_state(struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int avr_poll(struct target *target) { if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) - { target->state = TARGET_HALTED; - } - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int avr_halt(struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int avr_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int avr_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } @@ -140,7 +139,7 @@ static int avr_assert_reset(struct target *target) { target->state = TARGET_RESET; - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } @@ -148,13 +147,13 @@ static int avr_deassert_reset(struct target *target) { target->state = TARGET_RUNNING; - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int avr_soft_reset_halt(struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } @@ -173,13 +172,11 @@ int avr_jtag_sendinstr(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out) static int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_len, int rti) { - if (NULL == tap) - { + if (NULL == tap) { LOG_ERROR("invalid tap"); return ERROR_FAIL; } - if (ir_len != tap->ir_length) - { + if (ir_len != tap->ir_length) { LOG_ERROR("invalid ir_len"); return ERROR_FAIL; } @@ -194,8 +191,7 @@ static int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_len, int rti) { - if (NULL == tap) - { + if (NULL == tap) { LOG_ERROR("invalid tap"); return ERROR_FAIL; } @@ -210,8 +206,7 @@ static int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, uint8_t ir_out, int ir_len, int rti) { - if (ir_len > 8) - { + if (ir_len > 8) { LOG_ERROR("ir_len overflow, maxium is 8"); return ERROR_FAIL; } @@ -224,13 +219,12 @@ static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in, static int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *dr_in, uint32_t dr_out, int dr_len, int rti) { - if (dr_len > 32) - { + if (dr_len > 32) { LOG_ERROR("dr_len overflow, maxium is 32"); return ERROR_FAIL; } - mcu_write_dr(tap, (uint8_t*)dr_in, (uint8_t*)&dr_out, dr_len, rti); + mcu_write_dr(tap, (uint8_t *)dr_in, (uint8_t *)&dr_out, dr_len, rti); return ERROR_OK; } diff --git a/src/target/avrt.h b/src/target/avrt.h index 221f924..076fddb 100644 --- a/src/target/avrt.h +++ b/src/target/avrt.h @@ -17,18 +17,17 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef AVRT_H #define AVRT_H #include <jtag/jtag.h> -struct mcu_jtag -{ +struct mcu_jtag { struct jtag_tap *tap; }; -struct avr_common -{ +struct avr_common { struct mcu_jtag jtag_info; }; diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c index c0905ed..3b516d0 100644 --- a/src/target/breakpoints.c +++ b/src/target/breakpoints.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -28,24 +29,24 @@ #include <helper/log.h> #include "breakpoints.h" - -static char *breakpoint_type_strings[] = -{ +static char *breakpoint_type_strings[] = { "hardware", "software" }; -static char *watchpoint_rw_strings[] = -{ +static char *watchpoint_rw_strings[] = { "read", "write", "access" }; -// monotonic counter/id-number for breakpoints and watch points +/* monotonic counter/id-number for breakpoints and watch points */ static int bpwp_unique_id; -int breakpoint_add_internal(struct target *target, uint32_t address, uint32_t length, enum breakpoint_type type) +int breakpoint_add_internal(struct target *target, + uint32_t address, + uint32_t length, + enum breakpoint_type type) { struct breakpoint *breakpoint = target->breakpoints; struct breakpoint **breakpoint_p = &target->breakpoints; @@ -54,8 +55,7 @@ int breakpoint_add_internal(struct target *target, uint32_t address, uint32_t le int n; n = 0; - while (breakpoint) - { + while (breakpoint) { n++; if (breakpoint->address == address) { /* FIXME don't assume "same address" means "same @@ -63,7 +63,7 @@ int breakpoint_add_internal(struct target *target, uint32_t address, uint32_t le * succeeding. */ LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)", - address, breakpoint->unique_id); + address, breakpoint->unique_id); return ERROR_OK; } breakpoint_p = &breakpoint->next; @@ -82,33 +82,36 @@ int breakpoint_add_internal(struct target *target, uint32_t address, uint32_t le retval = target_add_breakpoint(target, *breakpoint_p); switch (retval) { - case ERROR_OK: - break; - case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: - reason = "resource not available"; - goto fail; - case ERROR_TARGET_NOT_HALTED: - reason = "target running"; - goto fail; - default: - reason = "unknown reason"; + case ERROR_OK: + break; + case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: + reason = "resource not available"; + goto fail; + case ERROR_TARGET_NOT_HALTED: + reason = "target running"; + goto fail; + default: + reason = "unknown reason"; fail: - LOG_ERROR("can't add breakpoint: %s", reason); - free((*breakpoint_p)->orig_instr); - free(*breakpoint_p); - *breakpoint_p = NULL; - return retval; + LOG_ERROR("can't add breakpoint: %s", reason); + free((*breakpoint_p)->orig_instr); + free(*breakpoint_p); + *breakpoint_p = NULL; + return retval; } LOG_DEBUG("added %s breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", - breakpoint_type_strings[(*breakpoint_p)->type], - (*breakpoint_p)->address, (*breakpoint_p)->length, - (*breakpoint_p)->unique_id); + breakpoint_type_strings[(*breakpoint_p)->type], + (*breakpoint_p)->address, (*breakpoint_p)->length, + (*breakpoint_p)->unique_id); return ERROR_OK; } -int context_breakpoint_add_internal(struct target *target, uint32_t asid, uint32_t length, enum breakpoint_type type) +int context_breakpoint_add_internal(struct target *target, + uint32_t asid, + uint32_t length, + enum breakpoint_type type) { struct breakpoint *breakpoint = target->breakpoints; struct breakpoint **breakpoint_p = &target->breakpoints; @@ -116,17 +119,15 @@ int context_breakpoint_add_internal(struct target *target, uint32_t asid, uint32 int n; n = 0; - while (breakpoint) - { + while (breakpoint) { n++; - if (breakpoint->asid == asid) - { + if (breakpoint->asid == asid) { /* FIXME don't assume "same address" means "same * breakpoint" ... check all the parameters before * succeeding. */ LOG_DEBUG("Duplicate Breakpoint asid: 0x%08" PRIx32 " (BP %d)", - asid, breakpoint->unique_id); + asid, breakpoint->unique_id); return -1; } breakpoint_p = &breakpoint->next; @@ -143,8 +144,7 @@ int context_breakpoint_add_internal(struct target *target, uint32_t asid, uint32 (*breakpoint_p)->next = NULL; (*breakpoint_p)->unique_id = bpwp_unique_id++; retval = target_add_context_breakpoint(target, *breakpoint_p); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("could not add breakpoint"); free((*breakpoint_p)->orig_instr); free(*breakpoint_p); @@ -153,22 +153,25 @@ int context_breakpoint_add_internal(struct target *target, uint32_t asid, uint32 } LOG_DEBUG("added %s Context breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", - breakpoint_type_strings[(*breakpoint_p)->type], - (*breakpoint_p)->asid, (*breakpoint_p)->length, - (*breakpoint_p)->unique_id); + breakpoint_type_strings[(*breakpoint_p)->type], + (*breakpoint_p)->asid, (*breakpoint_p)->length, + (*breakpoint_p)->unique_id); return ERROR_OK; } -int hybrid_breakpoint_add_internal(struct target *target, uint32_t address, uint32_t asid, uint32_t length, enum breakpoint_type type) +int hybrid_breakpoint_add_internal(struct target *target, + uint32_t address, + uint32_t asid, + uint32_t length, + enum breakpoint_type type) { struct breakpoint *breakpoint = target->breakpoints; struct breakpoint **breakpoint_p = &target->breakpoints; int retval; int n; n = 0; - while (breakpoint) - { + while (breakpoint) { n++; if ((breakpoint->asid == asid) && (breakpoint->address == address)) { /* FIXME don't assume "same address" means "same @@ -176,13 +179,11 @@ int hybrid_breakpoint_add_internal(struct target *target, uint32_t address, uint * succeeding. */ LOG_DEBUG("Duplicate Hybrid Breakpoint asid: 0x%08" PRIx32 " (BP %d)", - asid, breakpoint->unique_id); + asid, breakpoint->unique_id); return -1; - } - else if ((breakpoint->address == address) && (breakpoint->asid == 0)) - { + } else if ((breakpoint->address == address) && (breakpoint->asid == 0)) { LOG_DEBUG("Duplicate Breakpoint IVA: 0x%08" PRIx32 " (BP %d)", - address, breakpoint->unique_id); + address, breakpoint->unique_id); return -1; } @@ -201,92 +202,89 @@ int hybrid_breakpoint_add_internal(struct target *target, uint32_t address, uint retval = target_add_hybrid_breakpoint(target, *breakpoint_p); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("could not add breakpoint"); free((*breakpoint_p)->orig_instr); free(*breakpoint_p); *breakpoint_p = NULL; return retval; } - LOG_DEBUG("added %s Hybrid breakpoint at address 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", - breakpoint_type_strings[(*breakpoint_p)->type], - (*breakpoint_p)->address, (*breakpoint_p)->length, - (*breakpoint_p)->unique_id); + LOG_DEBUG( + "added %s Hybrid breakpoint at address 0x%8.8" PRIx32 " of length 0x%8.8x, (BPID: %d)", + breakpoint_type_strings[(*breakpoint_p)->type], + (*breakpoint_p)->address, + (*breakpoint_p)->length, + (*breakpoint_p)->unique_id); return ERROR_OK; } - - -int breakpoint_add(struct target *target, uint32_t address, uint32_t length, enum breakpoint_type type) +int breakpoint_add(struct target *target, + uint32_t address, + uint32_t length, + enum breakpoint_type type) { - int retval = ERROR_OK; - if (target->smp) - { + if (target->smp) { struct target_list *head; struct target *curr; head = target->head; if (type == BKPT_SOFT) - return(breakpoint_add_internal(head->target, address,length, type)); + return breakpoint_add_internal(head->target, address, length, type); - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - retval = breakpoint_add_internal(curr, address,length, type); - if (retval != ERROR_OK) return retval; + retval = breakpoint_add_internal(curr, address, length, type); + if (retval != ERROR_OK) + return retval; head = head->next; } return retval; - } - else - return(breakpoint_add_internal(target, address, length, type)); - + } else + return breakpoint_add_internal(target, address, length, type); } -int context_breakpoint_add(struct target *target, uint32_t asid, uint32_t length, enum breakpoint_type type) +int context_breakpoint_add(struct target *target, + uint32_t asid, + uint32_t length, + enum breakpoint_type type) { - int retval = ERROR_OK; - if (target->smp) - { + if (target->smp) { struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - retval = context_breakpoint_add_internal(curr, asid,length, type); - if (retval != ERROR_OK) return retval; + retval = context_breakpoint_add_internal(curr, asid, length, type); + if (retval != ERROR_OK) + return retval; head = head->next; } return retval; - } - else - return(context_breakpoint_add_internal(target, asid, length, type)); - + } else + return context_breakpoint_add_internal(target, asid, length, type); } -int hybrid_breakpoint_add(struct target *target, uint32_t address, uint32_t asid, uint32_t length, enum breakpoint_type type) +int hybrid_breakpoint_add(struct target *target, + uint32_t address, + uint32_t asid, + uint32_t length, + enum breakpoint_type type) { - int retval = ERROR_OK; - if (target->smp) - { + if (target->smp) { struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; retval = hybrid_breakpoint_add_internal(curr, address, asid, length, type); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; head = head->next; } return retval; - } - else - return(hybrid_breakpoint_add_internal(target, address, asid, length, type)); - + } else + return hybrid_breakpoint_add_internal(target, address, asid, length, type); } /* free up a breakpoint */ @@ -296,8 +294,7 @@ static void breakpoint_free(struct target *target, struct breakpoint *breakpoint struct breakpoint **breakpoint_p = &target->breakpoints; int retval; - while (breakpoint) - { + while (breakpoint) { if (breakpoint == breakpoint_to_remove) break; breakpoint_p = &breakpoint->next; @@ -319,8 +316,7 @@ int breakpoint_remove_internal(struct target *target, uint32_t address) { struct breakpoint *breakpoint = target->breakpoints; - while (breakpoint) - { + while (breakpoint) { if ((breakpoint->address == address) && (breakpoint->asid == 0)) break; else if ((breakpoint->address == 0) && (breakpoint->asid == address)) @@ -330,13 +326,10 @@ int breakpoint_remove_internal(struct target *target, uint32_t address) breakpoint = breakpoint->next; } - if (breakpoint) - { + if (breakpoint) { breakpoint_free(target, breakpoint); return 1; - } - else - { + } else { if (!target->smp) LOG_ERROR("no breakpoint at address 0x%8.8" PRIx32 " found", address); return 0; @@ -345,60 +338,50 @@ int breakpoint_remove_internal(struct target *target, uint32_t address) void breakpoint_remove(struct target *target, uint32_t address) { int found = 0; - if (target->smp) - { + if (target->smp) { struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; found += breakpoint_remove_internal(curr, address); head = head->next; } if (found == 0) LOG_ERROR("no breakpoint at address 0x%8.8" PRIx32 " found", address); - } - else breakpoint_remove_internal(target, address); + } else + breakpoint_remove_internal(target, address); } void breakpoint_clear_target_internal(struct target *target) { - struct breakpoint *breakpoint; - LOG_DEBUG("Delete all breakpoints for target: %s", - target_name(target)); - while ((breakpoint = target->breakpoints) != NULL) - { - breakpoint_free(target, breakpoint); - } + target_name(target)); + while (target->breakpoints != NULL) + breakpoint_free(target, target->breakpoints); } void breakpoint_clear_target(struct target *target) { - if (target->smp) - { + if (target->smp) { struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; breakpoint_clear_target_internal(curr); head = head->next; } - } - else breakpoint_clear_target_internal(target); + } else + breakpoint_clear_target_internal(target); } - -struct breakpoint* breakpoint_find(struct target *target, uint32_t address) +struct breakpoint *breakpoint_find(struct target *target, uint32_t address) { struct breakpoint *breakpoint = target->breakpoints; - while (breakpoint) - { + while (breakpoint) { if (breakpoint->address == address) return breakpoint; breakpoint = breakpoint->next; @@ -408,23 +391,22 @@ struct breakpoint* breakpoint_find(struct target *target, uint32_t address) } int watchpoint_add(struct target *target, uint32_t address, uint32_t length, - enum watchpoint_rw rw, uint32_t value, uint32_t mask) + enum watchpoint_rw rw, uint32_t value, uint32_t mask) { struct watchpoint *watchpoint = target->watchpoints; struct watchpoint **watchpoint_p = &target->watchpoints; int retval; char *reason; - while (watchpoint) - { + while (watchpoint) { if (watchpoint->address == address) { if (watchpoint->length != length - || watchpoint->value != value - || watchpoint->mask != mask - || watchpoint->rw != rw) { + || watchpoint->value != value + || watchpoint->mask != mask + || watchpoint->rw != rw) { LOG_ERROR("address 0x%8.8" PRIx32 - "already has watchpoint %d", - address, watchpoint->unique_id); + "already has watchpoint %d", + address, watchpoint->unique_id); return ERROR_FAIL; } @@ -445,31 +427,31 @@ int watchpoint_add(struct target *target, uint32_t address, uint32_t length, retval = target_add_watchpoint(target, *watchpoint_p); switch (retval) { - case ERROR_OK: - break; - case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: - reason = "resource not available"; - goto bye; - case ERROR_TARGET_NOT_HALTED: - reason = "target running"; - goto bye; - default: - reason = "unrecognized error"; + case ERROR_OK: + break; + case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: + reason = "resource not available"; + goto bye; + case ERROR_TARGET_NOT_HALTED: + reason = "target running"; + goto bye; + default: + reason = "unrecognized error"; bye: - LOG_ERROR("can't add %s watchpoint at 0x%8.8" PRIx32 ", %s", + LOG_ERROR("can't add %s watchpoint at 0x%8.8" PRIx32 ", %s", watchpoint_rw_strings[(*watchpoint_p)->rw], address, reason); - free (*watchpoint_p); - *watchpoint_p = NULL; - return retval; + free(*watchpoint_p); + *watchpoint_p = NULL; + return retval; } LOG_DEBUG("added %s watchpoint at 0x%8.8" PRIx32 - " of length 0x%8.8" PRIx32 " (WPID: %d)", - watchpoint_rw_strings[(*watchpoint_p)->rw], - (*watchpoint_p)->address, - (*watchpoint_p)->length, - (*watchpoint_p)->unique_id); + " of length 0x%8.8" PRIx32 " (WPID: %d)", + watchpoint_rw_strings[(*watchpoint_p)->rw], + (*watchpoint_p)->address, + (*watchpoint_p)->length, + (*watchpoint_p)->unique_id); return ERROR_OK; } @@ -480,8 +462,7 @@ static void watchpoint_free(struct target *target, struct watchpoint *watchpoint struct watchpoint **watchpoint_p = &target->watchpoints; int retval; - while (watchpoint) - { + while (watchpoint) { if (watchpoint == watchpoint_to_remove) break; watchpoint_p = &watchpoint->next; @@ -500,31 +481,22 @@ void watchpoint_remove(struct target *target, uint32_t address) { struct watchpoint *watchpoint = target->watchpoints; - while (watchpoint) - { + while (watchpoint) { if (watchpoint->address == address) break; watchpoint = watchpoint->next; } if (watchpoint) - { watchpoint_free(target, watchpoint); - } else - { LOG_ERROR("no watchpoint at address 0x%8.8" PRIx32 " found", address); - } } void watchpoint_clear_target(struct target *target) { - struct watchpoint *watchpoint; - LOG_DEBUG("Delete all watchpoints for target: %s", - target_name(target)); - while ((watchpoint = target->watchpoints) != NULL) - { - watchpoint_free(target, watchpoint); - } + target_name(target)); + while (target->watchpoints != NULL) + watchpoint_free(target, target->watchpoints); } diff --git a/src/target/breakpoints.h b/src/target/breakpoints.h index 912117f..8b1631a 100644 --- a/src/target/breakpoints.h +++ b/src/target/breakpoints.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef BREAKPOINTS_H #define BREAKPOINTS_H @@ -24,19 +25,16 @@ struct target; -enum breakpoint_type -{ +enum breakpoint_type { BKPT_HARD, BKPT_SOFT, }; -enum watchpoint_rw -{ +enum watchpoint_rw { WPT_READ = 0, WPT_WRITE = 1, WPT_ACCESS = 2 }; -struct breakpoint -{ +struct breakpoint { uint32_t address; uint32_t asid; int length; @@ -45,11 +43,10 @@ struct breakpoint uint8_t *orig_instr; struct breakpoint *next; uint32_t unique_id; - int linked_BRP; + int linked_BRP; }; -struct watchpoint -{ +struct watchpoint { uint32_t address; uint32_t length; uint32_t mask; @@ -69,7 +66,7 @@ int hybrid_breakpoint_add(struct target *target, uint32_t address, uint32_t asid, uint32_t length, enum breakpoint_type type); void breakpoint_remove(struct target *target, uint32_t address); -struct breakpoint* breakpoint_find(struct target *target, uint32_t address); +struct breakpoint *breakpoint_find(struct target *target, uint32_t address); void watchpoint_clear_target(struct target *target); int watchpoint_add(struct target *target, diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 862fd55..e1c4c9c 100755 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -36,6 +36,7 @@ * Cortex-A9(tm) TRM, ARM DDI 0407F * * * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -52,20 +53,20 @@ static int cortex_a8_poll(struct target *target); static int cortex_a8_debug_entry(struct target *target); static int cortex_a8_restore_context(struct target *target, bool bpwp); static int cortex_a8_set_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode); + struct breakpoint *breakpoint, uint8_t matchmode); static int cortex_a8_set_context_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode); + struct breakpoint *breakpoint, uint8_t matchmode); static int cortex_a8_set_hybrid_breakpoint(struct target *target, - struct breakpoint *breakpoint); + struct breakpoint *breakpoint); static int cortex_a8_unset_breakpoint(struct target *target, - struct breakpoint *breakpoint); + struct breakpoint *breakpoint); static int cortex_a8_dap_read_coreregister_u32(struct target *target, - uint32_t *value, int regnum); + uint32_t *value, int regnum); static int cortex_a8_dap_write_coreregister_u32(struct target *target, - uint32_t value, int regnum); + uint32_t value, int regnum); static int cortex_a8_mmu(struct target *target, int *enabled); static int cortex_a8_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys); + uint32_t virt, uint32_t *phys); /* * FIXME do topology discovery using the ROM; don't @@ -77,19 +78,18 @@ static int cortex_a8_virt2phys(struct target *target, #define swjdp_debugap 1 /* restore cp15_control_reg at resume */ -static int cortex_a8_restore_cp15_control_reg(struct target* target) +static int cortex_a8_restore_cp15_control_reg(struct target *target) { int retval = ERROR_OK; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - struct armv7a_common *armv7a = target_to_armv7a(target); + struct armv7a_common *armv7a = target_to_armv7a(target); - if (cortex_a8->cp15_control_reg !=cortex_a8->cp15_control_reg_curr) - { + if (cortex_a8->cp15_control_reg != cortex_a8->cp15_control_reg_curr) { cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; - //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); + /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); */ retval = armv7a->arm.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg); } return retval; @@ -103,20 +103,20 @@ static int cortex_a8_check_address(struct target *target, uint32_t address) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); uint32_t os_border = armv7a->armv7a_mmu.os_border; if ((address < os_border) && - (armv7a->arm.core_mode == ARM_MODE_SVC)) { - LOG_ERROR("%x access in userspace and target in supervisor",address); + (armv7a->arm.core_mode == ARM_MODE_SVC)) { + LOG_ERROR("%x access in userspace and target in supervisor", address); return ERROR_FAIL; } if ((address >= os_border) && - (cortex_a8->curr_mode != ARM_MODE_SVC)) { + (cortex_a8->curr_mode != ARM_MODE_SVC)) { dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); cortex_a8->curr_mode = ARM_MODE_SVC; LOG_INFO("%x access in kernel space and target not in supervisor", - address); + address); return ERROR_OK; } if ((address < os_border) && - (cortex_a8->curr_mode == ARM_MODE_SVC)) { + (cortex_a8->curr_mode == ARM_MODE_SVC)) { dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); cortex_a8->curr_mode = ARM_MODE_ANY; } @@ -130,39 +130,32 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); int retval = ERROR_OK; - if (enable) - { + if (enable) { /* if mmu enabled at target stop and mmu not enable */ - if (!(cortex_a8->cp15_control_reg & 0x1U)) - { + if (!(cortex_a8->cp15_control_reg & 0x1U)) { LOG_ERROR("trying to enable mmu on target stopped with mmu disable"); return ERROR_FAIL; } - if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) - { + if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr |= 0x1U; retval = armv7a->arm.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); } - } - else - { - if (cortex_a8->cp15_control_reg_curr & 0x4U) - { - /* data cache is active */ + } else { + if (cortex_a8->cp15_control_reg_curr & 0x4U) { + /* data cache is active */ cortex_a8->cp15_control_reg_curr &= ~0x4U; /* flush data cache armv7 function to be called */ if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache) - armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target); + armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache(target); } - if ( (cortex_a8->cp15_control_reg_curr & 0x1U)) - { + if ((cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr &= ~0x1U; retval = armv7a->arm.mcr(target, 15, - 0, 0, /* op1, op2 */ - 1, 0, /* CRn, CRm */ + 0, 0, /* op1, op2 */ + 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); } } @@ -181,26 +174,24 @@ static int cortex_a8_init_debug_access(struct target *target) LOG_DEBUG(" "); - /* Unlocking the debug registers for modification */ - /* The debugport might be uninitialised so try twice */ + /* Unlocking the debug registers for modification + * The debugport might be uninitialised so try twice */ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { /* try again */ retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55); if (retval == ERROR_OK) - { - LOG_USER("Locking debug access failed on first, but succeeded on second try."); - } + LOG_USER( + "Locking debug access failed on first, but succeeded on second try."); } if (retval != ERROR_OK) return retval; /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_PRSR, &dummy); + armv7a->debug_base + CPUDBG_PRSR, &dummy); if (retval != ERROR_OK) return retval; @@ -218,7 +209,7 @@ static int cortex_a8_init_debug_access(struct target *target) * happen to know that no instruction is pending. */ static int cortex_a8_exec_opcode(struct target *target, - uint32_t opcode, uint32_t *dscr_p) + uint32_t opcode, uint32_t *dscr_p) { uint32_t dscr; int retval; @@ -231,44 +222,37 @@ static int cortex_a8_exec_opcode(struct target *target, /* Wait for InstrCompl bit to be set */ long long then = timeval_ms(); - while ((dscr & DSCR_INSTR_COMP) == 0) - { + while ((dscr & DSCR_INSTR_COMP) == 0) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); return retval; } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } } retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_ITR, opcode); + armv7a->debug_base + CPUDBG_ITR, opcode); if (retval != ERROR_OK) return retval; then = timeval_ms(); - do - { + do { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register"); return retval; } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } - } - while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ + } while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ if (dscr_p) *dscr_p = dscr; @@ -281,7 +265,7 @@ Read core register with very few exec_opcode, fast but needs work_area. This can cause problems with MMU active. **************************************************************************/ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address, - uint32_t * regfile) + uint32_t *regfile) { int retval = ERROR_OK; struct armv7a_common *armv7a = target_to_armv7a(target); @@ -304,7 +288,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre } static int cortex_a8_dap_read_coreregister_u32(struct target *target, - uint32_t *value, int regnum) + uint32_t *value, int regnum) { int retval = ERROR_OK; uint8_t reg = regnum&0xFF; @@ -315,17 +299,14 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, if (reg > 17) return retval; - if (reg < 15) - { + if (reg < 15) { /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0), &dscr); if (retval != ERROR_OK) return retval; - } - else if (reg == 15) - { + } else if (reg == 15) { /* "MOV r0, r15"; then move r0 to DCCTX */ retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr); if (retval != ERROR_OK) @@ -335,9 +316,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, &dscr); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* "MRS r0, CPSR" or "MRS r0, SPSR" * then move r0 to DCCTX */ @@ -353,14 +332,12 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, /* Wait for DTRRXfull then read DTRRTX */ long long then = timeval_ms(); - while ((dscr & DSCR_DTR_TX_FULL) == 0) - { + while ((dscr & DSCR_DTR_TX_FULL) == 0) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode"); return ERROR_FAIL; } @@ -374,7 +351,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, } static int cortex_a8_dap_write_coreregister_u32(struct target *target, - uint32_t value, int regnum) + uint32_t value, int regnum) { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; @@ -386,11 +363,10 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, /* Check that DCCRX is not full */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; - if (dscr & DSCR_DTR_RX_FULL) - { + if (dscr & DSCR_DTR_RX_FULL) { LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), @@ -409,17 +385,14 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, if (retval != ERROR_OK) return retval; - if (Rd < 15) - { + if (Rd < 15) { /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), &dscr); - + if (retval != ERROR_OK) return retval; - } - else if (Rd == 15) - { + } else if (Rd == 15) { /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "mov r15, r0" */ @@ -430,9 +403,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr); if (retval != ERROR_OK) return retval; - } - else - { + } else { /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) */ @@ -446,8 +417,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, return retval; /* "Prefetch flush" after modifying execution status in CPSR */ - if (Rd == 16) - { + if (Rd == 16) { retval = cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4), &dscr); @@ -460,7 +430,9 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, } /* Write to memory mapped registers directly with no cache or mmu handling */ -static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value) +static int cortex_a8_dap_write_memap_register_u32(struct target *target, + uint32_t address, + uint32_t value) { int retval; struct armv7a_common *armv7a = target_to_armv7a(target); @@ -491,11 +463,11 @@ static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap, - swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); + swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, - uint32_t *dscr_p) + uint32_t *dscr_p) { struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr = DSCR_INSTR_COMP; @@ -512,8 +484,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, &dscr); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for read dcc"); return ERROR_FAIL; } @@ -523,7 +494,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, a8->armv7a_common.debug_base + CPUDBG_DTRTX, data); if (retval != ERROR_OK) return retval; - //LOG_DEBUG("read DCC 0x%08" PRIx32, *data); + /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */ if (dscr_p) *dscr_p = dscr; @@ -540,8 +511,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) /* set up invariant: INSTR_COMP is set after ever DPM operation */ long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, a8->armv7a_common.debug_base + CPUDBG_DSCR, &dscr); @@ -549,8 +519,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) return retval; if ((dscr & DSCR_INSTR_COMP) != 0) break; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for dpm prepare"); return ERROR_FAIL; } @@ -578,7 +547,7 @@ static int cortex_a8_dpm_finish(struct arm_dpm *dpm) } static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; @@ -595,7 +564,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, } static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t data) + uint32_t opcode, uint32_t data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t dscr = DSCR_INSTR_COMP; @@ -634,7 +603,7 @@ static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm) } static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); int retval; @@ -653,7 +622,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, - uint32_t opcode, uint32_t *data) + uint32_t opcode, uint32_t *data) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t dscr = DSCR_INSTR_COMP; @@ -679,7 +648,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, } static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, - uint32_t addr, uint32_t control) + uint32_t addr, uint32_t control) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); uint32_t vr = a8->armv7a_common.debug_base; @@ -687,23 +656,23 @@ static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t, int retval; switch (index_t) { - case 0 ... 15: /* breakpoints */ - vr += CPUDBG_BVR_BASE; - cr += CPUDBG_BCR_BASE; - break; - case 16 ... 31: /* watchpoints */ - vr += CPUDBG_WVR_BASE; - cr += CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: /* breakpoints */ + vr += CPUDBG_BVR_BASE; + cr += CPUDBG_BCR_BASE; + break; + case 16 ... 31: /* watchpoints */ + vr += CPUDBG_WVR_BASE; + cr += CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } vr += 4 * index_t; cr += 4 * index_t; LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x", - (unsigned) vr, (unsigned) cr); + (unsigned) vr, (unsigned) cr); retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target, vr, addr); @@ -720,15 +689,15 @@ static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t) uint32_t cr; switch (index_t) { - case 0 ... 15: - cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; - break; - case 16 ... 31: - cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE; + break; + case 16 ... 31: + cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } cr += 4 * index_t; @@ -767,20 +736,17 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) } static struct target *get_cortex_a8(struct target *target, int32_t coreid) { -struct target_list *head; -struct target *curr; + struct target_list *head; + struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED)) - { - return curr; - } + return curr; head = head->next; } - return target; + return target; } static int cortex_a8_halt(struct target *target); @@ -790,13 +756,10 @@ static int cortex_a8_halt_smp(struct target *target) struct target_list *head; struct target *curr; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - if ((curr != target) && (curr->state!= TARGET_HALTED)) - { + if ((curr != target) && (curr->state != TARGET_HALTED)) retval += cortex_a8_halt(curr); - } head = head->next; } return retval; @@ -805,8 +768,7 @@ static int cortex_a8_halt_smp(struct target *target) static int update_halt_gdb(struct target *target) { int retval = 0; - if (target->gdb_service->core[0]==-1) - { + if (target->gdb_service->core[0] == -1) { target->gdb_service->target = target; target->gdb_service->core[0] = target->coreid; retval += cortex_a8_halt_smp(target); @@ -826,75 +788,61 @@ static int cortex_a8_poll(struct target *target) struct armv7a_common *armv7a = &cortex_a8->armv7a_common; struct adiv5_dap *swjdp = armv7a->arm.dap; enum target_state prev_target_state = target->state; - // toggle to another core is done by gdb as follow - // maint packet J core_id - // continue - // the next polling trigger an halt event sent to gdb + /* toggle to another core is done by gdb as follow */ + /* maint packet J core_id */ + /* continue */ + /* the next polling trigger an halt event sent to gdb */ if ((target->state == TARGET_HALTED) && (target->smp) && - (target->gdb_service) && - (target->gdb_service->target==NULL) ) - { + (target->gdb_service) && + (target->gdb_service->target == NULL)) { target->gdb_service->target = get_cortex_a8(target, target->gdb_service->core[1]); - target_call_event_callbacks(target, - TARGET_EVENT_HALTED); + target_call_event_callbacks(target, TARGET_EVENT_HALTED); return retval; } retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) - { return retval; - } cortex_a8->cpudbg_dscr = dscr; - if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) - { - if (prev_target_state != TARGET_HALTED) - { + if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) { + if (prev_target_state != TARGET_HALTED) { /* We have a halting debug event */ LOG_DEBUG("Target halted"); target->state = TARGET_HALTED; if ((prev_target_state == TARGET_RUNNING) - || (prev_target_state == TARGET_RESET)) - { + || (prev_target_state == TARGET_RESET)) { retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; - if (target->smp) - { + if (target->smp) { retval = update_halt_gdb(target); if (retval != ERROR_OK) return retval; } target_call_event_callbacks(target, - TARGET_EVENT_HALTED); + TARGET_EVENT_HALTED); } - if (prev_target_state == TARGET_DEBUG_RUNNING) - { + if (prev_target_state == TARGET_DEBUG_RUNNING) { LOG_DEBUG(" "); retval = cortex_a8_debug_entry(target); if (retval != ERROR_OK) return retval; - if (target->smp) - { + if (target->smp) { retval = update_halt_gdb(target); if (retval != ERROR_OK) return retval; } target_call_event_callbacks(target, - TARGET_EVENT_DEBUG_HALTED); + TARGET_EVENT_DEBUG_HALTED); } } - } - else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED) - { + } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED) target->state = TARGET_RUNNING; - } - else - { + else { LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr); target->state = TARGET_UNKNOWN; } @@ -922,28 +870,24 @@ static int cortex_a8_halt(struct target *target) * enter halting debug mode */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); + armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE); if (retval != ERROR_OK) return retval; long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; if ((dscr & DSCR_CORE_HALTED) != 0) - { break; - } - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for halt"); return ERROR_FAIL; } @@ -955,7 +899,7 @@ static int cortex_a8_halt(struct target *target) } static int cortex_a8_internal_restore(struct target *target, int current, - uint32_t *address, int handle_breakpoints, int debug_execution) + uint32_t *address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *arm = &armv7a->arm; @@ -966,8 +910,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, target_free_all_working_areas(target); #if 0 - if (debug_execution) - { + if (debug_execution) { /* Disable interrupts */ /* We disable interrupts in the PRIMASK register instead of * masking with C_MASKINTS, @@ -980,7 +923,8 @@ static int cortex_a8_internal_restore(struct target *target, int current, /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, + 32) | (1 << 24)); armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } @@ -996,29 +940,28 @@ static int cortex_a8_internal_restore(struct target *target, int current, /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - switch (arm->core_state) - { - case ARM_STATE_ARM: - resume_pc &= 0xFFFFFFFC; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - resume_pc |= 0x1; - break; - case ARM_STATE_JAZELLE: - LOG_ERROR("How do I resume into Jazelle state??"); - return ERROR_FAIL; + switch (arm->core_state) { + case ARM_STATE_ARM: + resume_pc &= 0xFFFFFFFC; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + resume_pc |= 0x1; + break; + case ARM_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); buf_set_u32(arm->pc->value, 0, 32, resume_pc); arm->pc->dirty = 1; arm->pc->valid = 1; /* restore dpm_mode at system halt */ - dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); - /* called it now before restoring context because it uses cpu + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + /* called it now before restoring context because it uses cpu * register r0 for restoring cp15 control register */ retval = cortex_a8_restore_cp15_control_reg(target); if (retval != ERROR_OK) @@ -1026,7 +969,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, retval = cortex_a8_restore_context(target, handle_breakpoints); if (retval != ERROR_OK) return retval; - target->debug_reason = DBG_REASON_NOTHALTED; + target->debug_reason = DBG_REASON_NOTHALTED; target->state = TARGET_RUNNING; /* registers are now invalid */ @@ -1034,11 +977,10 @@ static int cortex_a8_internal_restore(struct target *target, int current, #if 0 /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); @@ -1057,9 +999,9 @@ static int cortex_a8_internal_restart(struct target *target) struct adiv5_dap *swjdp = arm->dap; int retval; uint32_t dscr; -/* - * Restart core and wait for it to be started. Clear ITRen and sticky - * exception flags: see ARMv7 ARM, C5.9. + /* + * * Restart core and wait for it to be started. Clear ITRen and sticky + * * exception flags: see ARMv7 ARM, C5.9. * * REVISIT: for single stepping, we probably want to * disable IRQs by default, with optional override... @@ -1074,7 +1016,7 @@ static int cortex_a8_internal_restart(struct target *target) LOG_ERROR("DSCR InstrCompl must be set before leaving debug!"); retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); + armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN); if (retval != ERROR_OK) return retval; @@ -1085,16 +1027,14 @@ static int cortex_a8_internal_restart(struct target *target) return retval; long long then = timeval_ms(); - for (;;) - { + for (;; ) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; if ((dscr & DSCR_CORE_RESTARTED) != 0) break; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("Timeout waiting for resume"); return ERROR_FAIL; } @@ -1109,22 +1049,20 @@ static int cortex_a8_internal_restart(struct target *target) return ERROR_OK; } -static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints) +static int cortex_a8_restore_smp(struct target *target, int handle_breakpoints) { int retval = 0; struct target_list *head; struct target *curr; - uint32_t address; + uint32_t address; head = target->head; - while(head != (struct target_list*)NULL) - { + while (head != (struct target_list *)NULL) { curr = head->target; - if ((curr != target) && (curr->state != TARGET_RUNNING)) - { - /* resume current address , not in step mode */ - retval += cortex_a8_internal_restore(curr, 1, &address, - handle_breakpoints, 0); - retval += cortex_a8_internal_restart(curr); + if ((curr != target) && (curr->state != TARGET_RUNNING)) { + /* resume current address , not in step mode */ + retval += cortex_a8_internal_restore(curr, 1, &address, + handle_breakpoints, 0); + retval += cortex_a8_internal_restart(curr); } head = head->next; @@ -1133,12 +1071,11 @@ static int cortex_a8_restore_smp(struct target *target,int handle_breakpoints) } static int cortex_a8_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) + uint32_t address, int handle_breakpoints, int debug_execution) { int retval = 0; - /* dummy resume for smp toggle in order to reduce gdb impact */ - if ((target->smp) && (target->gdb_service->core[1]!=-1)) - { + /* dummy resume for smp toggle in order to reduce gdb impact */ + if ((target->smp) && (target->gdb_service->core[1] != -1)) { /* simulate a start and halt of target */ target->gdb_service->target = NULL; target->gdb_service->core[0] = target->gdb_service->core[1]; @@ -1147,22 +1084,19 @@ static int cortex_a8_resume(struct target *target, int current, return 0; } cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution); - if (target->smp) - { target->gdb_service->core[0] = -1; + if (target->smp) { + target->gdb_service->core[0] = -1; retval = cortex_a8_restore_smp(target, handle_breakpoints); if (retval != ERROR_OK) return retval; } cortex_a8_internal_restart(target); - if (!debug_execution) - { + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); LOG_DEBUG("target resumed at 0x%" PRIx32, address); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%" PRIx32, address); @@ -1187,7 +1121,7 @@ static int cortex_a8_debug_entry(struct target *target) /* REVISIT surely we should not re-read DSCR !! */ retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) return retval; @@ -1226,19 +1160,14 @@ static int cortex_a8_debug_entry(struct target *target) /* First load register acessible through core debug port*/ if (!regfile_working_area) - { retval = arm_dpm_read_current_registers(&armv7a->dpm); - } - else - { + else { retval = cortex_a8_read_regs_through_mem(target, regfile_working_area->address, regfile); target_free_working_area(target, regfile_working_area); if (retval != ERROR_OK) - { return retval; - } /* read Current PSR */ retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16); @@ -1251,8 +1180,7 @@ static int cortex_a8_debug_entry(struct target *target) arm_set_cpsr(arm, cpsr); /* update cache */ - for (i = 0; i <= ARM_PC; i++) - { + for (i = 0; i <= ARM_PC; i++) { reg = arm_reg_current(arm, i); buf_set_u32(reg->value, 0, 32, regfile[i]); @@ -1261,14 +1189,11 @@ static int cortex_a8_debug_entry(struct target *target) } /* Fixup PC Resume Address */ - if (cpsr & (1 << 5)) - { - // T bit set for Thumb or ThumbEE state + if (cpsr & (1 << 5)) { + /* T bit set for Thumb or ThumbEE state */ regfile[ARM_PC] -= 4; - } - else - { - // ARM state + } else { + /* ARM state */ regfile[ARM_PC] -= 8; } @@ -1291,9 +1216,8 @@ static int cortex_a8_debug_entry(struct target *target) #endif /* Are we in an exception handler */ -// armv4_5->exception_number = 0; - if (armv7a->post_debug_entry) - { +/* armv4_5->exception_number = 0; */ + if (armv7a->post_debug_entry) { retval = armv7a->post_debug_entry(target); if (retval != ERROR_OK) return retval; @@ -1316,26 +1240,24 @@ static int cortex_a8_post_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); - cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; + cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) - { armv7a_identify_cache(target); - } armv7a->armv7a_mmu.mmu_enabled = - (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; + (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0; armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled = - (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; + (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = - (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; + (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; cortex_a8->curr_mode = armv7a->arm.core_mode; return ERROR_OK; } static int cortex_a8_step(struct target *target, int current, uint32_t address, - int handle_breakpoints) + int handle_breakpoints) { struct armv7a_common *armv7a = target_to_armv7a(target); struct arm *arm = &armv7a->arm; @@ -1344,8 +1266,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, struct reg *r; int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1353,13 +1274,9 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* current = 1: continue on current pc, otherwise continue at <address> */ r = arm->pc; if (!current) - { buf_set_u32(r->value, 0, 32, address); - } else - { address = buf_get_u32(r->value, 0, 32); - } /* The front-end may request us not to handle breakpoints. * But since Cortex-A8 uses breakpoint for single step, @@ -1375,7 +1292,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* Setup single step breakpoint */ stepbreakpoint.address = address; stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB) - ? 2 : 4; + ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -1389,13 +1306,11 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, return retval; long long then = timeval_ms(); - while (target->state != TARGET_HALTED) - { + while (target->state != TARGET_HALTED) { retval = cortex_a8_poll(target); if (retval != ERROR_OK) return retval; - if (timeval_ms() > then + 1000) - { + if (timeval_ms() > then + 1000) { LOG_ERROR("timeout waiting for target halt"); return ERROR_FAIL; } @@ -1426,46 +1341,40 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp) return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp); } - /* * Cortex-A8 Breakpoint and watchpoint functions */ /* Setup hardware Breakpoint Register Pair */ static int cortex_a8_set_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode) + struct breakpoint *breakpoint, uint8_t matchmode) { int retval; - int brp_i=0; + int brp_i = 0; uint32_t control; uint8_t byte_addr_select = 0x0F; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num)) - brp_i++ ; - if (brp_i >= cortex_a8->brp_num) - { + brp_i++; + if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } breakpoint->set = brp_i + 1; if (breakpoint->length == 2) - { byte_addr_select = (3 << (breakpoint->address & 0x02)); - } control = ((matchmode & 0x7) << 20) - | (byte_addr_select << 5) - | (3 << 1) | 1; + | (byte_addr_select << 5) + | (3 << 1) | 1; brp_list[brp_i].used = 1; brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC); brp_list[brp_i].control = control; @@ -1480,20 +1389,14 @@ static int cortex_a8_set_breakpoint(struct target *target, if (retval != ERROR_OK) return retval; LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, - brp_list[brp_i].value); - } - else if (breakpoint->type == BKPT_SOFT) - { + brp_list[brp_i].control, + brp_list[brp_i].value); + } else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; if (breakpoint->length == 2) - { buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11)); - } else - { buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11)); - } retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, @@ -1505,67 +1408,66 @@ static int cortex_a8_set_breakpoint(struct target *target, breakpoint->length, 1, code); if (retval != ERROR_OK) return retval; - breakpoint->set = 0x11; /* Any nice value but 0 */ + breakpoint->set = 0x11; /* Any nice value but 0 */ } return ERROR_OK; } static int cortex_a8_set_context_breakpoint(struct target *target, - struct breakpoint *breakpoint, uint8_t matchmode) + struct breakpoint *breakpoint, uint8_t matchmode) { int retval = ERROR_FAIL; - int brp_i=0; + int brp_i = 0; uint32_t control; uint8_t byte_addr_select = 0x0F; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; - - if (breakpoint->set) - { + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; + + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); - return retval ; + return retval; } /*check available context BRPs*/ - while ((brp_list[brp_i].used || (brp_list[brp_i].type!=BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num)) - brp_i++ ; - - if (brp_i >= cortex_a8->brp_num) - { + while ((brp_list[brp_i].used || + (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < cortex_a8->brp_num)) + brp_i++; + + if (brp_i >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; } breakpoint->set = brp_i + 1; control = ((matchmode & 0x7) << 20) - | (byte_addr_select << 5) - | (3 << 1) | 1; + | (byte_addr_select << 5) + | (3 << 1) | 1; brp_list[brp_i].used = 1; brp_list[brp_i].value = (breakpoint->asid); brp_list[brp_i].control = control; retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, + + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].value); - if(retval != ERROR_OK) + if (retval != ERROR_OK) return retval; retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].control); - if(retval != ERROR_OK) + if (retval != ERROR_OK) return retval; LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, - brp_list[brp_i].value); + brp_list[brp_i].control, + brp_list[brp_i].value); return ERROR_OK; - + } static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_FAIL; - int brp_1=0; //holds the contextID pair - int brp_2=0; // holds the IVA pair + int brp_1 = 0; /* holds the contextID pair */ + int brp_2 = 0; /* holds the IVA pair */ uint32_t control_CTX, control_IVA; uint8_t CTX_byte_addr_select = 0x0F; uint8_t IVA_byte_addr_select = 0x0F; @@ -1573,105 +1475,97 @@ static int cortex_a8_set_hybrid_breakpoint(struct target *target, struct breakpo uint8_t IVA_machmode = 0x01; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; - - - - if (breakpoint->set) - { + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; + + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); - return retval ; + return retval; } /*check available context BRPs*/ - while ((brp_list[brp_1].used || (brp_list[brp_1].type!=BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num)) - brp_1++ ; - - printf("brp(CTX) found num: %d \n",brp_1); - if (brp_1 >= cortex_a8->brp_num) - { + while ((brp_list[brp_1].used || + (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < cortex_a8->brp_num)) + brp_1++; + + printf("brp(CTX) found num: %d\n", brp_1); + if (brp_1 >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; } - while ((brp_list[brp_2].used || (brp_list[brp_2].type!=BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num)) - brp_2++ ; - - printf("brp(IVA) found num: %d \n",brp_2); - if (brp_2 >= cortex_a8->brp_num) - { + while ((brp_list[brp_2].used || + (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < cortex_a8->brp_num)) + brp_2++; + + printf("brp(IVA) found num: %d\n", brp_2); + if (brp_2 >= cortex_a8->brp_num) { LOG_ERROR("ERROR Can not find free Breakpoint Register Pair"); return ERROR_FAIL; } breakpoint->set = brp_1 + 1; - breakpoint->linked_BRP= brp_2; + breakpoint->linked_BRP = brp_2; control_CTX = ((CTX_machmode & 0x7) << 20) - | (brp_2 << 16) - | (0 << 14) - | (CTX_byte_addr_select << 5) - | (3 << 1) | 1; - brp_list[brp_1].used = 1; - brp_list[brp_1].value = (breakpoint->asid); - brp_list[brp_1].control = control_CTX; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn, - brp_list[brp_1].value); - if (retval != ERROR_OK) - return retval; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn, - brp_list[brp_1].control); - if( retval != ERROR_OK ) - return retval; + | (brp_2 << 16) + | (0 << 14) + | (CTX_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_1].used = 1; + brp_list[brp_1].value = (breakpoint->asid); + brp_list[brp_1].control = control_CTX; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn, + brp_list[brp_1].control); + if (retval != ERROR_OK) + return retval; - control_IVA = ((IVA_machmode & 0x7) << 20) - | (brp_1 << 16) - | (IVA_byte_addr_select << 5) - | (3 << 1) | 1; - brp_list[brp_2].used = 1; - brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); - brp_list[brp_2].control = control_IVA; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn, - brp_list[brp_2].value); - if (retval != ERROR_OK) - return retval; - retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base - + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn, - brp_list[brp_2].control); - if (retval != ERROR_OK ) - return retval; + control_IVA = ((IVA_machmode & 0x7) << 20) + | (brp_1 << 16) + | (IVA_byte_addr_select << 5) + | (3 << 1) | 1; + brp_list[brp_2].used = 1; + brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC); + brp_list[brp_2].control = control_IVA; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].value); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base + + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn, + brp_list[brp_2].control); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } - static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct cortex_a8_brp * brp_list = cortex_a8->brp_list; + struct cortex_a8_brp *brp_list = cortex_a8->brp_list; - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { - if ((breakpoint->address != 0) && (breakpoint->asid != 0)) - { + if (breakpoint->type == BKPT_HARD) { + if ((breakpoint->address != 0) && (breakpoint->asid != 0)) { int brp_i = breakpoint->set - 1; int brp_j = breakpoint->linked_BRP; - if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) - { + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) { LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].control, brp_list[brp_i].value); brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; @@ -1684,14 +1578,13 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn, brp_list[brp_i].value); if (retval != ERROR_OK) - return retval; - if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) - { + return retval; + if ((brp_j < 0) || (brp_j >= cortex_a8->brp_num)) { LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_j, - brp_list[brp_j].control, brp_list[brp_j].value); + brp_list[brp_j].control, brp_list[brp_j].value); brp_list[brp_j].used = 0; brp_list[brp_j].value = 0; brp_list[brp_j].control = 0; @@ -1708,18 +1601,15 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * breakpoint->linked_BRP = 0; breakpoint->set = 0; return ERROR_OK; - - } - else - { + + } else { int brp_i = breakpoint->set - 1; - if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) - { + if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num)) { LOG_DEBUG("Invalid BRP number in breakpoint"); return ERROR_OK; } LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i, - brp_list[brp_i].control, brp_list[brp_i].value); + brp_list[brp_i].control, brp_list[brp_i].value); brp_list[brp_i].used = 0; brp_list[brp_i].value = 0; brp_list[brp_i].control = 0; @@ -1735,21 +1625,16 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * return retval; breakpoint->set = 0; return ERROR_OK; - } - } - else - { + } + } else { /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) - { + if (breakpoint->length == 4) { retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; - } - else - { + } else { retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr); @@ -1763,12 +1648,11 @@ static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint * } static int cortex_a8_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1776,16 +1660,15 @@ static int cortex_a8_add_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) cortex_a8->brp_num_available--; - return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ + return cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */ } static int cortex_a8_add_context_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1793,16 +1676,15 @@ static int cortex_a8_add_context_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) cortex_a8->brp_num_available--; - return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */ + return cortex_a8_set_context_breakpoint(target, breakpoint, 0x02); /* asid match */ } static int cortex_a8_add_hybrid_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); - if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1)) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1810,7 +1692,7 @@ static int cortex_a8_add_hybrid_breakpoint(struct target *target, if (breakpoint->type == BKPT_HARD) cortex_a8->brp_num_available--; - return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */ + return cortex_a8_set_hybrid_breakpoint(target, breakpoint); /* ??? */ } @@ -1820,26 +1702,22 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint #if 0 /* It is perfectly possible to remove breakpoints while the target is running */ - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } #endif - if (breakpoint->set) - { + if (breakpoint->set) { cortex_a8_unset_breakpoint(target, breakpoint); if (breakpoint->type == BKPT_HARD) - cortex_a8->brp_num_available++ ; + cortex_a8->brp_num_available++; } return ERROR_OK; } - - /* * Cortex-A8 Reset functions */ @@ -1853,9 +1731,9 @@ static int cortex_a8_assert_reset(struct target *target) /* FIXME when halt is requested, make it work somehow... */ /* Issue some kind of warm reset. */ - if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) target_handle_event(target, TARGET_EVENT_RESET_ASSERT); - } else if (jtag_get_reset_config() & RESET_HAS_SRST) { + else if (jtag_get_reset_config() & RESET_HAS_SRST) { /* REVISIT handle "pulls" cases, if there's * hardware that needs them to work. */ @@ -1889,8 +1767,9 @@ static int cortex_a8_deassert_reset(struct target *target) if (target->reset_halt) { if (target->state != TARGET_HALTED) { LOG_WARNING("%s: ran after reset and before halt ...", - target_name(target)); - if ((retval = target_halt(target)) != ERROR_OK) + target_name(target)); + retval = target_halt(target); + if (retval != ERROR_OK) return retval; } } @@ -1898,12 +1777,10 @@ static int cortex_a8_deassert_reset(struct target *target) return ERROR_OK; } - static int cortex_a8_write_apb_ab_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { - /* write memory through APB-AP */ int retval = ERROR_COMMAND_SYNTAX_ERROR; @@ -1917,8 +1794,7 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, uint32_t ui; } data; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1938,10 +1814,10 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, nbytes_to_write = 4 - start_byte; if (total_bytes < nbytes_to_write) - nbytes_to_write = total_bytes; - - if ( nbytes_to_write != 4 ) { - + nbytes_to_write = total_bytes; + + if (nbytes_to_write != 4) { + /* execute instruction LDR r1, [r0] */ retval = cortex_a8_exec_opcode(target, ARMV4_5_LDR(1, 0), NULL); if (retval != ERROR_OK) @@ -1951,7 +1827,7 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, if (retval != ERROR_OK) return retval; } - + for (i = 0; i < nbytes_to_write; ++i) data.uc_a[i + start_byte] = *buffer++; @@ -1960,9 +1836,9 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, return retval; /* execute instruction STRW r1, [r0], 1 (0xe4801004) */ - retval = cortex_a8_exec_opcode(target, ARMV4_5_STRW_IP(1, 0) , NULL); + retval = cortex_a8_exec_opcode(target, ARMV4_5_STRW_IP(1, 0), NULL); if (retval != ERROR_OK) - return retval; + return retval; total_bytes -= nbytes_to_write; start_byte = 0; @@ -1973,8 +1849,8 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, static int cortex_a8_read_apb_ab_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { /* read memory through APB-AP */ @@ -1990,8 +1866,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, uint32_t ui; } data; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2020,11 +1895,11 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, nbytes_to_read = 4 - start_byte; if (total_bytes < nbytes_to_read) - nbytes_to_read = total_bytes; - + nbytes_to_read = total_bytes; + for (i = 0; i < nbytes_to_read; ++i) *buffer++ = data.uc_a[i + start_byte]; - + total_bytes -= nbytes_to_read; start_byte = 0; } @@ -2042,50 +1917,51 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, */ static int cortex_a8_read_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", - address, size, count); + address, size, count); if (count && buffer) { - if ( apsel == swjdp_memoryap ) { + if (apsel == swjdp_memoryap) { /* read memory through AHB-AP */ switch (size) { - case 4: - retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, + case 4: + retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap, buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, + break; + case 2: + retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap, buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, + break; + case 1: + retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap, buffer, count, address); - break; + break; } } else { - /* read memory through APB-AP */ - /* disable mmu */ + /* read memory through APB-AP + * disable mmu */ retval = cortex_a8_mmu_modify(target, 0); - if (retval != ERROR_OK) return retval; - retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) + return retval; + retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } } return retval; } static int cortex_a8_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { int enabled = 0; uint32_t virt, phys; @@ -2096,39 +1972,40 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, /* cortex_a8 handles unaligned memory access */ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, - size, count); + size, count); if (apsel == swjdp_memoryap) { retval = cortex_a8_mmu(target, &enabled); if (retval != ERROR_OK) return retval; - if(enabled) - { + if (enabled) { virt = address; retval = cortex_a8_virt2phys(target, virt, &phys); if (retval != ERROR_OK) return retval; LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", - virt, phys); + virt, phys); address = phys; } retval = cortex_a8_read_phys_memory(target, address, size, count, buffer); } else { retval = cortex_a8_check_address(target, address); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; /* enable mmu */ retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; retval = cortex_a8_read_apb_ab_memory(target, address, size, count, buffer); } return retval; } static int cortex_a8_write_phys_memory(struct target *target, - uint32_t address, uint32_t size, - uint32_t count, const uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; @@ -2136,26 +2013,26 @@ static int cortex_a8_write_phys_memory(struct target *target, uint8_t apsel = swjdp->apsel; LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, - size, count); + size, count); if (count && buffer) { - if ( apsel == swjdp_memoryap ) { + if (apsel == swjdp_memoryap) { /* write memory through AHB-AP */ switch (size) { case 4: retval = mem_ap_sel_write_buf_u32(swjdp, swjdp_memoryap, - buffer, 4 * count, address); + buffer, 4 * count, address); break; case 2: retval = mem_ap_sel_write_buf_u16(swjdp, swjdp_memoryap, - buffer, 2 * count, address); + buffer, 2 * count, address); break; case 1: retval = mem_ap_sel_write_buf_u8(swjdp, swjdp_memoryap, - buffer, count, address); + buffer, count, address); break; } @@ -2165,14 +2042,13 @@ static int cortex_a8_write_phys_memory(struct target *target, retval = cortex_a8_mmu_modify(target, 0); if (retval != ERROR_OK) return retval; - return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); + return cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } } /* REVISIT this op is generic ARMv7-A/R stuff */ - if (retval == ERROR_OK && target->state == TARGET_HALTED) - { + if (retval == ERROR_OK && target->state == TARGET_HALTED) { struct arm_dpm *dpm = armv7a->arm.dpm; retval = dpm->prepare(dpm); @@ -2189,15 +2065,14 @@ static int cortex_a8_write_phys_memory(struct target *target, */ /* invalidate I-Cache */ - if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) - { + if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) { /* ICIMVAU - Invalidate Cache single entry * with MVA to PoU * MCR p15, 0, r0, c7, c5, 1 */ for (uint32_t cacheline = address; - cacheline < address + size * count; - cacheline += 64) { + cacheline < address + size * count; + cacheline += 64) { retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 5, 1), cacheline); @@ -2207,15 +2082,14 @@ static int cortex_a8_write_phys_memory(struct target *target, } /* invalidate D-Cache */ - if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) - { + if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) { /* DCIMVAC - Invalidate data Cache line * with MVA to PoC * MCR p15, 0, r0, c7, c6, 1 */ for (uint32_t cacheline = address; - cacheline < address + size * count; - cacheline += 64) { + cacheline < address + size * count; + cacheline += 64) { retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MCR(15, 0, 0, 7, 6, 1), cacheline); @@ -2231,7 +2105,7 @@ static int cortex_a8_write_phys_memory(struct target *target, } static int cortex_a8_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { int enabled = 0; uint32_t virt, phys; @@ -2241,45 +2115,47 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, - size, count); + size, count); if (apsel == swjdp_memoryap) { - LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count); + LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, + count); retval = cortex_a8_mmu(target, &enabled); if (retval != ERROR_OK) return retval; - if(enabled) - { + if (enabled) { virt = address; retval = cortex_a8_virt2phys(target, virt, &phys); if (retval != ERROR_OK) return retval; - LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys); + LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", + virt, + phys); address = phys; } - retval = cortex_a8_write_phys_memory(target, address, size, + retval = cortex_a8_write_phys_memory(target, address, size, count, buffer); - } - else { + } else { retval = cortex_a8_check_address(target, address); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; /* enable mmu */ retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) return retval; + if (retval != ERROR_OK) + return retval; retval = cortex_a8_write_apb_ab_memory(target, address, size, count, buffer); } - return retval; + return retval; } static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { return cortex_a8_write_memory(target, address, 4, count, buffer); } - static int cortex_a8_handle_target_request(void *priv) { struct target *target = priv; @@ -2292,23 +2168,20 @@ static int cortex_a8_handle_target_request(void *priv) if (!target->dbg_msg_enabled) return ERROR_OK; - if (target->state == TARGET_RUNNING) - { + if (target->state == TARGET_RUNNING) { uint32_t request; uint32_t dscr; retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); /* check if we have data */ - while ((dscr & DSCR_DTR_TX_FULL) && (retval==ERROR_OK)) - { + while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) { retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base+ CPUDBG_DTRTX, &request); - if (retval == ERROR_OK) - { + armv7a->debug_base + CPUDBG_DTRTX, &request); + if (retval == ERROR_OK) { target_request(target, request); retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base+ CPUDBG_DSCR, &dscr); + armv7a->debug_base + CPUDBG_DSCR, &dscr); } } } @@ -2336,8 +2209,7 @@ static int cortex_a8_examine_first(struct target *target) if (retval != ERROR_OK) return retval; - if (!target->dbgbase_set) - { + if (!target->dbgbase_set) { uint32_t dbgbase; /* Get ROM Table base */ uint32_t apid; @@ -2349,41 +2221,38 @@ static int cortex_a8_examine_first(struct target *target) &armv7a->debug_base); if (retval != ERROR_OK) return retval; - } - else - { + } else armv7a->debug_base = target->dbgbase; - } retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, armv7a->debug_base + CPUDBG_CPUID, &cpuid); if (retval != ERROR_OK) return retval; - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_CPUID, &cpuid); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CPUID"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_CTYPR, &ctypr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "CTYPR"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_TTYPR, &ttypr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "TTYPR"); return retval; } - if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, - armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK) - { + retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap, + armv7a->debug_base + CPUDBG_DIDR, &didr); + if (retval != ERROR_OK) { LOG_DEBUG("Examine %s failed", "DIDR"); return retval; } @@ -2403,9 +2272,8 @@ static int cortex_a8_examine_first(struct target *target) cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1; cortex_a8->brp_num_available = cortex_a8->brp_num; cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp)); -// cortex_a8->brb_enabled = ????; - for (i = 0; i < cortex_a8->brp_num; i++) - { +/* cortex_a8->brb_enabled = ????; */ + for (i = 0; i < cortex_a8->brp_num; i++) { cortex_a8->brp_list[i].used = 0; if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context)) cortex_a8->brp_list[i].type = BRP_NORMAL; @@ -2442,14 +2310,14 @@ static int cortex_a8_examine(struct target *target) */ static int cortex_a8_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { /* examine_first() does a bunch of this */ return ERROR_OK; } static int cortex_a8_init_arch_info(struct target *target, - struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) + struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { struct armv7a_common *armv7a = &cortex_a8->armv7a_common; struct adiv5_dap *dap = &armv7a->dap; @@ -2459,25 +2327,23 @@ static int cortex_a8_init_arch_info(struct target *target, /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; /* tap has no dap initialized */ - if (!tap->dap) - { - armv7a->arm.dap = dap; - /* Setup struct cortex_a8_common */ + if (!tap->dap) { + armv7a->arm.dap = dap; + /* Setup struct cortex_a8_common */ - /* prepare JTAG information for the new target */ - cortex_a8->jtag_info.tap = tap; - cortex_a8->jtag_info.scann_size = 4; + /* prepare JTAG information for the new target */ + cortex_a8->jtag_info.tap = tap; + cortex_a8->jtag_info.scann_size = 4; - /* Leave (only) generic DAP stuff for debugport_init() */ - dap->jtag_info = &cortex_a8->jtag_info; + /* Leave (only) generic DAP stuff for debugport_init() */ + dap->jtag_info = &cortex_a8->jtag_info; - /* Number of bits for tar autoincrement, impl. dep. at least 10 */ - dap->tar_autoincr_block = (1 << 10); - dap->memaccess_tck = 80; - tap->dap = dap; - } - else - armv7a->arm.dap = tap->dap; + /* Number of bits for tar autoincrement, impl. dep. at least 10 */ + dap->tar_autoincr_block = (1 << 10); + dap->memaccess_tck = 80; + tap->dap = dap; + } else + armv7a->arm.dap = tap->dap; cortex_a8->fast_reg_read = 0; @@ -2490,8 +2356,8 @@ static int cortex_a8_init_arch_info(struct target *target, armv7a->armv7a_mmu.read_physical_memory = cortex_a8_read_phys_memory; - -// arm7_9->handle_target_request = cortex_a8_handle_target_request; + +/* arm7_9->handle_target_request = cortex_a8_handle_target_request; */ /* REVISIT v7a setup should be in a v7a-specific routine */ armv7a_init_arch_info(target, armv7a); @@ -2521,26 +2387,24 @@ static int cortex_a8_mmu(struct target *target, int *enabled) } static int cortex_a8_virt2phys(struct target *target, - uint32_t virt, uint32_t *phys) + uint32_t virt, uint32_t *phys) { int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; - if (apsel == swjdp_memoryap) - { + if (apsel == swjdp_memoryap) { uint32_t ret; retval = armv7a_mmu_translate_va(target, - virt, &ret); + virt, &ret); if (retval != ERROR_OK) goto done; *phys = ret; - } - else - { /* use this method if swjdp_memoryap not selected */ - /* mmu must be enable in order to get a correct translation */ + } else {/* use this method if swjdp_memoryap not selected + * mmu must be enable in order to get a correct translation */ retval = cortex_a8_mmu_modify(target, 1); - if (retval != ERROR_OK) goto done; + if (retval != ERROR_OK) + goto done; retval = armv7a_mmu_translate_va_pa(target, virt, phys, 1); } done: @@ -2560,8 +2424,7 @@ COMMAND_HANDLER(cortex_a8_handle_cache_info_command) COMMAND_HANDLER(cortex_a8_handle_dbginit_command) { struct target *target = get_current_target(CMD_CTX); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("target not examined yet"); return ERROR_FAIL; } @@ -2571,15 +2434,13 @@ COMMAND_HANDLER(cortex_a8_handle_dbginit_command) COMMAND_HANDLER(cortex_a8_handle_smp_off_command) { struct target *target = get_current_target(CMD_CTX); - /* check target is an smp target */ - struct target_list *head; + /* check target is an smp target */ + struct target_list *head; struct target *curr; head = target->head; target->smp = 0; - if (head != (struct target_list*)NULL) - { - while (head != (struct target_list*)NULL) - { + if (head != (struct target_list *)NULL) { + while (head != (struct target_list *)NULL) { curr = head->target; curr->smp = 0; head = head->next; @@ -2596,10 +2457,9 @@ COMMAND_HANDLER(cortex_a8_handle_smp_on_command) struct target_list *head; struct target *curr; head = target->head; - if (head != (struct target_list*)NULL) - { target->smp=1; - while (head != (struct target_list*)NULL) - { + if (head != (struct target_list *)NULL) { + target->smp = 1; + while (head != (struct target_list *)NULL) { curr = head->target; curr->smp = 1; head = head->next; @@ -2614,19 +2474,17 @@ COMMAND_HANDLER(cortex_a8_handle_smp_gdb_command) int retval = ERROR_OK; struct target_list *head; head = target->head; - if (head != (struct target_list*)NULL) - { - if (CMD_ARGC == 1) - { + if (head != (struct target_list *)NULL) { + if (CMD_ARGC == 1) { int coreid = 0; COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid); if (ERROR_OK != retval) return retval; - target->gdb_service->core[1]=coreid; + target->gdb_service->core[1] = coreid; } command_print(CMD_CTX, "gdb coreid %d -> %d", target->gdb_service->core[0] - , target->gdb_service->core[1]); + , target->gdb_service->core[1]); } return ERROR_OK; } @@ -2646,22 +2504,21 @@ static const struct command_registration cortex_a8_exec_command_handlers[] = { .help = "Initialize core debug", .usage = "", }, - { .name ="smp_off", + { .name = "smp_off", .handler = cortex_a8_handle_smp_off_command, - .mode = COMMAND_EXEC, - .help = "Stop smp handling", - .usage = "", - }, + .mode = COMMAND_EXEC, + .help = "Stop smp handling", + .usage = "",}, { - .name ="smp_on", - .handler = cortex_a8_handle_smp_on_command, + .name = "smp_on", + .handler = cortex_a8_handle_smp_on_command, .mode = COMMAND_EXEC, .help = "Restart smp handling", .usage = "", }, { - .name ="smp_gdb", - .handler = cortex_a8_handle_smp_gdb_command, + .name = "smp_gdb", + .handler = cortex_a8_handle_smp_gdb_command, .mode = COMMAND_EXEC, .help = "display/fix current core played to gdb", .usage = "", diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h index e736857..f34ea67 100644 --- a/src/target/cortex_a.h +++ b/src/target/cortex_a.h @@ -26,6 +26,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef CORTEX_A8_H #define CORTEX_A8_H @@ -44,8 +45,7 @@ #define CORTEX_A8_PADDRDBG_CPU_SHIFT 13 -struct cortex_a8_brp -{ +struct cortex_a8_brp { int used; int type; uint32_t value; @@ -53,8 +53,7 @@ struct cortex_a8_brp uint8_t BRPn; }; -struct cortex_a8_common -{ +struct cortex_a8_common { int common_magic; struct arm_jtag jtag_info; @@ -65,7 +64,7 @@ struct cortex_a8_common uint32_t cp15_control_reg; /* latest cp15 register value written and cpsr processor mode */ uint32_t cp15_control_reg_curr; - enum arm_mode curr_mode; + enum arm_mode curr_mode; /* Breakpoint register pairs */ @@ -84,8 +83,7 @@ struct cortex_a8_common static inline struct cortex_a8_common * target_to_cortex_a8(struct target *target) { - return container_of(target->arch_info, struct cortex_a8_common, - armv7a_common.arm); + return container_of(target->arch_info, struct cortex_a8_common, armv7a_common.arm); } #endif /* CORTEX_A8_H */ diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 7bf6f79..625065c 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -60,10 +60,10 @@ /* forward declarations */ static int cortex_m3_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value); + enum armv7m_regtype type, uint32_t num, uint32_t value); static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, - uint32_t *value, int regnum) + uint32_t *value, int regnum) { int retval; uint32_t dcrdr; @@ -104,7 +104,7 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, } static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, - uint32_t value, int regnum) + uint32_t value, int regnum) { int retval; uint32_t dcrdr; @@ -145,7 +145,7 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, } static int cortex_m3_write_debug_halt_mask(struct target *target, - uint32_t mask_on, uint32_t mask_off) + uint32_t mask_on, uint32_t mask_off) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; @@ -195,15 +195,14 @@ static int cortex_m3_single_step_core(struct target *target) * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing * HALT can put the core into an unknown state. */ - if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) - { + if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) { retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN); if (retval != ERROR_OK) return retval; } retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, - DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); + DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN); if (retval != ERROR_OK) return retval; LOG_DEBUG(" "); @@ -230,7 +229,7 @@ static int cortex_m3_endreset_event(struct target *target) retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr); if (retval != ERROR_OK) return retval; - LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr); + LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr); /* this register is used for emulated dcc channel */ retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0); @@ -241,8 +240,7 @@ static int cortex_m3_endreset_event(struct target *target) retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (retval != ERROR_OK) return retval; - if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - { + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) { retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); if (retval != ERROR_OK) return retval; @@ -274,16 +272,14 @@ static int cortex_m3_endreset_event(struct target *target) cortex_m3->fpb_enabled = 1; /* Restore FPB registers */ - for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) - { + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value); if (retval != ERROR_OK) return retval; } /* Restore DWT registers */ - for (i = 0; i < cortex_m3->dwt_num_comp; i++) - { + for (i = 0; i < cortex_m3->dwt_num_comp; i++) { retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0, dwt_list[i].comp); if (retval != ERROR_OK) @@ -313,23 +309,20 @@ static int cortex_m3_examine_debug_reason(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */ - /* only check the debug reason if we don't know it already */ + /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason + * only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { - if (cortex_m3->nvic_dfsr & DFSR_BKPT) - { + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { + if (cortex_m3->nvic_dfsr & DFSR_BKPT) { target->debug_reason = DBG_REASON_BREAKPOINT; if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WPTANDBKPT; - } - else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) + } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP) target->debug_reason = DBG_REASON_WATCHPOINT; else if (cortex_m3->nvic_dfsr & DFSR_VCATCH) target->debug_reason = DBG_REASON_BREAKPOINT; - else /* EXTERNAL, HALTED */ + else /* EXTERNAL, HALTED */ target->debug_reason = DBG_REASON_UNDEFINED; } @@ -346,16 +339,14 @@ static int cortex_m3_examine_exception_reason(struct target *target) retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); if (retval != ERROR_OK) return retval; - switch (armv7m->exception_number) - { + switch (armv7m->exception_number) { case 2: /* NMI */ break; case 3: /* Hard Fault */ retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); if (retval != ERROR_OK) return retval; - if (except_sr & 0x40000000) - { + if (except_sr & 0x40000000) { retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); if (retval != ERROR_OK) return retval; @@ -424,15 +415,15 @@ static int cortex_m3_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; - if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK) + retval = armv7m->examine_debug_reason(target); + if (retval != ERROR_OK) return retval; - /* Examine target state and mode */ - /* First load register acessible through core debug port*/ + /* Examine target state and mode + * First load register acessible through core debug port*/ int num_regs = armv7m->core_cache->num_regs; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); } @@ -452,31 +443,27 @@ static int cortex_m3_debug_entry(struct target *target) #endif /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ - if (xPSR & 0xf00) - { + if (xPSR & 0xf00) { r->dirty = r->valid; - cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); + cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR & ~0xff); } /* Are we in an exception handler */ - if (xPSR & 0x1FF) - { + if (xPSR & 0x1FF) { armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); arm->core_mode = ARM_MODE_HANDLER; arm->map = armv7m_msp_reg_map; - } - else - { + } else { unsigned control = buf_get_u32(armv7m->core_cache ->reg_list[ARMV7M_CONTROL].value, 0, 2); /* is this thread privileged? */ armv7m->core_mode = control & 1; arm->core_mode = armv7m->core_mode - ? ARM_MODE_USER_THREAD - : ARM_MODE_THREAD; + ? ARM_MODE_USER_THREAD + : ARM_MODE_THREAD; /* which stack is it using? */ if (control & 2) @@ -488,17 +475,14 @@ static int cortex_m3_debug_entry(struct target *target) } if (armv7m->exception_number) - { cortex_m3_examine_exception_reason(target); - } LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s", armv7m_mode_strings[armv7m->core_mode], - *(uint32_t*)(arm->pc->value), + *(uint32_t *)(arm->pc->value), target_state_name(target)); - if (armv7m->post_debug_entry) - { + if (armv7m->post_debug_entry) { retval = armv7m->post_debug_entry(target); if (retval != ERROR_OK) return retval; @@ -517,8 +501,7 @@ static int cortex_m3_poll(struct target *target) /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { target->state = TARGET_UNKNOWN; return retval; } @@ -528,7 +511,7 @@ static int cortex_m3_poll(struct target *target) */ if (cortex_m3->dcb_dhcsr & S_LOCKUP) { LOG_ERROR("%s -- clearing lockup after double fault", - target_name(target)); + target_name(target)); cortex_m3_write_debug_halt_mask(target, C_HALT, 0); target->debug_reason = DBG_REASON_DBGRQ; @@ -543,39 +526,35 @@ static int cortex_m3_poll(struct target *target) return retval; } - if (cortex_m3->dcb_dhcsr & S_RESET_ST) - { + if (cortex_m3->dcb_dhcsr & S_RESET_ST) { /* check if still in reset */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (retval != ERROR_OK) return retval; - if (cortex_m3->dcb_dhcsr & S_RESET_ST) - { + if (cortex_m3->dcb_dhcsr & S_RESET_ST) { target->state = TARGET_RESET; return ERROR_OK; } } - if (target->state == TARGET_RESET) - { + if (target->state == TARGET_RESET) { /* Cannot switch context while running so endreset is * called with target->state == TARGET_RESET */ LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32, - cortex_m3->dcb_dhcsr); + cortex_m3->dcb_dhcsr); cortex_m3_endreset_event(target); target->state = TARGET_RUNNING; prev_target_state = TARGET_RUNNING; } - if (cortex_m3->dcb_dhcsr & S_HALT) - { + if (cortex_m3->dcb_dhcsr & S_HALT) { target->state = TARGET_HALTED; - if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) - { - if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) + if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) { + retval = cortex_m3_debug_entry(target); + if (retval != ERROR_OK) return retval; if (arm_semihosting(target, &retval) != 0) @@ -583,10 +562,10 @@ static int cortex_m3_poll(struct target *target) target_call_event_callbacks(target, TARGET_EVENT_HALTED); } - if (prev_target_state == TARGET_DEBUG_RUNNING) - { + if (prev_target_state == TARGET_DEBUG_RUNNING) { LOG_DEBUG(" "); - if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK) + retval = cortex_m3_debug_entry(target); + if (retval != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); @@ -597,11 +576,9 @@ static int cortex_m3_poll(struct target *target) * How best to model low power modes? */ - if (target->state == TARGET_UNKNOWN) - { + if (target->state == TARGET_UNKNOWN) { /* check if processor is retiring instructions */ - if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) - { + if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) { target->state = TARGET_RUNNING; retval = ERROR_OK; } @@ -618,26 +595,19 @@ static int cortex_m3_halt(struct target *target) LOG_DEBUG("target->state: %s", target_state_name(target)); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - { LOG_WARNING("target was in unknown state when halt was requested"); - } - if (target->state == TARGET_RESET) - { - if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) - { + if (target->state == TARGET_RESET) { + if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; - } - else - { + } else { /* we came here in a reset_halt or reset_init sequence * debug entry was already prepared in cortex_m3_prepare_reset_halt() */ @@ -678,18 +648,15 @@ static int cortex_m3_soft_reset_halt(struct target *target) /* registers are now invalid */ register_cache_invalidate(cortex_m3->armv7m.core_cache); - while (timeout < 100) - { + while (timeout < 100) { retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr); if (retval != ERROR_OK) return retval; if ((dcb_dhcsr & S_HALT) - && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) - { + && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) { LOG_DEBUG("system reset-halted, DHCSR 0x%08x, " "DFSR 0x%08x", (unsigned) dcb_dhcsr, @@ -697,8 +664,7 @@ static int cortex_m3_soft_reset_halt(struct target *target) cortex_m3_poll(target); /* FIXME restore user's vector catch config */ return ERROR_OK; - } - else + } else LOG_DEBUG("waiting for system reset-halt, " "DHCSR 0x%08x, %d ms", (unsigned) dcb_dhcsr, timeout); @@ -715,8 +681,7 @@ static void cortex_m3_enable_breakpoints(struct target *target) struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ - while (breakpoint) - { + while (breakpoint) { if (!breakpoint->set) cortex_m3_set_breakpoint(target, breakpoint); breakpoint = breakpoint->next; @@ -724,28 +689,25 @@ static void cortex_m3_enable_breakpoints(struct target *target) } static int cortex_m3_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) + uint32_t address, int handle_breakpoints, int debug_execution) { struct armv7m_common *armv7m = target_to_armv7m(target); struct breakpoint *breakpoint = NULL; uint32_t resume_pc; struct reg *r; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!debug_execution) - { + if (!debug_execution) { target_free_all_working_areas(target); cortex_m3_enable_breakpoints(target); cortex_m3_enable_watchpoints(target); } - if (debug_execution) - { + if (debug_execution) { r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK; /* Disable interrupts */ @@ -772,8 +734,7 @@ static int cortex_m3_resume(struct target *target, int current, /* current = 1: continue on current pc, otherwise continue at <address> */ r = armv7m->arm.pc; - if (!current) - { + if (!current) { buf_set_u32(r->value, 0, 32, address); r->dirty = true; r->valid = true; @@ -784,24 +745,21 @@ static int cortex_m3_resume(struct target *target, int current, * the core will break again */ if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32)) - && !debug_execution) - { + && !debug_execution) armv7m_maybe_skip_bkpt_inst(target, NULL); - } resume_pc = buf_get_u32(r->value, 0, 32); armv7m_restore_context(target); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", - breakpoint->address, - breakpoint->unique_id); + breakpoint->address, + breakpoint->unique_id); cortex_m3_unset_breakpoint(target, breakpoint); cortex_m3_single_step_core(target); cortex_m3_set_breakpoint(target, breakpoint); @@ -816,14 +774,11 @@ static int cortex_m3_resume(struct target *target, int current, /* registers are now invalid */ register_cache_invalidate(armv7m->core_cache); - if (!debug_execution) - { + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc); @@ -834,7 +789,7 @@ static int cortex_m3_resume(struct target *target, int current, /* int irqstepcount = 0; */ static int cortex_m3_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + uint32_t address, int handle_breakpoints) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; @@ -845,8 +800,7 @@ static int cortex_m3_step(struct target *target, int current, int retval; bool isr_timed_out = false; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -875,15 +829,11 @@ static int cortex_m3_step(struct target *target, int current, /* if no bkpt instruction is found at pc then we can perform * a normal step, otherwise we have to manually step over the bkpt * instruction - as such simulate a step */ - if (bkpt_inst_found == false) - { + if (bkpt_inst_found == false) { /* Automatic ISR masking mode off: Just step over the next instruction */ if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO)) - { cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); - } - else - { + else { /* Process interrupts during stepping in a way they don't interfere * debugging. * @@ -904,16 +854,13 @@ static int cortex_m3_step(struct target *target, int current, */ /* Set a temporary break point */ - retval = breakpoint_add(target, pc_value , 2, BKPT_TYPE_BY_ADDR(pc_value)); + retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value)); bool tmp_bp_set = (retval == ERROR_OK); /* No more breakpoints left, just do a step */ if (!tmp_bp_set) - { cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); - } - else - { + else { /* Start the core */ LOG_DEBUG("Starting core to serve pending interrupts"); int64_t t_start = timeval_ms(); @@ -921,9 +868,10 @@ static int cortex_m3_step(struct target *target, int current, /* Wait for pending handlers to complete or timeout */ do { - retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - if (retval != ERROR_OK) - { + retval = mem_ap_read_atomic_u32(swjdp, + DCB_DHCSR, + &cortex_m3->dcb_dhcsr); + if (retval != ERROR_OK) { target->state = TARGET_UNKNOWN; return retval; } @@ -933,15 +881,14 @@ static int cortex_m3_step(struct target *target, int current, /* Remove the temporary breakpoint */ breakpoint_remove(target, pc_value); - if (isr_timed_out) - { + if (isr_timed_out) { LOG_DEBUG("Interrupt handlers didn't complete within time, " - "leaving target running"); - } - else - { + "leaving target running"); + } else { /* Step over next instruction with interrupts disabled */ - cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0); + cortex_m3_write_debug_halt_mask(target, + C_HALT | C_MASKINTS, + 0); cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT); /* Re-enable interrupts */ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); @@ -968,8 +915,8 @@ static int cortex_m3_step(struct target *target, int current, } LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 - " nvic_icsr = 0x%" PRIx32, - cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + " nvic_icsr = 0x%" PRIx32, + cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); retval = cortex_m3_debug_entry(target); if (retval != ERROR_OK) @@ -977,8 +924,8 @@ static int cortex_m3_step(struct target *target, int current, target_call_event_callbacks(target, TARGET_EVENT_HALTED); LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 - " nvic_icsr = 0x%" PRIx32, - cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); + " nvic_icsr = 0x%" PRIx32, + cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); return ERROR_OK; } @@ -1009,8 +956,7 @@ static int cortex_m3_assert_reset(struct target *target) retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); if (retval != ERROR_OK) return retval; - if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) - { + if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) { retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN); if (retval != ERROR_OK) return retval; @@ -1020,11 +966,9 @@ static int cortex_m3_assert_reset(struct target *target) if (retval != ERROR_OK) return retval; - if (!target->reset_halt) - { + if (!target->reset_halt) { /* Set/Clear C_MASKINTS in a separate operation */ - if (cortex_m3->dcb_dhcsr & C_MASKINTS) - { + if (cortex_m3->dcb_dhcsr & C_MASKINTS) { retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); if (retval != ERROR_OK) @@ -1036,9 +980,7 @@ static int cortex_m3_assert_reset(struct target *target) /* clear C_HALT in dhcsr reg */ cortex_m3_write_debug_halt_mask(target, 0, C_HALT); - } - else - { + } else { /* Halt in debug on reset; endreset_event() restores DEMCR. * * REVISIT catching BUSERR presumably helps to defend against @@ -1051,20 +993,13 @@ static int cortex_m3_assert_reset(struct target *target) return retval; } - if (jtag_reset_config & RESET_HAS_SRST) - { + if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { jtag_add_reset(1, 1); - } else - { jtag_add_reset(0, 1); - } - } - else - { + } else { /* Use a standard Cortex-M3 software reset mechanism. * We default to using VECRESET as it is supported on all current cores. * This has the disadvantage of not resetting the peripherals, so a @@ -1077,11 +1012,11 @@ static int cortex_m3_assert_reset(struct target *target) return retval; LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ) - ? "SYSRESETREQ" : "VECTRESET"); + ? "SYSRESETREQ" : "VECTRESET"); if (reset_config == CORTEX_M3_RESET_VECTRESET) { LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event " - "handler to reset any peripherals"); + "handler to reset any peripherals"); } { @@ -1101,9 +1036,9 @@ static int cortex_m3_assert_reset(struct target *target) register_cache_invalidate(cortex_m3->armv7m.core_cache); - if (target->reset_halt) - { - if ((retval = target_halt(target)) != ERROR_OK) + if (target->reset_halt) { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; } @@ -1121,8 +1056,7 @@ static int cortex_m3_deassert_reset(struct target *target) return ERROR_OK; } -int -cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) +int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; int fp_num = 0; @@ -1130,23 +1064,18 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list; - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id); return ERROR_OK; } if (cortex_m3->auto_bp_type) - { breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); - } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code)) fp_num++; - if (fp_num >= cortex_m3->fp_num_code) - { + if (fp_num >= cortex_m3->fp_num_code) { LOG_ERROR("Can not find free FPB Comparator!"); return ERROR_FAIL; } @@ -1154,16 +1083,16 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW; comparator_list[fp_num].used = 1; comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1; - target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); - LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value); - if (!cortex_m3->fpb_enabled) - { + target_write_u32(target, comparator_list[fp_num].fpcr_address, + comparator_list[fp_num].fpcr_value); + LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", + fp_num, + comparator_list[fp_num].fpcr_value); + if (!cortex_m3->fpb_enabled) { LOG_DEBUG("FPB wasn't enabled, do it now"); target_write_u32(target, FP_CTRL, 3); } - } - else if (breakpoint->type == BKPT_SOFT) - { + } else if (breakpoint->type == BKPT_SOFT) { uint8_t code[4]; /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for @@ -1187,63 +1116,55 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint) } LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", - breakpoint->unique_id, - (int)(breakpoint->type), - breakpoint->address, - breakpoint->length, - breakpoint->set); + breakpoint->unique_id, + (int)(breakpoint->type), + breakpoint->address, + breakpoint->length, + breakpoint->set); return ERROR_OK; } -int -cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) +int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list; + struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list; - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", - breakpoint->unique_id, - (int)(breakpoint->type), - breakpoint->address, - breakpoint->length, - breakpoint->set); + breakpoint->unique_id, + (int)(breakpoint->type), + breakpoint->address, + breakpoint->length, + breakpoint->set); - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { int fp_num = breakpoint->set - 1; - if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) - { + if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) { LOG_DEBUG("Invalid FP Comparator number in breakpoint"); return ERROR_OK; } comparator_list[fp_num].used = 0; comparator_list[fp_num].fpcr_value = 0; - target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value); - } - else - { + target_write_u32(target, comparator_list[fp_num].fpcr_address, + comparator_list[fp_num].fpcr_value); + } else { /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) - { - if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK) - { + if (breakpoint->length == 4) { + retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - } - else - { - if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK) - { + } else { + retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } } } breakpoint->set = false; @@ -1251,13 +1172,11 @@ cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) return ERROR_OK; } -int -cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) +int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - if (cortex_m3->auto_bp_type) - { + if (cortex_m3->auto_bp_type) { breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); #ifdef ARMV7_GDB_HACKS if (breakpoint->length != 2) { @@ -1269,28 +1188,24 @@ cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) #endif } - if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) { - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) { + if (breakpoint->type == BKPT_HARD) { LOG_INFO("flash patch comparator requested outside code memory region"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if (breakpoint->type == BKPT_SOFT) - { + if (breakpoint->type == BKPT_SOFT) { LOG_INFO("soft breakpoint requested in code (flash) memory region"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } } - if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) { LOG_INFO("no flash patch comparator unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((breakpoint->length != 2)) - { + if ((breakpoint->length != 2)) { LOG_INFO("only breakpoints of two bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1301,27 +1216,21 @@ cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint) return cortex_m3_set_breakpoint(target, breakpoint); } -int -cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) +int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* REVISIT why check? FBP can be updated with core running ... */ - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (cortex_m3->auto_bp_type) - { breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address); - } if (breakpoint->set) - { cortex_m3_unset_breakpoint(target, breakpoint); - } if (breakpoint->type == BKPT_HARD) cortex_m3->fp_code_available++; @@ -1329,8 +1238,7 @@ cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint return ERROR_OK; } -int -cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) +int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { int dwt_num = 0; uint32_t mask, temp; @@ -1353,11 +1261,10 @@ cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) struct cortex_m3_dwt_comparator *comparator; for (comparator = cortex_m3->dwt_comparator_list; - comparator->used && dwt_num < cortex_m3->dwt_num_comp; - comparator++, dwt_num++) + comparator->used && dwt_num < cortex_m3->dwt_num_comp; + comparator++, dwt_num++) continue; - if (dwt_num >= cortex_m3->dwt_num_comp) - { + if (dwt_num >= cortex_m3->dwt_num_comp) { LOG_ERROR("Can not find free DWT Comparator"); return ERROR_FAIL; } @@ -1366,56 +1273,53 @@ cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint) comparator->comp = watchpoint->address; target_write_u32(target, comparator->dwt_comparator_address + 0, - comparator->comp); + comparator->comp); comparator->mask = mask; target_write_u32(target, comparator->dwt_comparator_address + 4, - comparator->mask); + comparator->mask); switch (watchpoint->rw) { - case WPT_READ: - comparator->function = 5; - break; - case WPT_WRITE: - comparator->function = 6; - break; - case WPT_ACCESS: - comparator->function = 7; - break; + case WPT_READ: + comparator->function = 5; + break; + case WPT_WRITE: + comparator->function = 6; + break; + case WPT_ACCESS: + comparator->function = 7; + break; } target_write_u32(target, comparator->dwt_comparator_address + 8, - comparator->function); + comparator->function); LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x", - watchpoint->unique_id, dwt_num, - (unsigned) comparator->comp, - (unsigned) comparator->mask, - (unsigned) comparator->function); + watchpoint->unique_id, dwt_num, + (unsigned) comparator->comp, + (unsigned) comparator->mask, + (unsigned) comparator->function); return ERROR_OK; } -int -cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) +int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct cortex_m3_dwt_comparator *comparator; int dwt_num; - if (!watchpoint->set) - { + if (!watchpoint->set) { LOG_WARNING("watchpoint (wpid: %d) not set", - watchpoint->unique_id); + watchpoint->unique_id); return ERROR_OK; } dwt_num = watchpoint->set - 1; LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear", - watchpoint->unique_id, dwt_num, - (unsigned) watchpoint->address); + watchpoint->unique_id, dwt_num, + (unsigned) watchpoint->address); - if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) - { + if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) { LOG_DEBUG("Invalid DWT Comparator number in watchpoint"); return ERROR_OK; } @@ -1424,20 +1328,18 @@ cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) comparator->used = 0; comparator->function = 0; target_write_u32(target, comparator->dwt_comparator_address + 8, - comparator->function); + comparator->function); watchpoint->set = false; return ERROR_OK; } -int -cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint) +int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - if (cortex_m3->dwt_comp_available < 1) - { + if (cortex_m3->dwt_comp_available < 1) { LOG_DEBUG("no comparators?"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1482,22 +1384,18 @@ cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint) return ERROR_OK; } -int -cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) +int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); /* REVISIT why check? DWT can be updated with core running ... */ - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (watchpoint->set) - { cortex_m3_unset_watchpoint(target, watchpoint); - } cortex_m3->dwt_comp_available++; LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available); @@ -1510,8 +1408,7 @@ void cortex_m3_enable_watchpoints(struct target *target) struct watchpoint *watchpoint = target->watchpoints; /* set any pending watchpoints */ - while (watchpoint) - { + while (watchpoint) { if (!watchpoint->set) cortex_m3_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; @@ -1519,7 +1416,7 @@ void cortex_m3_enable_watchpoints(struct target *target) } static int cortex_m3_load_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t * value) + enum armv7m_regtype type, uint32_t num, uint32_t *value) { int retval; struct armv7m_common *armv7m = target_to_armv7m(target); @@ -1530,59 +1427,57 @@ static int cortex_m3_load_core_reg_u32(struct target *target, * Selector values for R0..R15, xPSR, MSP, and PSP. */ switch (num) { - case 0 ... 18: - /* read a normal core register */ - retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); + case 0 ... 18: + /* read a normal core register */ + retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); - if (retval != ERROR_OK) - { - LOG_ERROR("JTAG failure %i",retval); - return ERROR_JTAG_DEVICE_ERROR; - } - LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value); - break; - - case ARMV7M_PRIMASK: - case ARMV7M_BASEPRI: - case ARMV7M_FAULTMASK: - case ARMV7M_CONTROL: - /* Cortex-M3 packages these four registers as bitfields - * in one Debug Core register. So say r0 and r2 docs; - * it was removed from r1 docs, but still works. - */ - cortexm3_dap_read_coreregister_u32(swjdp, value, 20); + if (retval != ERROR_OK) { + LOG_ERROR("JTAG failure %i", retval); + return ERROR_JTAG_DEVICE_ERROR; + } + LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value); + break; - switch (num) - { - case ARMV7M_PRIMASK: - *value = buf_get_u32((uint8_t*)value, 0, 1); - break; + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ + cortexm3_dap_read_coreregister_u32(swjdp, value, 20); - case ARMV7M_BASEPRI: - *value = buf_get_u32((uint8_t*)value, 8, 8); - break; + switch (num) { + case ARMV7M_PRIMASK: + *value = buf_get_u32((uint8_t *)value, 0, 1); + break; - case ARMV7M_FAULTMASK: - *value = buf_get_u32((uint8_t*)value, 16, 1); - break; + case ARMV7M_BASEPRI: + *value = buf_get_u32((uint8_t *)value, 8, 8); + break; - case ARMV7M_CONTROL: - *value = buf_get_u32((uint8_t*)value, 24, 2); - break; - } + case ARMV7M_FAULTMASK: + *value = buf_get_u32((uint8_t *)value, 16, 1); + break; + + case ARMV7M_CONTROL: + *value = buf_get_u32((uint8_t *)value, 24, 2); + break; + } - LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); - break; + LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); + break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return ERROR_OK; } static int cortex_m3_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, uint32_t num, uint32_t value) + enum armv7m_regtype type, uint32_t num, uint32_t value) { int retval; uint32_t reg; @@ -1606,63 +1501,61 @@ static int cortex_m3_store_core_reg_u32(struct target *target, * Selector values for R0..R15, xPSR, MSP, and PSP. */ switch (num) { - case 0 ... 18: - retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); - if (retval != ERROR_OK) - { - struct reg *r; + case 0 ... 18: + retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); + if (retval != ERROR_OK) { + struct reg *r; + + LOG_ERROR("JTAG failure"); + r = armv7m->core_cache->reg_list + num; + r->dirty = r->valid; + return ERROR_JTAG_DEVICE_ERROR; + } + LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); + break; - LOG_ERROR("JTAG failure"); - r = armv7m->core_cache->reg_list + num; - r->dirty = r->valid; - return ERROR_JTAG_DEVICE_ERROR; - } - LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - break; - - case ARMV7M_PRIMASK: - case ARMV7M_BASEPRI: - case ARMV7M_FAULTMASK: - case ARMV7M_CONTROL: - /* Cortex-M3 packages these four registers as bitfields - * in one Debug Core register. So say r0 and r2 docs; - * it was removed from r1 docs, but still works. - */ - cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ + cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); - switch (num) - { - case ARMV7M_PRIMASK: - buf_set_u32((uint8_t*)®, 0, 1, value); - break; + switch (num) { + case ARMV7M_PRIMASK: + buf_set_u32((uint8_t *)®, 0, 1, value); + break; - case ARMV7M_BASEPRI: - buf_set_u32((uint8_t*)®, 8, 8, value); - break; + case ARMV7M_BASEPRI: + buf_set_u32((uint8_t *)®, 8, 8, value); + break; - case ARMV7M_FAULTMASK: - buf_set_u32((uint8_t*)®, 16, 1, value); - break; + case ARMV7M_FAULTMASK: + buf_set_u32((uint8_t *)®, 16, 1, value); + break; - case ARMV7M_CONTROL: - buf_set_u32((uint8_t*)®, 24, 2, value); - break; - } + case ARMV7M_CONTROL: + buf_set_u32((uint8_t *)®, 24, 2, value); + break; + } - cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); + cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); - LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); - break; + LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); + break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return ERROR_OK; } static int cortex_m3_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); struct adiv5_dap *swjdp = &armv7m->dap; @@ -1671,15 +1564,15 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, /* cortex_m3 handles unaligned memory access */ if (count && buffer) { switch (size) { - case 4: - retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); - break; + case 4: + retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address); + break; + case 2: + retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address); + break; + case 1: + retval = mem_ap_read_buf_u8(swjdp, buffer, count, address); + break; } } @@ -1687,7 +1580,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, } static int cortex_m3_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); struct adiv5_dap *swjdp = &armv7m->dap; @@ -1695,15 +1588,15 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, if (count && buffer) { switch (size) { - case 4: - retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); - break; - case 2: - retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address); - break; - case 1: - retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); - break; + case 4: + retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address); + break; + case 2: + retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address); + break; + case 1: + retval = mem_ap_write_buf_u8(swjdp, buffer, count, address); + break; } } @@ -1711,13 +1604,13 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, } static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { return cortex_m3_write_memory(target, address, 4, count, buffer); } static int cortex_m3_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { armv7m_build_reg_cache(target); return ERROR_OK; @@ -1729,9 +1622,9 @@ static int cortex_m3_init_target(struct command_context *cmd_ctx, */ struct dwt_reg_state { - struct target *target; - uint32_t addr; - uint32_t value; /* scratch/cache */ + struct target *target; + uint32_t addr; + uint32_t value; /* scratch/cache */ }; static int cortex_m3_dwt_get_reg(struct reg *reg) @@ -1750,9 +1643,9 @@ static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf) } struct dwt_reg { - uint32_t addr; - char *name; - unsigned size; + uint32_t addr; + char *name; + unsigned size; }; static struct dwt_reg dwt_base_regs[] = { @@ -1781,8 +1674,7 @@ static const struct reg_arch_type dwt_reg_type = { .set = cortex_m3_dwt_set_reg, }; -static void -cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d) +static void cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d) { struct dwt_reg_state *state; @@ -1799,8 +1691,7 @@ cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d) r->type = &dwt_reg_type; } -void -cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target) +void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target) { uint32_t dwtcr; struct reg_cache *cache; @@ -1840,7 +1731,7 @@ fail1: for (reg = 0; reg < 2; reg++) cortex_m3_dwt_addreg(target, cache->reg_list + reg, - dwt_base_regs + reg); + dwt_base_regs + reg); comparator = cm3->dwt_comparator_list; for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) { @@ -1849,15 +1740,15 @@ fail1: comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i; for (j = 0; j < 3; j++, reg++) cortex_m3_dwt_addreg(target, cache->reg_list + reg, - dwt_comp + 3 * i + j); + dwt_comp + 3 * i + j); } *register_get_last_cache_p(&target->reg_cache) = cache; cm3->dwt_cache = cache; LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s", - dwtcr, cm3->dwt_num_comp, - (dwtcr & (0xf << 24)) ? " only" : "/trigger"); + dwtcr, cm3->dwt_num_comp, + (dwtcr & (0xf << 24)) ? " only" : "/trigger"); /* REVISIT: if num_comp > 1, check whether comparator #1 can * implement single-address data value watchpoints ... so we @@ -1873,11 +1764,11 @@ static int cortex_m3_examine(struct target *target) struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; - if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) + retval = ahbap_debugport_init(swjdp); + if (retval != ERROR_OK) return retval; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { target_set_examined(target); /* Read from Device Identification Registers */ @@ -1895,26 +1786,34 @@ static int cortex_m3_examine(struct target *target) /* Setup FPB */ target_read_u32(target, FP_CTRL, &fpcr); cortex_m3->auto_bp_type = 1; - cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */ + cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits + *[14:12] + *and [7:4] + **/ cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF; cortex_m3->fp_code_available = cortex_m3->fp_num_code; - cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator)); + cortex_m3->fp_comparator_list = calloc( + cortex_m3->fp_num_code + cortex_m3->fp_num_lit, + sizeof(struct cortex_m3_fp_comparator)); cortex_m3->fpb_enabled = fpcr & 1; - for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) - { - cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; + for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) { + cortex_m3->fp_comparator_list[i].type = + (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL; cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i; } - LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit); + LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", + fpcr, + cortex_m3->fp_num_code, + cortex_m3->fp_num_lit); /* Setup DWT */ cortex_m3_dwt_setup(cortex_m3, target); /* These hardware breakpoints only work for code in flash! */ LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", - target_name(target), - cortex_m3->fp_num_code, - cortex_m3->dwt_num_comp); + target_name(target), + cortex_m3->fp_num_code, + cortex_m3->dwt_num_comp); } return ERROR_OK; @@ -1925,7 +1824,7 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t * uint16_t dcrdr; int retval; - mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); + mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR); *ctrl = (uint8_t)dcrdr; *value = (uint8_t)(dcrdr >> 8); @@ -1933,10 +1832,9 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t * /* write ack back to software dcc register * signify we have read data */ - if (dcrdr & (1 << 0)) - { + if (dcrdr & (1 << 0)) { dcrdr = 0; - retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR); + retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR); if (retval != ERROR_OK) return retval; } @@ -1945,7 +1843,7 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t * } static int cortex_m3_target_request_data(struct target *target, - uint32_t size, uint8_t *buffer) + uint32_t size, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); struct adiv5_dap *swjdp = &armv7m->dap; @@ -1953,8 +1851,7 @@ static int cortex_m3_target_request_data(struct target *target, uint8_t ctrl; uint32_t i; - for (i = 0; i < (size * 4); i++) - { + for (i = 0; i < (size * 4); i++) { cortex_m3_dcc_read(swjdp, &data, &ctrl); buffer[i] = data; } @@ -1973,16 +1870,14 @@ static int cortex_m3_handle_target_request(void *priv) if (!target->dbg_msg_enabled) return ERROR_OK; - if (target->state == TARGET_RUNNING) - { + if (target->state == TARGET_RUNNING) { uint8_t data; uint8_t ctrl; cortex_m3_dcc_read(swjdp, &data, &ctrl); /* check if we have data */ - if (ctrl & (1 << 0)) - { + if (ctrl & (1 << 0)) { uint32_t request; /* we assume target is quick enough */ @@ -2001,7 +1896,7 @@ static int cortex_m3_handle_target_request(void *priv) } static int cortex_m3_init_arch_info(struct target *target, - struct cortex_m3_common *cortex_m3, struct jtag_tap *tap) + struct cortex_m3_common *cortex_m3, struct jtag_tap *tap) { int retval; struct armv7m_common *armv7m = &cortex_m3->armv7m; @@ -2036,17 +1931,16 @@ static int cortex_m3_init_arch_info(struct target *target, target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target); - if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK) - { + retval = arm_jtag_setup_connection(&cortex_m3->jtag_info); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } static int cortex_m3_target_create(struct target *target, Jim_Interp *interp) { - struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common)); + struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common)); cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC; cortex_m3_init_arch_info(target, cortex_m3, target->tap); @@ -2057,7 +1951,7 @@ static int cortex_m3_target_create(struct target *target, Jim_Interp *interp) /*--------------------------------------------------------------------------*/ static int cortex_m3_verify_pointer(struct command_context *cmd_ctx, - struct cortex_m3_common *cm3) + struct cortex_m3_common *cm3) { if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) { command_print(cmd_ctx, "target is not a Cortex-M3"); @@ -2076,14 +1970,14 @@ static const struct { char name[10]; unsigned mask; } vec_ids[] = { - { "hard_err", VC_HARDERR, }, - { "int_err", VC_INTERR, }, - { "bus_err", VC_BUSERR, }, - { "state_err", VC_STATERR, }, - { "chk_err", VC_CHKERR, }, - { "nocp_err", VC_NOCPERR, }, - { "mm_err", VC_MMERR, }, - { "reset", VC_CORERESET, }, + { "hard_err", VC_HARDERR, }, + { "int_err", VC_INTERR, }, + { "bus_err", VC_BUSERR, }, + { "state_err", VC_STATERR, }, + { "chk_err", VC_CHKERR, }, + { "nocp_err", VC_NOCPERR, }, + { "mm_err", VC_MMERR, }, + { "reset", VC_CORERESET, }, }; COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) @@ -2112,9 +2006,8 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) | VC_STATERR | VC_CHKERR | VC_NOCPERR | VC_MMERR | VC_CORERESET; goto write; - } else if (strcmp(CMD_ARGV[0], "none") == 0) { + } else if (strcmp(CMD_ARGV[0], "none") == 0) goto write; - } } while (CMD_ARGC-- > 0) { unsigned i; @@ -2150,8 +2043,7 @@ write: */ } - for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) - { + for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) { command_print(CMD_CTX, "%9s: %s", vec_ids[i].name, (demcr & vec_ids[i].mask) ? "catch" : "ignore"); } @@ -2167,9 +2059,9 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) static const Jim_Nvp nvp_maskisr_modes[] = { { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO }, - { .name = "off" , .value = CORTEX_M3_ISRMASK_OFF }, - { .name = "on" , .value = CORTEX_M3_ISRMASK_ON }, - { .name = NULL , .value = -1 }, + { .name = "off", .value = CORTEX_M3_ISRMASK_OFF }, + { .name = "on", .value = CORTEX_M3_ISRMASK_ON }, + { .name = NULL, .value = -1 }, }; const Jim_Nvp *n; @@ -2178,30 +2070,22 @@ COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]); if (n->name == NULL) - { return ERROR_COMMAND_SYNTAX_ERROR; - } cortex_m3->isrmasking_mode = n->value; - if(cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON) - { + if (cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON) cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0); - } else - { cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); - } } n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode); @@ -2221,16 +2105,14 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command) if (retval != ERROR_OK) return retval; - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { if (strcmp(*CMD_ARGV, "sysresetreq") == 0) cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ; else if (strcmp(*CMD_ARGV, "vectreset") == 0) cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET; } - switch (cortex_m3->soft_reset_config) - { + switch (cortex_m3->soft_reset_config) { case CORTEX_M3_RESET_SYSRESETREQ: reset_config = "sysresetreq"; break; @@ -2287,8 +2169,7 @@ static const struct command_registration cortex_m3_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct target_type cortexm3_target = -{ +struct target_type cortexm3_target = { .name = "cortex_m3", .poll = cortex_m3_poll, diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index 789e853..ae0c8a5 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -23,12 +23,12 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef CORTEX_M3_H #define CORTEX_M3_H #include "armv7m.h" - #define CORTEX_M3_COMMON_MAGIC 0x1A451A45 #define SYSTEM_CONTROL_BASE 0x400FE000 @@ -117,16 +117,14 @@ #define FPCR_REPLACE_BKPT_HIGH (2 << 30) #define FPCR_REPLACE_BKPT_BOTH (3 << 30) -struct cortex_m3_fp_comparator -{ +struct cortex_m3_fp_comparator { int used; int type; uint32_t fpcr_value; uint32_t fpcr_address; }; -struct cortex_m3_dwt_comparator -{ +struct cortex_m3_dwt_comparator { int used; uint32_t comp; uint32_t mask; @@ -134,21 +132,18 @@ struct cortex_m3_dwt_comparator uint32_t dwt_comparator_address; }; -enum cortex_m3_soft_reset_config -{ +enum cortex_m3_soft_reset_config { CORTEX_M3_RESET_SYSRESETREQ, CORTEX_M3_RESET_VECTRESET, }; -enum cortex_m3_isrmasking_mode -{ +enum cortex_m3_isrmasking_mode { CORTEX_M3_ISRMASK_AUTO, CORTEX_M3_ISRMASK_OFF, CORTEX_M3_ISRMASK_ON, }; -struct cortex_m3_common -{ +struct cortex_m3_common { int common_magic; struct arm_jtag jtag_info; diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index 28f8bac..1d703ee 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -30,95 +31,95 @@ #include "dsp563xx.h" #include "dsp563xx_once.h" -#define ASM_REG_W_R0 0x60F400 -#define ASM_REG_W_R1 0x61F400 -#define ASM_REG_W_R2 0x62F400 -#define ASM_REG_W_R3 0x63F400 -#define ASM_REG_W_R4 0x64F400 -#define ASM_REG_W_R5 0x65F400 -#define ASM_REG_W_R6 0x66F400 -#define ASM_REG_W_R7 0x67F400 - -#define ASM_REG_W_N0 0x70F400 -#define ASM_REG_W_N1 0x71F400 -#define ASM_REG_W_N2 0x72F400 -#define ASM_REG_W_N3 0x73F400 -#define ASM_REG_W_N4 0x74F400 -#define ASM_REG_W_N5 0x75F400 -#define ASM_REG_W_N6 0x76F400 -#define ASM_REG_W_N7 0x77F400 - -#define ASM_REG_W_M0 0x05F420 -#define ASM_REG_W_M1 0x05F421 -#define ASM_REG_W_M2 0x05F422 -#define ASM_REG_W_M3 0x05F423 -#define ASM_REG_W_M4 0x05F424 -#define ASM_REG_W_M5 0x05F425 -#define ASM_REG_W_M6 0x05F426 -#define ASM_REG_W_M7 0x05F427 - -#define ASM_REG_W_X0 0x44F400 -#define ASM_REG_W_X1 0x45F400 - -#define ASM_REG_W_Y0 0x46F400 -#define ASM_REG_W_Y1 0x47F400 - -#define ASM_REG_W_A0 0x50F400 -#define ASM_REG_W_A1 0x54F400 -#define ASM_REG_W_A2 0x52F400 - -#define ASM_REG_W_B0 0x51F400 -#define ASM_REG_W_B1 0x55F400 -#define ASM_REG_W_B2 0x53F400 - -#define ASM_REG_W_VBA 0x05F430 -#define ASM_REG_W_OMR 0x05F43A -#define ASM_REG_W_EP 0x05F42A -#define ASM_REG_W_SC 0x05F431 -#define ASM_REG_W_SZ 0x05F438 -#define ASM_REG_W_SR 0x05F439 -#define ASM_REG_W_SP 0x05F43B -#define ASM_REG_W_SSH 0x05F43C -#define ASM_REG_W_SSL 0x05F43D -#define ASM_REG_W_LA 0x05F43E -#define ASM_REG_W_LC 0x05F43F -#define ASM_REG_W_PC 0x000000 -#define ASM_REG_W_IPRC 0xFFFFFF -#define ASM_REG_W_IPRP 0xFFFFFE - -#define ASM_REG_W_BCR 0xFFFFFB -#define ASM_REG_W_DCR 0xFFFFFA -#define ASM_REG_W_AAR0 0xFFFFF9 -#define ASM_REG_W_AAR1 0xFFFFF8 -#define ASM_REG_W_AAR2 0xFFFFF7 -#define ASM_REG_W_AAR3 0xFFFFF6 +#define ASM_REG_W_R0 0x60F400 +#define ASM_REG_W_R1 0x61F400 +#define ASM_REG_W_R2 0x62F400 +#define ASM_REG_W_R3 0x63F400 +#define ASM_REG_W_R4 0x64F400 +#define ASM_REG_W_R5 0x65F400 +#define ASM_REG_W_R6 0x66F400 +#define ASM_REG_W_R7 0x67F400 + +#define ASM_REG_W_N0 0x70F400 +#define ASM_REG_W_N1 0x71F400 +#define ASM_REG_W_N2 0x72F400 +#define ASM_REG_W_N3 0x73F400 +#define ASM_REG_W_N4 0x74F400 +#define ASM_REG_W_N5 0x75F400 +#define ASM_REG_W_N6 0x76F400 +#define ASM_REG_W_N7 0x77F400 + +#define ASM_REG_W_M0 0x05F420 +#define ASM_REG_W_M1 0x05F421 +#define ASM_REG_W_M2 0x05F422 +#define ASM_REG_W_M3 0x05F423 +#define ASM_REG_W_M4 0x05F424 +#define ASM_REG_W_M5 0x05F425 +#define ASM_REG_W_M6 0x05F426 +#define ASM_REG_W_M7 0x05F427 + +#define ASM_REG_W_X0 0x44F400 +#define ASM_REG_W_X1 0x45F400 + +#define ASM_REG_W_Y0 0x46F400 +#define ASM_REG_W_Y1 0x47F400 + +#define ASM_REG_W_A0 0x50F400 +#define ASM_REG_W_A1 0x54F400 +#define ASM_REG_W_A2 0x52F400 + +#define ASM_REG_W_B0 0x51F400 +#define ASM_REG_W_B1 0x55F400 +#define ASM_REG_W_B2 0x53F400 + +#define ASM_REG_W_VBA 0x05F430 +#define ASM_REG_W_OMR 0x05F43A +#define ASM_REG_W_EP 0x05F42A +#define ASM_REG_W_SC 0x05F431 +#define ASM_REG_W_SZ 0x05F438 +#define ASM_REG_W_SR 0x05F439 +#define ASM_REG_W_SP 0x05F43B +#define ASM_REG_W_SSH 0x05F43C +#define ASM_REG_W_SSL 0x05F43D +#define ASM_REG_W_LA 0x05F43E +#define ASM_REG_W_LC 0x05F43F +#define ASM_REG_W_PC 0x000000 +#define ASM_REG_W_IPRC 0xFFFFFF +#define ASM_REG_W_IPRP 0xFFFFFE + +#define ASM_REG_W_BCR 0xFFFFFB +#define ASM_REG_W_DCR 0xFFFFFA +#define ASM_REG_W_AAR0 0xFFFFF9 +#define ASM_REG_W_AAR1 0xFFFFF8 +#define ASM_REG_W_AAR2 0xFFFFF7 +#define ASM_REG_W_AAR3 0xFFFFF6 enum once_reg_idx { - ONCE_REG_IDX_OSCR=0, - ONCE_REG_IDX_OMBC=1, - ONCE_REG_IDX_OBCR=2, - ONCE_REG_IDX_OMLR0=3, - ONCE_REG_IDX_OMLR1=4, - ONCE_REG_IDX_OGDBR=5, - ONCE_REG_IDX_OPDBR=6, - ONCE_REG_IDX_OPILR=7, - ONCE_REG_IDX_PDB=8, - ONCE_REG_IDX_OTC=9, - ONCE_REG_IDX_OPABFR=10, - ONCE_REG_IDX_OPABDR=11, - ONCE_REG_IDX_OPABEX=12, - ONCE_REG_IDX_OPABF0=13, - ONCE_REG_IDX_OPABF1=14, - ONCE_REG_IDX_OPABF2=15, - ONCE_REG_IDX_OPABF3=16, - ONCE_REG_IDX_OPABF4=17, - ONCE_REG_IDX_OPABF5=18, - ONCE_REG_IDX_OPABF6=19, - ONCE_REG_IDX_OPABF7=20, - ONCE_REG_IDX_OPABF8=21, - ONCE_REG_IDX_OPABF9=22, - ONCE_REG_IDX_OPABF10=23, - ONCE_REG_IDX_OPABF11=24, + ONCE_REG_IDX_OSCR = 0, + ONCE_REG_IDX_OMBC = 1, + ONCE_REG_IDX_OBCR = 2, + ONCE_REG_IDX_OMLR0 = 3, + ONCE_REG_IDX_OMLR1 = 4, + ONCE_REG_IDX_OGDBR = 5, + ONCE_REG_IDX_OPDBR = 6, + ONCE_REG_IDX_OPILR = 7, + ONCE_REG_IDX_PDB = 8, + ONCE_REG_IDX_OTC = 9, + ONCE_REG_IDX_OPABFR = 10, + ONCE_REG_IDX_OPABDR = 11, + ONCE_REG_IDX_OPABEX = 12, + ONCE_REG_IDX_OPABF0 = 13, + ONCE_REG_IDX_OPABF1 = 14, + ONCE_REG_IDX_OPABF2 = 15, + ONCE_REG_IDX_OPABF3 = 16, + ONCE_REG_IDX_OPABF4 = 17, + ONCE_REG_IDX_OPABF5 = 18, + ONCE_REG_IDX_OPABF6 = 19, + ONCE_REG_IDX_OPABF7 = 20, + ONCE_REG_IDX_OPABF8 = 21, + ONCE_REG_IDX_OPABF9 = 22, + ONCE_REG_IDX_OPABF10 = 23, + ONCE_REG_IDX_OPABF11 = 24, }; static struct once_reg once_regs[] = { @@ -147,76 +148,74 @@ static struct once_reg once_regs[] = { {ONCE_REG_IDX_OPABF9, DSP563XX_ONCE_OPABF11, 25, "OPABF9", 0}, {ONCE_REG_IDX_OPABF10, DSP563XX_ONCE_OPABF11, 25, "OPABF10", 0}, {ONCE_REG_IDX_OPABF11, DSP563XX_ONCE_OPABF11, 25, "OPABF11", 0}, -// {25,0x1f,24,"NRSEL",0}, +/* {25,0x1f,24,"NRSEL",0}, */ }; enum dsp563xx_reg_idx { - DSP563XX_REG_IDX_R0=0, - DSP563XX_REG_IDX_R1=1, - DSP563XX_REG_IDX_R2=2, - DSP563XX_REG_IDX_R3=3, - DSP563XX_REG_IDX_R4=4, - DSP563XX_REG_IDX_R5=5, - DSP563XX_REG_IDX_R6=6, - DSP563XX_REG_IDX_R7=7, - DSP563XX_REG_IDX_N0=8, - DSP563XX_REG_IDX_N1=9, - DSP563XX_REG_IDX_N2=10, - DSP563XX_REG_IDX_N3=11, - DSP563XX_REG_IDX_N4=12, - DSP563XX_REG_IDX_N5=13, - DSP563XX_REG_IDX_N6=14, - DSP563XX_REG_IDX_N7=15, - DSP563XX_REG_IDX_M0=16, - DSP563XX_REG_IDX_M1=17, - DSP563XX_REG_IDX_M2=18, - DSP563XX_REG_IDX_M3=19, - DSP563XX_REG_IDX_M4=20, - DSP563XX_REG_IDX_M5=21, - DSP563XX_REG_IDX_M6=22, - DSP563XX_REG_IDX_M7=23, - DSP563XX_REG_IDX_X0=24, - DSP563XX_REG_IDX_X1=25, - DSP563XX_REG_IDX_Y0=26, - DSP563XX_REG_IDX_Y1=27, - DSP563XX_REG_IDX_A0=28, - DSP563XX_REG_IDX_A1=29, - DSP563XX_REG_IDX_A2=30, - DSP563XX_REG_IDX_B0=31, - DSP563XX_REG_IDX_B1=32, - DSP563XX_REG_IDX_B2=33, - DSP563XX_REG_IDX_SSH=34, - DSP563XX_REG_IDX_SSL=35, - DSP563XX_REG_IDX_SP=36, - DSP563XX_REG_IDX_EP=37, - DSP563XX_REG_IDX_SZ=38, - DSP563XX_REG_IDX_SC=39, - DSP563XX_REG_IDX_PC=40, - DSP563XX_REG_IDX_SR=41, - DSP563XX_REG_IDX_OMR=42, - DSP563XX_REG_IDX_LA=43, - DSP563XX_REG_IDX_LC=44, - DSP563XX_REG_IDX_VBA=45, - DSP563XX_REG_IDX_IPRC=46, - DSP563XX_REG_IDX_IPRP=47, - DSP563XX_REG_IDX_BCR=48, - DSP563XX_REG_IDX_DCR=49, - DSP563XX_REG_IDX_AAR0=50, - DSP563XX_REG_IDX_AAR1=51, - DSP563XX_REG_IDX_AAR2=52, - DSP563XX_REG_IDX_AAR3=53, + DSP563XX_REG_IDX_R0 = 0, + DSP563XX_REG_IDX_R1 = 1, + DSP563XX_REG_IDX_R2 = 2, + DSP563XX_REG_IDX_R3 = 3, + DSP563XX_REG_IDX_R4 = 4, + DSP563XX_REG_IDX_R5 = 5, + DSP563XX_REG_IDX_R6 = 6, + DSP563XX_REG_IDX_R7 = 7, + DSP563XX_REG_IDX_N0 = 8, + DSP563XX_REG_IDX_N1 = 9, + DSP563XX_REG_IDX_N2 = 10, + DSP563XX_REG_IDX_N3 = 11, + DSP563XX_REG_IDX_N4 = 12, + DSP563XX_REG_IDX_N5 = 13, + DSP563XX_REG_IDX_N6 = 14, + DSP563XX_REG_IDX_N7 = 15, + DSP563XX_REG_IDX_M0 = 16, + DSP563XX_REG_IDX_M1 = 17, + DSP563XX_REG_IDX_M2 = 18, + DSP563XX_REG_IDX_M3 = 19, + DSP563XX_REG_IDX_M4 = 20, + DSP563XX_REG_IDX_M5 = 21, + DSP563XX_REG_IDX_M6 = 22, + DSP563XX_REG_IDX_M7 = 23, + DSP563XX_REG_IDX_X0 = 24, + DSP563XX_REG_IDX_X1 = 25, + DSP563XX_REG_IDX_Y0 = 26, + DSP563XX_REG_IDX_Y1 = 27, + DSP563XX_REG_IDX_A0 = 28, + DSP563XX_REG_IDX_A1 = 29, + DSP563XX_REG_IDX_A2 = 30, + DSP563XX_REG_IDX_B0 = 31, + DSP563XX_REG_IDX_B1 = 32, + DSP563XX_REG_IDX_B2 = 33, + DSP563XX_REG_IDX_SSH = 34, + DSP563XX_REG_IDX_SSL = 35, + DSP563XX_REG_IDX_SP = 36, + DSP563XX_REG_IDX_EP = 37, + DSP563XX_REG_IDX_SZ = 38, + DSP563XX_REG_IDX_SC = 39, + DSP563XX_REG_IDX_PC = 40, + DSP563XX_REG_IDX_SR = 41, + DSP563XX_REG_IDX_OMR = 42, + DSP563XX_REG_IDX_LA = 43, + DSP563XX_REG_IDX_LC = 44, + DSP563XX_REG_IDX_VBA = 45, + DSP563XX_REG_IDX_IPRC = 46, + DSP563XX_REG_IDX_IPRP = 47, + DSP563XX_REG_IDX_BCR = 48, + DSP563XX_REG_IDX_DCR = 49, + DSP563XX_REG_IDX_AAR0 = 50, + DSP563XX_REG_IDX_AAR1 = 51, + DSP563XX_REG_IDX_AAR2 = 52, + DSP563XX_REG_IDX_AAR3 = 53, }; -static const struct -{ +static const struct { unsigned id; const char *name; unsigned bits; /* effective addressing mode encoding */ uint8_t eame; uint32_t instr_mask; -} dsp563xx_regs[] = -{ +} dsp563xx_regs[] = { /* *INDENT-OFF* */ /* address registers */ {DSP563XX_REG_IDX_R0, "r0", 24, 0x10, ASM_REG_W_R0}, @@ -253,13 +252,13 @@ static const struct /* data alu accumulator register */ {DSP563XX_REG_IDX_A0, "a0", 24, 0x08, ASM_REG_W_A0}, {DSP563XX_REG_IDX_A1, "a1", 24, 0x0c, ASM_REG_W_A1}, - {DSP563XX_REG_IDX_A2, "a2", 8, 0x0a, ASM_REG_W_A2}, + {DSP563XX_REG_IDX_A2, "a2", 8, 0x0a, ASM_REG_W_A2}, {DSP563XX_REG_IDX_B0, "b0", 24, 0x09, ASM_REG_W_B0}, {DSP563XX_REG_IDX_B1, "b1", 24, 0x0d, ASM_REG_W_B1}, - {DSP563XX_REG_IDX_B2, "b2", 8, 0x0b, ASM_REG_W_B2}, + {DSP563XX_REG_IDX_B2, "b2", 8, 0x0b, ASM_REG_W_B2}, /* stack */ - {DSP563XX_REG_IDX_SSH, "ssh",24, 0x3c, ASM_REG_W_SSH}, - {DSP563XX_REG_IDX_SSL, "ssl",24, 0x3d, ASM_REG_W_SSL}, + {DSP563XX_REG_IDX_SSH, "ssh", 24, 0x3c, ASM_REG_W_SSH}, + {DSP563XX_REG_IDX_SSL, "ssl", 24, 0x3d, ASM_REG_W_SSL}, {DSP563XX_REG_IDX_SP, "sp", 24, 0x3b, ASM_REG_W_SP}, {DSP563XX_REG_IDX_EP, "ep", 24, 0x2a, ASM_REG_W_EP}, {DSP563XX_REG_IDX_SZ, "sz", 24, 0x38, ASM_REG_W_SZ}, @@ -267,34 +266,33 @@ static const struct /* system */ {DSP563XX_REG_IDX_PC, "pc", 24, 0x00, ASM_REG_W_PC}, {DSP563XX_REG_IDX_SR, "sr", 24, 0x39, ASM_REG_W_SR}, - {DSP563XX_REG_IDX_OMR, "omr",24, 0x3a, ASM_REG_W_OMR}, + {DSP563XX_REG_IDX_OMR, "omr", 24, 0x3a, ASM_REG_W_OMR}, {DSP563XX_REG_IDX_LA, "la", 24, 0x3e, ASM_REG_W_LA}, {DSP563XX_REG_IDX_LC, "lc", 24, 0x3f, ASM_REG_W_LC}, /* interrupt */ {DSP563XX_REG_IDX_VBA, "vba", 24, 0x30, ASM_REG_W_VBA}, - {DSP563XX_REG_IDX_IPRC, "iprc",24, 0x00, ASM_REG_W_IPRC}, - {DSP563XX_REG_IDX_IPRP, "iprp",24, 0x00, ASM_REG_W_IPRP}, + {DSP563XX_REG_IDX_IPRC, "iprc", 24, 0x00, ASM_REG_W_IPRC}, + {DSP563XX_REG_IDX_IPRP, "iprp", 24, 0x00, ASM_REG_W_IPRP}, /* port a */ {DSP563XX_REG_IDX_BCR, "bcr", 24, 0x00, ASM_REG_W_BCR}, {DSP563XX_REG_IDX_DCR, "dcr", 24, 0x00, ASM_REG_W_DCR}, - {DSP563XX_REG_IDX_AAR0, "aar0",24, 0x00, ASM_REG_W_AAR0}, - {DSP563XX_REG_IDX_AAR1, "aar1",24, 0x00, ASM_REG_W_AAR1}, - {DSP563XX_REG_IDX_AAR2, "aar2",24, 0x00, ASM_REG_W_AAR2}, - {DSP563XX_REG_IDX_AAR3, "aar3",24, 0x00, ASM_REG_W_AAR3}, + {DSP563XX_REG_IDX_AAR0, "aar0", 24, 0x00, ASM_REG_W_AAR0}, + {DSP563XX_REG_IDX_AAR1, "aar1", 24, 0x00, ASM_REG_W_AAR1}, + {DSP563XX_REG_IDX_AAR2, "aar2", 24, 0x00, ASM_REG_W_AAR2}, + {DSP563XX_REG_IDX_AAR3, "aar3", 24, 0x00, ASM_REG_W_AAR3}, /* *INDENT-ON* */ }; -enum memory_type -{ +enum memory_type { MEM_X = 0, MEM_Y = 1, MEM_P = 2, MEM_L = 3, }; -#define INSTR_JUMP 0x0AF080 +#define INSTR_JUMP 0x0AF080 /* Effective Addressing Mode Encoding */ -#define EAME_R0 0x10 +#define EAME_R0 0x10 /* instrcution encoder */ /* movep * s - peripheral space X/Y (X=0,Y=1) @@ -302,18 +300,19 @@ enum memory_type * d - source/destination register * p - IO short address */ -#define INSTR_MOVEP_REG_HIO(s,w,d,p) (0x084000 | ((s & 1)<<16) | ((w&1)<<15) | ((d & 0x3f)<<8) | (p & 0x3f)) +#define INSTR_MOVEP_REG_HIO(s, w, d, p) (0x084000 | \ + ((s & 1) << 16) | ((w & 1) << 15) | ((d & 0x3f) << 8) | (p & 0x3f)) /* the gdb register list is send in this order */ uint8_t gdb_reg_list_idx[] = { DSP563XX_REG_IDX_X1, DSP563XX_REG_IDX_X0, DSP563XX_REG_IDX_Y1, DSP563XX_REG_IDX_Y0, DSP563XX_REG_IDX_A2, DSP563XX_REG_IDX_A1, DSP563XX_REG_IDX_A0, DSP563XX_REG_IDX_B2, DSP563XX_REG_IDX_B1, DSP563XX_REG_IDX_B0, DSP563XX_REG_IDX_PC, DSP563XX_REG_IDX_SR, - DSP563XX_REG_IDX_OMR,DSP563XX_REG_IDX_LA, DSP563XX_REG_IDX_LC, DSP563XX_REG_IDX_SSH, - DSP563XX_REG_IDX_SSL,DSP563XX_REG_IDX_SP, DSP563XX_REG_IDX_EP, DSP563XX_REG_IDX_SZ, - DSP563XX_REG_IDX_SC, DSP563XX_REG_IDX_VBA,DSP563XX_REG_IDX_IPRC, DSP563XX_REG_IDX_IPRP, - DSP563XX_REG_IDX_BCR,DSP563XX_REG_IDX_DCR,DSP563XX_REG_IDX_AAR0,DSP563XX_REG_IDX_AAR1, - DSP563XX_REG_IDX_AAR2,DSP563XX_REG_IDX_AAR3,DSP563XX_REG_IDX_R0,DSP563XX_REG_IDX_R1, + DSP563XX_REG_IDX_OMR, DSP563XX_REG_IDX_LA, DSP563XX_REG_IDX_LC, DSP563XX_REG_IDX_SSH, + DSP563XX_REG_IDX_SSL, DSP563XX_REG_IDX_SP, DSP563XX_REG_IDX_EP, DSP563XX_REG_IDX_SZ, + DSP563XX_REG_IDX_SC, DSP563XX_REG_IDX_VBA, DSP563XX_REG_IDX_IPRC, DSP563XX_REG_IDX_IPRP, + DSP563XX_REG_IDX_BCR, DSP563XX_REG_IDX_DCR, DSP563XX_REG_IDX_AAR0, DSP563XX_REG_IDX_AAR1, + DSP563XX_REG_IDX_AAR2, DSP563XX_REG_IDX_AAR3, DSP563XX_REG_IDX_R0, DSP563XX_REG_IDX_R1, DSP563XX_REG_IDX_R2, DSP563XX_REG_IDX_R3, DSP563XX_REG_IDX_R4, DSP563XX_REG_IDX_R5, DSP563XX_REG_IDX_R6, DSP563XX_REG_IDX_R7, DSP563XX_REG_IDX_N0, DSP563XX_REG_IDX_N1, DSP563XX_REG_IDX_N2, DSP563XX_REG_IDX_N3, DSP563XX_REG_IDX_N4, DSP563XX_REG_IDX_N5, @@ -322,15 +321,15 @@ uint8_t gdb_reg_list_idx[] = { DSP563XX_REG_IDX_M6, DSP563XX_REG_IDX_M7, }; -static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) +static int dsp563xx_get_gdb_reg_list(struct target *target, + struct reg **reg_list[], + int *reg_list_size) { int i; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } *reg_list_size = DSP563XX_NUMCOREREGS; *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); @@ -339,9 +338,7 @@ static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_lis return ERROR_COMMAND_SYNTAX_ERROR; for (i = 0; i < DSP563XX_NUMCOREREGS; i++) - { (*reg_list)[i] = &dsp563xx->core_cache->reg_list[gdb_reg_list_idx[i]]; - } return ERROR_OK; @@ -385,28 +382,24 @@ static int dsp563xx_get_core_reg(struct reg *reg) struct target *target = dsp563xx_reg->target; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } return dsp563xx->read_core_reg(target, dsp563xx_reg->num); } -static int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf) +static int dsp563xx_set_core_reg(struct reg *reg, uint8_t *buf) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info; struct target *target = dsp563xx_reg->target; uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } buf_set_u32(reg->value, 0, reg->size, value); reg->dirty = 1; @@ -427,7 +420,8 @@ static void dsp563xx_build_reg_cache(struct target *target) struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS); - struct dsp563xx_core_reg *arch_info = malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS); + struct dsp563xx_core_reg *arch_info = malloc( + sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS); int i; /* Build the process context cache */ @@ -438,8 +432,7 @@ static void dsp563xx_build_reg_cache(struct target *target) (*cache_p) = cache; dsp563xx->core_cache = cache; - for (i = 0; i < DSP563XX_NUMCOREREGS; i++) - { + for (i = 0; i < DSP563XX_NUMCOREREGS; i++) { arch_info[i].num = dsp563xx_regs[i].id; arch_info[i].name = dsp563xx_regs[i].name; arch_info[i].size = dsp563xx_regs[i].bits; @@ -448,7 +441,7 @@ static void dsp563xx_build_reg_cache(struct target *target) arch_info[i].target = target; arch_info[i].dsp563xx_common = dsp563xx; reg_list[i].name = dsp563xx_regs[i].name; - reg_list[i].size = 32; //dsp563xx_regs[i].bits; + reg_list[i].size = 32; /* dsp563xx_regs[i].bits; */ reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; @@ -460,7 +453,7 @@ static void dsp563xx_build_reg_cache(struct target *target) static int dsp563xx_read_register(struct target *target, int num, int force); static int dsp563xx_write_register(struct target *target, int num, int force); -static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, uint32_t * data) +static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, uint32_t *data) { int err; uint32_t instr; @@ -472,14 +465,17 @@ static int dsp563xx_reg_read_high_io(struct target *target, uint32_t instr_mask, /* move source memory to r0 */ instr = INSTR_MOVEP_REG_HIO(MEM_X, 0, EAME_R0, instr_mask); - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr); + if (err != ERROR_OK) return err; /* move r0 to debug register */ instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, 0xfffffc); - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr); + if (err != ERROR_OK) return err; /* read debug register */ - if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data)) != ERROR_OK) + err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data); + if (err != ERROR_OK) return err; /* r0 is no longer valid on target */ dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_R0].dirty = 1; @@ -498,11 +494,13 @@ static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_R0); /* move data to r0 */ - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x60F400, data)) != ERROR_OK) + err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x60F400, data); + if (err != ERROR_OK) return err; /* move r0 to destination memory */ instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, EAME_R0, instr_mask); - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 1, instr); + if (err != ERROR_OK) return err; /* r0 is no longer valid on target */ @@ -511,16 +509,18 @@ static int dsp563xx_reg_write_high_io(struct target *target, uint32_t instr_mask return ERROR_OK; } -static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t * data) +static int dsp563xx_reg_read(struct target *target, uint32_t eame, uint32_t *data) { int err; uint32_t instr; instr = INSTR_MOVEP_REG_HIO(MEM_X, 1, eame, 0xfffffc); - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 0, instr); + if (err != ERROR_OK) return err; /* nop */ - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000); + if (err != ERROR_OK) return err; /* read debug register */ return dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OGDBR, data); @@ -530,7 +530,8 @@ static int dsp563xx_reg_write(struct target *target, uint32_t instr_mask, uint32 { int err; - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0, instr_mask, data)) != ERROR_OK) + err = dsp563xx_once_execute_dw_ir(target->tap, 0, instr_mask, data); + if (err != ERROR_OK) return err; /* nop */ return dsp563xx_once_execute_sw_ir(target->tap, 1, 0x000000); @@ -545,11 +546,10 @@ static int dsp563xx_reg_pc_read(struct target *target) return ERROR_OK; /* conditional branch check */ - if ( once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg ) - { - if ( (once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0 ) - { - LOG_DEBUG("%s conditional branch not supported yet (0x%x 0x%x 0x%x)", __FUNCTION__, + if (once_regs[ONCE_REG_IDX_OPABDR].reg == once_regs[ONCE_REG_IDX_OPABEX].reg) { + if ((once_regs[ONCE_REG_IDX_OPABF11].reg & 1) == 0) { + LOG_DEBUG("%s conditional branch not supported yet (0x%x 0x%x 0x%x)", + __func__, (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1), once_regs[ONCE_REG_IDX_OPABDR].reg, once_regs[ONCE_REG_IDX_OPABEX].reg); @@ -557,24 +557,19 @@ static int dsp563xx_reg_pc_read(struct target *target) /* TODO: use disassembly to set correct pc offset * read 2 words from OPABF11 and disasm the instruction */ - dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1) & 0x00FFFFFF; - } - else - { - if ( once_regs[ONCE_REG_IDX_OPABEX].reg == once_regs[ONCE_REG_IDX_OPABFR].reg ) - { - dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg; - } + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = + (once_regs[ONCE_REG_IDX_OPABF11].reg >> 1) & 0x00FFFFFF; + } else { + if (once_regs[ONCE_REG_IDX_OPABEX].reg == + once_regs[ONCE_REG_IDX_OPABFR].reg) + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = + once_regs[ONCE_REG_IDX_OPABEX].reg; else - { - dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg - 1; - } + dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = + once_regs[ONCE_REG_IDX_OPABEX].reg - 1; } - } - else - { + } else dsp563xx->core_regs[DSP563XX_REG_IDX_PC] = once_regs[ONCE_REG_IDX_OPABEX].reg; - } dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_PC); @@ -591,40 +586,47 @@ static int dsp563xx_reg_ssh_read(struct target *target) arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info; /* get a valid stack pointer */ - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0); + if (err != ERROR_OK) return err; sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP]; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 0); + if (err != ERROR_OK) return err; /* get a valid stack count */ - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SC, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SC, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 0)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 0); + if (err != ERROR_OK) return err; /* get a valid extended pointer */ - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_EP, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_EP, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 0)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 0); + if (err != ERROR_OK) return err; if (!sp) - { sp = 0x00FFFFFF; - } - else - { - if ((err = dsp563xx_reg_read(target, arch_info->eame, &sp)) != ERROR_OK) + else { + err = dsp563xx_reg_read(target, arch_info->eame, &sp); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 1)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SC, 1); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 1)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_EP, 1); + if (err != ERROR_OK) return err; } @@ -644,26 +646,32 @@ static int dsp563xx_reg_ssh_write(struct target *target) arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].arch_info; /* get a valid stack pointer */ - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0); + if (err != ERROR_OK) return err; sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP]; - if (sp) - { + if (sp) { sp--; /* write new stackpointer */ dsp563xx->core_regs[DSP563XX_REG_IDX_SP] = sp; - if ((err = dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SP)) != ERROR_OK) + err = dsp563xx->read_core_reg(target, DSP563XX_REG_IDX_SP); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1)) != ERROR_OK) + err = dsp563xx_write_register(target, DSP563XX_REG_IDX_SP, 1); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, dsp563xx->core_regs[DSP563XX_REG_IDX_SSH])) != ERROR_OK) + err = dsp563xx_reg_write(target, arch_info->instr_mask, + dsp563xx->core_regs[DSP563XX_REG_IDX_SSH]); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 1)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 1); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SSH, 1)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SSH, 1); + if (err != ERROR_OK) return err; } @@ -680,17 +688,16 @@ static int dsp563xx_reg_ssl_read(struct target *target) arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].arch_info; /* get a valid stack pointer */ - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SP, 0); + if (err != ERROR_OK) return err; sp = dsp563xx->core_regs[DSP563XX_REG_IDX_SP]; if (!sp) - { sp = 0x00FFFFFF; - } - else - { - if ((err = dsp563xx_reg_read(target, arch_info->eame, &sp)) != ERROR_OK) + else { + err = dsp563xx_reg_read(target, arch_info->eame, &sp); + if (err != ERROR_OK) return err; } @@ -710,12 +717,10 @@ static int dsp563xx_read_register(struct target *target, int num, int force) if (force) dsp563xx->core_cache->reg_list[num].valid = 0; - if (!dsp563xx->core_cache->reg_list[num].valid) - { + if (!dsp563xx->core_cache->reg_list[num].valid) { arch_info = dsp563xx->core_cache->reg_list[num].arch_info; - switch (arch_info->num) - { + switch (arch_info->num) { case DSP563XX_REG_IDX_SSH: err = dsp563xx_reg_ssh_read(target); break; @@ -733,23 +738,21 @@ static int dsp563xx_read_register(struct target *target, int num, int force) case DSP563XX_REG_IDX_AAR1: case DSP563XX_REG_IDX_AAR2: case DSP563XX_REG_IDX_AAR3: - err = dsp563xx_reg_read_high_io(target, arch_info->instr_mask, &data); - if (err == ERROR_OK) - { + err = dsp563xx_reg_read_high_io(target, + arch_info->instr_mask, &data); + if (err == ERROR_OK) { dsp563xx->core_regs[num] = data; dsp563xx->read_core_reg(target, num); } break; default: err = dsp563xx_reg_read(target, arch_info->eame, &data); - if (err == ERROR_OK) - { + if (err == ERROR_OK) { dsp563xx->core_regs[num] = data; dsp563xx->read_core_reg(target, num); } break; } - } return err; @@ -764,14 +767,12 @@ static int dsp563xx_write_register(struct target *target, int num, int force) if (force) dsp563xx->core_cache->reg_list[num].dirty = 1; - if (dsp563xx->core_cache->reg_list[num].dirty) - { + if (dsp563xx->core_cache->reg_list[num].dirty) { arch_info = dsp563xx->core_cache->reg_list[num].arch_info; dsp563xx->write_core_reg(target, num); - switch (arch_info->num) - { + switch (arch_info->num) { case DSP563XX_REG_IDX_SSH: err = dsp563xx_reg_ssh_write(target); break; @@ -786,15 +787,20 @@ static int dsp563xx_write_register(struct target *target, int num, int force) case DSP563XX_REG_IDX_AAR1: case DSP563XX_REG_IDX_AAR2: case DSP563XX_REG_IDX_AAR3: - err = dsp563xx_reg_write_high_io(target, arch_info->instr_mask, dsp563xx->core_regs[num]); + err = dsp563xx_reg_write_high_io(target, + arch_info->instr_mask, + dsp563xx->core_regs[num]); break; default: - err = dsp563xx_reg_write(target, arch_info->instr_mask, dsp563xx->core_regs[num]); - - if ((err == ERROR_OK) && (arch_info->num == DSP563XX_REG_IDX_SP)) - { - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0; - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0; + err = dsp563xx_reg_write(target, + arch_info->instr_mask, + dsp563xx->core_regs[num]); + + if ((err == ERROR_OK) && (arch_info->num == DSP563XX_REG_IDX_SP)) { + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = + 0; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = + 0; } break; @@ -808,9 +814,9 @@ static int dsp563xx_save_context(struct target *target) { int i, err = ERROR_OK; - for (i = 0; i < DSP563XX_NUMCOREREGS; i++) - { - if ((err = dsp563xx_read_register(target, i, 0)) != ERROR_OK) + for (i = 0; i < DSP563XX_NUMCOREREGS; i++) { + err = dsp563xx_read_register(target, i, 0); + if (err != ERROR_OK) break; } @@ -821,40 +827,40 @@ static int dsp563xx_restore_context(struct target *target) { int i, err = ERROR_OK; - for (i = 0; i < DSP563XX_NUMCOREREGS; i++) - { - if ((err = dsp563xx_write_register(target, i, 0)) != ERROR_OK) + for (i = 0; i < DSP563XX_NUMCOREREGS; i++) { + err = dsp563xx_write_register(target, i, 0); + if (err != ERROR_OK) break; } return err; } -static void dsp563xx_invalidate_x_context(struct target *target, uint32_t addr_start, uint32_t addr_end ) +static void dsp563xx_invalidate_x_context(struct target *target, + uint32_t addr_start, + uint32_t addr_end) { int i; struct dsp563xx_core_reg *arch_info; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - if ( addr_start > ASM_REG_W_IPRC ) + if (addr_start > ASM_REG_W_IPRC) return; - if ( addr_start < ASM_REG_W_AAR3 ) + if (addr_start < ASM_REG_W_AAR3) return; - for (i = DSP563XX_REG_IDX_IPRC; i < DSP563XX_NUMCOREREGS; i++) - { + for (i = DSP563XX_REG_IDX_IPRC; i < DSP563XX_NUMCOREREGS; i++) { arch_info = dsp563xx->core_cache->reg_list[i].arch_info; - if ( (arch_info->instr_mask >= addr_start) && - (arch_info->instr_mask <= addr_end)) - { + if ((arch_info->instr_mask >= addr_start) && + (arch_info->instr_mask <= addr_end)) { dsp563xx->core_cache->reg_list[i].valid = 0; dsp563xx->core_cache->reg_list[i].dirty = 0; } } } -static int dsp563xx_target_create(struct target *target, Jim_Interp * interp) +static int dsp563xx_target_create(struct target *target, Jim_Interp *interp) { struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common)); @@ -871,7 +877,7 @@ static int dsp563xx_target_create(struct target *target, Jim_Interp * interp) static int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); dsp563xx_build_reg_cache(target); @@ -882,24 +888,21 @@ static int dsp563xx_examine(struct target *target) { uint32_t chip; - if (target->tap->hasidcode == false) - { + if (target->tap->hasidcode == false) { LOG_ERROR("no IDCODE present on device"); - return ERROR_COMMAND_SYNTAX_ERROR; } - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { target_set_examined(target); /* examine core and chip derivate number */ - chip = (target->tap->idcode>>12)&0x3ff; + chip = (target->tap->idcode>>12) & 0x3ff; /* core number 0 means DSP563XX */ - if ( ((chip>>5)&0x1f) == 0 ) + if (((chip>>5)&0x1f) == 0) chip += 300; - LOG_INFO("DSP56%03d device found",chip); + LOG_INFO("DSP56%03d device found", chip); } return ERROR_OK; @@ -907,12 +910,12 @@ static int dsp563xx_examine(struct target *target) static int dsp563xx_arch_state(struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } -#define DSP563XX_SR_SA (1<<17) -#define DSP563XX_SR_SC (1<<13) +#define DSP563XX_SR_SA (1<<17) +#define DSP563XX_SR_SC (1<<13) static int dsp563xx_debug_once_init(struct target *target) { @@ -926,68 +929,75 @@ static int dsp563xx_debug_init(struct target *target) struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); struct dsp563xx_core_reg *arch_info; - if ((err = dsp563xx_debug_once_init(target)) != ERROR_OK) + err = dsp563xx_debug_once_init(target); + if (err != ERROR_OK) return err; arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].arch_info; /* check 24bit mode */ - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SR, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_SR, 0); + if (err != ERROR_OK) return err; sr = dsp563xx->core_regs[DSP563XX_REG_IDX_SR]; - if (sr & (DSP563XX_SR_SA | DSP563XX_SR_SC)) - { + if (sr & (DSP563XX_SR_SA | DSP563XX_SR_SC)) { sr &= ~(DSP563XX_SR_SA | DSP563XX_SR_SC); - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr)) != ERROR_OK) + err = dsp563xx_once_execute_dw_ir(target->tap, 1, arch_info->instr_mask, sr); + if (err != ERROR_OK) return err; dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SR].dirty = 1; } - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N0, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N1, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_N1, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M0, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M0, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M1, 0)) != ERROR_OK) + err = dsp563xx_read_register(target, DSP563XX_REG_IDX_M1, 0); + if (err != ERROR_OK) return err; - if (dsp563xx->core_regs[DSP563XX_REG_IDX_N0] != 0x000000) - { + if (dsp563xx->core_regs[DSP563XX_REG_IDX_N0] != 0x000000) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].arch_info; - if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000)) != ERROR_OK) + err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000); + if (err != ERROR_OK) return err; } dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N0].dirty = 1; - if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) - { + if (dsp563xx->core_regs[DSP563XX_REG_IDX_N1] != 0x000000) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].arch_info; - if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000)) != ERROR_OK) + err = dsp563xx_reg_write(target, arch_info->instr_mask, 0x000000); + if (err != ERROR_OK) return err; } dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_N1].dirty = 1; - if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) - { + if (dsp563xx->core_regs[DSP563XX_REG_IDX_M0] != 0xffffff) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].arch_info; - if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff)) != ERROR_OK) + err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff); + if (err != ERROR_OK) return err; } dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M0].dirty = 1; - if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) - { + if (dsp563xx->core_regs[DSP563XX_REG_IDX_M1] != 0xffffff) { arch_info = dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].arch_info; - if ((err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff)) != ERROR_OK) + err = dsp563xx_reg_write(target, arch_info->instr_mask, 0xffffff); + if (err != ERROR_OK) return err; } dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_M1].dirty = 1; - if ((err = dsp563xx_save_context(target)) != ERROR_OK) + err = dsp563xx_save_context(target); + if (err != ERROR_OK) return err; return ERROR_OK; @@ -1002,42 +1012,36 @@ static int dsp563xx_poll(struct target *target) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - uint32_t once_status=0; + uint32_t once_status = 0; int state; state = dsp563xx_once_target_status(target->tap); - if (state == TARGET_UNKNOWN) - { + if (state == TARGET_UNKNOWN) { target->state = state; LOG_ERROR("jtag status contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status)) != ERROR_OK) + err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status); + if (err != ERROR_OK) return err; - if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M) - { - if (target->state != TARGET_HALTED) - { + if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M) { + if (target->state != TARGET_HALTED) { target->state = TARGET_HALTED; - if ((err = dsp563xx_debug_init(target)) != ERROR_OK) + err = dsp563xx_debug_init(target); + if (err != ERROR_OK) return err; - if ( once_status & (DSP563XX_ONCE_OSCR_MBO|DSP563XX_ONCE_OSCR_SWO) ) - { + if (once_status & (DSP563XX_ONCE_OSCR_MBO|DSP563XX_ONCE_OSCR_SWO)) target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); - } else - { target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } - - LOG_DEBUG("target->state: %s (%x)", target_state_name(target),once_status); - LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC] ); + LOG_DEBUG("target->state: %s (%x)", target_state_name(target), once_status); + LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC]); } } @@ -1048,20 +1052,18 @@ static int dsp563xx_halt(struct target *target) { int err; - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - { LOG_WARNING("target was in unknown state when halt was requested"); - } - if ((err = dsp563xx_jtag_debug_request(target)) != ERROR_OK) + err = dsp563xx_jtag_debug_request(target); + if (err != ERROR_OK) return err; target->debug_reason = DBG_REASON_DBGRQ; @@ -1069,7 +1071,11 @@ static int dsp563xx_halt(struct target *target) return ERROR_OK; } -static int dsp563xx_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static int dsp563xx_resume(struct target *target, + int current, + uint32_t address, + int handle_breakpoints, + int debug_execution) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); @@ -1080,35 +1086,38 @@ static int dsp563xx_resume(struct target *target, int current, uint32_t address, * this will not affect the resume command with an address argument * because current is set to zero then */ - if ( current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty ) - { - dsp563xx_write_core_reg(target,DSP563XX_REG_IDX_PC); + if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) { + dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC); address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC]; current = 0; } - LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address); + LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address); - if ((err = dsp563xx_restore_context(target)) != ERROR_OK) + err = dsp563xx_restore_context(target); + if (err != ERROR_OK) return err; register_cache_invalidate(dsp563xx->core_cache); - if (current) - { + if (current) { /* restore pipeline registers and go */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, once_regs[ONCE_REG_IDX_OPILR].reg)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, + once_regs[ONCE_REG_IDX_OPILR].reg); + if (err != ERROR_OK) return err; - if ((err = - dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, - once_regs[ONCE_REG_IDX_OPDBR].reg)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR | + DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, + once_regs[ONCE_REG_IDX_OPDBR].reg); + if (err != ERROR_OK) return err; - } - else - { + } else { /* set to go register and jump */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO | + DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address); + if (err != ERROR_OK) return err; } @@ -1119,15 +1128,18 @@ static int dsp563xx_resume(struct target *target, int current, uint32_t address, return ERROR_OK; } -static int dsp563xx_step_ex(struct target *target, int current, uint32_t address, int handle_breakpoints, int steps) +static int dsp563xx_step_ex(struct target *target, + int current, + uint32_t address, + int handle_breakpoints, + int steps) { int err; uint32_t once_status; uint32_t dr_in, cnt; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_DEBUG("target was not halted"); return ERROR_OK; } @@ -1138,25 +1150,28 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address * this will not affect the step command with an address argument * because current is set to zero then */ - if ( current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty ) - { - dsp563xx_write_core_reg(target,DSP563XX_REG_IDX_PC); + if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) { + dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC); address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC]; current = 0; } - LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address); + LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address); - if ((err = dsp563xx_jtag_debug_request(target)) != ERROR_OK) + err = dsp563xx_jtag_debug_request(target); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_restore_context(target)) != ERROR_OK) + err = dsp563xx_restore_context(target); + if (err != ERROR_OK) return err; /* reset trace mode */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000); + if (err != ERROR_OK) return err; /* enable trace mode */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, DSP563XX_ONCE_OSCR_TME)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, DSP563XX_ONCE_OSCR_TME); + if (err != ERROR_OK) return err; cnt = steps; @@ -1166,51 +1181,60 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address cnt++; /* load step counter with N-1 */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, cnt)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OTC, cnt); + if (err != ERROR_OK) return err; - if (current) - { + if (current) { /* restore pipeline registers and go */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, once_regs[ONCE_REG_IDX_OPILR].reg)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, + once_regs[ONCE_REG_IDX_OPILR].reg); + if (err != ERROR_OK) return err; - if ((err = - dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, - once_regs[ONCE_REG_IDX_OPDBR].reg)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR | + DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, + once_regs[ONCE_REG_IDX_OPDBR].reg); + if (err != ERROR_OK) return err; - } - else - { + } else { /* set to go register and jump */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OPDBR, INSTR_JUMP); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, address)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_PDBGOTO | + DSP563XX_ONCE_OCR_EX | DSP563XX_ONCE_OCR_GO, + address); + if (err != ERROR_OK) return err; } - while (1) - { - if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status)) != ERROR_OK) + while (1) { + err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OSCR, &once_status); + if (err != ERROR_OK) return err; - if (once_status & DSP563XX_ONCE_OSCR_TO) - { - if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in)) != ERROR_OK) + if (once_status & DSP563XX_ONCE_OSCR_TO) { + err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in); + if (err != ERROR_OK) return err; LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff); - if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in)) != ERROR_OK) + err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in); + if (err != ERROR_OK) return err; LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff); - if ((err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in)) != ERROR_OK) + err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in); + if (err != ERROR_OK) return err; LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff); /* reset trace mode */ - if ((err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000)) != ERROR_OK) + err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000); + if (err != ERROR_OK) return err; register_cache_invalidate(dsp563xx->core_cache); - if ((err = dsp563xx_debug_init(target)) != ERROR_OK) + err = dsp563xx_debug_init(target); + if (err != ERROR_OK) return err; break; @@ -1220,26 +1244,27 @@ static int dsp563xx_step_ex(struct target *target, int current, uint32_t address return ERROR_OK; } -static int dsp563xx_step(struct target *target, int current, uint32_t address, int handle_breakpoints) +static int dsp563xx_step(struct target *target, + int current, + uint32_t address, + int handle_breakpoints) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if ( (err=dsp563xx_step_ex(target, current, address, handle_breakpoints, 0)) != ERROR_OK ) - { + err = dsp563xx_step_ex(target, current, address, handle_breakpoints, 0); + if (err != ERROR_OK) return err; - } target->debug_reason = DBG_REASON_SINGLESTEP; target_call_event_callbacks(target, TARGET_EVENT_HALTED); - LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC] ); + LOG_INFO("halted: PC: 0x%x", dsp563xx->core_regs[DSP563XX_REG_IDX_PC]); return err; } @@ -1250,17 +1275,12 @@ static int dsp563xx_assert_reset(struct target *target) struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); enum reset_types jtag_reset_config = jtag_get_reset_config(); - if (jtag_reset_config & RESET_HAS_SRST) - { + if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { jtag_add_reset(1, 1); - } else - { jtag_add_reset(0, 1); - } } target->state = TARGET_RESET; @@ -1269,13 +1289,13 @@ static int dsp563xx_assert_reset(struct target *target) /* registers are now invalid */ register_cache_invalidate(dsp563xx->core_cache); - if (target->reset_halt) - { - if ((retval = target_halt(target)) != ERROR_OK) + if (target->reset_halt) { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; } - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } @@ -1286,119 +1306,110 @@ static int dsp563xx_deassert_reset(struct target *target) /* deassert reset lines */ jtag_add_reset(0, 0); - if ((err = dsp563xx_poll(target)) != ERROR_OK) + err = dsp563xx_poll(target); + if (err != ERROR_OK) return err; - if (target->reset_halt) - { - if (target->state == TARGET_HALTED) - { + if (target->reset_halt) { + if (target->state == TARGET_HALTED) { /* after a reset the cpu jmp to the * reset vector and need 2 cycles to fill * the cache (fetch,decode,excecute) */ - if ((err = dsp563xx_step_ex(target, 1, 0, 1, 1)) != ERROR_OK) + err = dsp563xx_step_ex(target, 1, 0, 1, 1); + if (err != ERROR_OK) return err; } - } - else - { + } else target->state = TARGET_RUNNING; - } - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int dsp563xx_soft_reset_halt(struct target *target) { - LOG_DEBUG("%s", __FUNCTION__); + LOG_DEBUG("%s", __func__); return ERROR_OK; } static int dsp563xx_run_algorithm(struct target *target, - int num_mem_params, struct mem_param *mem_params, - int num_reg_params, struct reg_param *reg_params, - uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info) + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { int i; int retval = ERROR_OK; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - for (i = 0; i < num_mem_params; i++) - { - if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK) - { + for (i = 0; i < num_mem_params; i++) { + retval = target_write_buffer(target, mem_params[i].address, + mem_params[i].size, mem_params[i].value); + if (retval != ERROR_OK) return retval; - } } - for (i = 0; i < num_reg_params; i++) - { - struct reg *reg = register_get_by_name(dsp563xx->core_cache, reg_params[i].reg_name, 0); + for (i = 0; i < num_reg_params; i++) { + struct reg *reg = register_get_by_name(dsp563xx->core_cache, + reg_params[i].reg_name, + 0); - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); continue; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + if (reg->size != reg_params[i].size) { + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); continue; } - if ((retval = dsp563xx_set_core_reg(reg, reg_params[i].value)) != ERROR_OK) - { + retval = dsp563xx_set_core_reg(reg, reg_params[i].value); + if (retval != ERROR_OK) return retval; - } } /* exec */ - if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) - { + retval = target_resume(target, 0, entry_point, 1, 1); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) - { + retval = target_wait_state(target, TARGET_HALTED, timeout_ms); + if (retval != ERROR_OK) return retval; - } - for (i = 0; i < num_mem_params; i++) - { + for (i = 0; i < num_mem_params; i++) { if (mem_params[i].direction != PARAM_OUT) retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); - if (retval != ERROR_OK) - return retval; + if (retval != ERROR_OK) + return retval; } - for (i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { + for (i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction != PARAM_OUT) { - struct reg *reg = register_get_by_name(dsp563xx->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { + struct reg *reg = register_get_by_name(dsp563xx->core_cache, + reg_params[i].reg_name, + 0); + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); continue; } - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + if (reg->size != reg_params[i].size) { + LOG_ERROR( + "BUG: register '%s' size doesn't match reg_params[i].size", + reg_params[i].reg_name); continue; } @@ -1415,29 +1426,28 @@ extern struct command_context *global_cmd_ctx; static int dsp563xx_get_default_memory(void) { Jim_Interp *interp; - Jim_Obj * memspace; - char * c; + Jim_Obj *memspace; + char *c; - if ( !global_cmd_ctx ) + if (!global_cmd_ctx) return MEM_P; interp = global_cmd_ctx->interp; - if ( !interp ) + if (!interp) return MEM_P; - memspace = Jim_GetGlobalVariableStr(interp,"memspace", JIM_NONE); + memspace = Jim_GetGlobalVariableStr(interp, "memspace", JIM_NONE); - if ( !memspace ) + if (!memspace) return MEM_P; - c = (char*)Jim_GetString(memspace,NULL); + c = (char *)Jim_GetString(memspace, NULL); - if ( !c ) + if (!c) return MEM_P; - switch(c[0]) - { + switch (c[0]) { case '1': return MEM_X; case '2': @@ -1451,7 +1461,12 @@ static int dsp563xx_get_default_memory(void) return MEM_P; } -static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) +static int dsp563xx_read_memory_core(struct target *target, + int mem_type, + uint32_t address, + uint32_t size, + uint32_t count, + uint8_t *buffer) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); @@ -1459,16 +1474,19 @@ static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32 uint32_t data, move_cmd = 0; uint8_t *b; - LOG_DEBUG("memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", mem_type,address, size, count); + LOG_DEBUG( + "memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + mem_type, + address, + size, + count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - switch (mem_type) - { + switch (mem_type) { case MEM_X: /* TODO: mark effected queued registers */ move_cmd = 0x61d800; @@ -1498,33 +1516,35 @@ static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32 x = count; b = buffer; - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address)) != ERROR_OK) + err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address); + if (err != ERROR_OK) return err; - for (i = 0; i < x; i++) - { - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd)) != ERROR_OK) + for (i = 0; i < x; i++) { + err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, 0x08D13C)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 0, 0x08D13C); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_once_reg_read(target->tap, 0, DSP563XX_ONCE_OGDBR, (uint32_t*)(void *)b)) != ERROR_OK) + err = dsp563xx_once_reg_read(target->tap, 0, + DSP563XX_ONCE_OGDBR, (uint32_t *)(void *)b); + if (err != ERROR_OK) return err; b += 4; } /* flush the jtag queue */ - if ((err = jtag_execute_queue()) != ERROR_OK) - { + err = jtag_execute_queue(); + if (err != ERROR_OK) return err; - } /* walk over the buffer and fix target endianness */ b = buffer; - for (i = 0; i < x; i++) - { + for (i = 0; i < x; i++) { data = buf_get_u32(b, 0, 32) & 0x00FFFFFF; -// LOG_DEBUG("R: %08X", *((uint32_t*)b)); +/* LOG_DEBUG("R: %08X", *((uint32_t*)b)); */ target_buffer_set_u32(target, b, data); b += 4; } @@ -1532,71 +1552,67 @@ static int dsp563xx_read_memory_core(struct target *target, int mem_type, uint32 return ERROR_OK; } -static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) +static int dsp563xx_read_memory(struct target *target, + int mem_type, + uint32_t address, + uint32_t size, + uint32_t count, + uint8_t *buffer) { int err; - uint32_t i,i1; - uint8_t *buffer_y,*buffer_x; + uint32_t i, i1; + uint8_t *buffer_y, *buffer_x; /* if size equals zero we are called from target read memory * and have to handle the parameter here */ - if ( (size == 0) && (count != 0) ) - { + if ((size == 0) && (count != 0)) { size = count % 4; - if ( size ) - { + if (size) LOG_DEBUG("size is not aligned to 4 byte"); - } count = (count - size) / 4; - size = 4; + size = 4; } /* we only support 4 byte aligned data */ - if ( (size != 4) || (!count) ) - { + if ((size != 4) || (!count)) return ERROR_COMMAND_SYNTAX_ERROR; - } - if ( mem_type != MEM_L ) - { - return dsp563xx_read_memory_core(target,mem_type,address,size,count,buffer); - } + if (mem_type != MEM_L) + return dsp563xx_read_memory_core(target, mem_type, address, size, count, buffer); - if ( !(buffer_y = malloc(size*count)) ) - { + buffer_y = malloc(size * count); + if (!buffer_y) return ERROR_COMMAND_SYNTAX_ERROR; - } - if ( !(buffer_x = malloc(size*count)) ) - { + buffer_x = malloc(size * count); + if (!buffer_x) { free(buffer_y); return ERROR_COMMAND_SYNTAX_ERROR; } - err = dsp563xx_read_memory_core(target,MEM_Y,address,size,count/2,buffer_y); + err = dsp563xx_read_memory_core(target, MEM_Y, address, size, count / 2, buffer_y); - if ( err != ERROR_OK ) - { + if (err != ERROR_OK) { free(buffer_y); free(buffer_x); return err; } - err = dsp563xx_read_memory_core(target,MEM_X,address,size,count/2,buffer_x); + err = dsp563xx_read_memory_core(target, MEM_X, address, size, count / 2, buffer_x); - if ( err != ERROR_OK ) - { + if (err != ERROR_OK) { free(buffer_y); free(buffer_x); return err; } - for(i=0,i1=0;i<count;i+=2,i1++) - { - buf_set_u32(buffer + i*sizeof(uint32_t), 0, 32, buf_get_u32(buffer_y+i1*sizeof(uint32_t), 0, 32)); - buf_set_u32(buffer + (i + 1) *sizeof(uint32_t), 0, 32, buf_get_u32(buffer_x+i1*sizeof(uint32_t), 0, 32)); + for (i = 0, i1 = 0; i < count; i += 2, i1++) { + buf_set_u32(buffer + i*sizeof(uint32_t), 0, 32, + buf_get_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32)); + buf_set_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32, + buf_get_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32)); } free(buffer_y); @@ -1605,19 +1621,33 @@ static int dsp563xx_read_memory(struct target *target, int mem_type, uint32_t ad return ERROR_OK; } -static int dsp563xx_read_memory_default(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t * buffer) +static int dsp563xx_read_memory_default(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + uint8_t *buffer) { - return dsp563xx_read_memory(target, dsp563xx_get_default_memory(), address, size, count, buffer); + return dsp563xx_read_memory(target, + dsp563xx_get_default_memory(), address, size, count, buffer); } -static int dsp563xx_read_buffer_default(struct target *target, uint32_t address, uint32_t size, uint8_t * buffer) +static int dsp563xx_read_buffer_default(struct target *target, + uint32_t address, + uint32_t size, + uint8_t *buffer) { - return dsp563xx_read_memory(target, dsp563xx_get_default_memory(), address, size, 0, buffer); + return dsp563xx_read_memory(target, dsp563xx_get_default_memory(), address, size, 0, + buffer); } -static int dsp563xx_write_memory_core(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer) +static int dsp563xx_write_memory_core(struct target *target, + int mem_type, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) { int err; struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); @@ -1625,19 +1655,22 @@ static int dsp563xx_write_memory_core(struct target *target, int mem_type, uint3 uint32_t data, move_cmd = 0; const uint8_t *b; - LOG_DEBUG("memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", mem_type,address, size, count); + LOG_DEBUG( + "memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + mem_type, + address, + size, + count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - switch (mem_type) - { + switch (mem_type) { case MEM_X: /* invalidate affected x registers */ - dsp563xx_invalidate_x_context(target,address,address+count-1); + dsp563xx_invalidate_x_context(target, address, address + count - 1); move_cmd = 0x615800; break; case MEM_Y: @@ -1665,95 +1698,92 @@ static int dsp563xx_write_memory_core(struct target *target, int mem_type, uint3 x = count; b = buffer; - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address)) != ERROR_OK) + err = dsp563xx_once_execute_dw_ir(target->tap, 1, 0x60F400, address); + if (err != ERROR_OK) return err; - for (i = 0; i < x; i++) - { + for (i = 0; i < x; i++) { data = target_buffer_get_u32(target, b); -// LOG_DEBUG("W: %08X", data); +/* LOG_DEBUG("W: %08X", data); */ data &= 0x00ffffff; - if ((err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x61F400, data)) != ERROR_OK) + err = dsp563xx_once_execute_dw_ir(target->tap, 0, 0x61F400, data); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd)) != ERROR_OK) + err = dsp563xx_once_execute_sw_ir(target->tap, 0, move_cmd); + if (err != ERROR_OK) return err; b += 4; } /* flush the jtag queue */ - if ((err = jtag_execute_queue()) != ERROR_OK) - { + err = jtag_execute_queue(); + if (err != ERROR_OK) return err; - } return ERROR_OK; } -static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer) +static int dsp563xx_write_memory(struct target *target, + int mem_type, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) { int err; - uint32_t i,i1; - uint8_t *buffer_y,*buffer_x; + uint32_t i, i1; + uint8_t *buffer_y, *buffer_x; /* if size equals zero we are called from target write memory * and have to handle the parameter here */ - if ( (size == 0) && (count != 0) ) - { + if ((size == 0) && (count != 0)) { size = count % 4; - if ( size ) - { + if (size) LOG_DEBUG("size is not aligned to 4 byte"); - } count = (count - size) / 4; - size = 4; + size = 4; } /* we only support 4 byte aligned data */ - if ( (size != 4) || (!count) ) - { + if ((size != 4) || (!count)) return ERROR_COMMAND_SYNTAX_ERROR; - } - if ( mem_type != MEM_L ) - { - return dsp563xx_write_memory_core(target,mem_type,address,size,count,buffer); - } + if (mem_type != MEM_L) + return dsp563xx_write_memory_core(target, mem_type, address, size, count, buffer); - if ( !(buffer_y = malloc(size*count)) ) - { + buffer_y = malloc(size * count); + if (!buffer_y) return ERROR_COMMAND_SYNTAX_ERROR; - } - if ( !(buffer_x = malloc(size*count)) ) - { + buffer_x = malloc(size * count); + if (!buffer_x) { free(buffer_y); return ERROR_COMMAND_SYNTAX_ERROR; } - for(i=0,i1=0;i<count;i+=2,i1++) - { - buf_set_u32(buffer_y + i1*sizeof(uint32_t), 0, 32, buf_get_u32(buffer+i*sizeof(uint32_t), 0, 32)); - buf_set_u32(buffer_x + i1*sizeof(uint32_t), 0, 32, buf_get_u32(buffer+(i+1)*sizeof(uint32_t), 0, 32)); + for (i = 0, i1 = 0; i < count; i += 2, i1++) { + buf_set_u32(buffer_y + i1 * sizeof(uint32_t), 0, 32, + buf_get_u32(buffer + i * sizeof(uint32_t), 0, 32)); + buf_set_u32(buffer_x + i1 * sizeof(uint32_t), 0, 32, + buf_get_u32(buffer + (i + 1) * sizeof(uint32_t), 0, 32)); } - err = dsp563xx_write_memory_core(target,MEM_Y,address,size,count/2,buffer_y); + err = dsp563xx_write_memory_core(target, MEM_Y, address, size, count / 2, buffer_y); - if ( err != ERROR_OK ) - { + if (err != ERROR_OK) { free(buffer_y); free(buffer_x); return err; } - err = dsp563xx_write_memory_core(target,MEM_X,address,size,count/2,buffer_x); + err = dsp563xx_write_memory_core(target, MEM_X, address, size, count / 2, buffer_x); - if ( err != ERROR_OK ) - { + if (err != ERROR_OK) { free(buffer_y); free(buffer_x); return err; @@ -1765,19 +1795,32 @@ static int dsp563xx_write_memory(struct target *target, int mem_type, uint32_t a return ERROR_OK; } -static int dsp563xx_write_memory_default(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer) +static int dsp563xx_write_memory_default(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) { - return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, size, count, buffer); + return dsp563xx_write_memory(target, + dsp563xx_get_default_memory(), address, size, count, buffer); } -static int dsp563xx_write_buffer_default(struct target *target, uint32_t address, uint32_t size, const uint8_t * buffer) +static int dsp563xx_write_buffer_default(struct target *target, + uint32_t address, + uint32_t size, + const uint8_t *buffer) { - return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, size, 0, buffer); + return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, size, 0, + buffer); } -static int dsp563xx_bulk_write_memory_default(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer) +static int dsp563xx_bulk_write_memory_default(struct target *target, + uint32_t address, + uint32_t count, + const uint8_t *buffer) { - return dsp563xx_write_memory(target, dsp563xx_get_default_memory(), address, 4, count, buffer); + return dsp563xx_write_memory(target, + dsp563xx_get_default_memory(), address, 4, count, buffer); } static int dsp563xx_add_breakpoint(struct target *target, struct breakpoint *breakpoint) @@ -1800,7 +1843,12 @@ static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint * return ERROR_OK; } -static void handle_md_output(struct command_context *cmd_ctx, struct target *target, uint32_t address, unsigned size, unsigned count, const uint8_t * buffer) +static void handle_md_output(struct command_context *cmd_ctx, + struct target *target, + uint32_t address, + unsigned size, + unsigned count, + const uint8_t *buffer) { const unsigned line_bytecnt = 32; unsigned line_modulo = line_bytecnt / size; @@ -1809,8 +1857,7 @@ static void handle_md_output(struct command_context *cmd_ctx, struct target *tar unsigned output_len = 0; const char *value_fmt; - switch (size) - { + switch (size) { case 4: value_fmt = "%8.8x "; break; @@ -1826,17 +1873,16 @@ static void handle_md_output(struct command_context *cmd_ctx, struct target *tar return; } - for (unsigned i = 0; i < count; i++) - { + for (unsigned i = 0; i < count; i++) { if (i % line_modulo == 0) - { - output_len += snprintf(output + output_len, sizeof(output) - output_len, "0x%8.8x: ", (unsigned) (address + i)); - } + output_len += snprintf(output + output_len, + sizeof(output) - output_len, + "0x%8.8x: ", + (unsigned) (address + i)); uint32_t value = 0; const uint8_t *value_ptr = buffer + i * size; - switch (size) - { + switch (size) { case 4: value = target_buffer_get_u32(target, value_ptr); break; @@ -1846,10 +1892,12 @@ static void handle_md_output(struct command_context *cmd_ctx, struct target *tar case 1: value = *value_ptr; } - output_len += snprintf(output + output_len, sizeof(output) - output_len, value_fmt, value); + output_len += snprintf(output + output_len, + sizeof(output) - output_len, + value_fmt, + value); - if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) - { + if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) { command_print(cmd_ctx, "%s", output); output_len = 0; } @@ -1867,8 +1915,7 @@ COMMAND_HANDLER(dsp563xx_mem_command) uint32_t mem_type; uint8_t *buffer, *b; - switch (CMD_NAME[1]) - { + switch (CMD_NAME[1]) { case 'w': read_mem = 0; break; @@ -1879,8 +1926,7 @@ COMMAND_HANDLER(dsp563xx_mem_command) return ERROR_COMMAND_SYNTAX_ERROR; } - switch (CMD_NAME[3]) - { + switch (CMD_NAME[3]) { case 'x': mem_type = MEM_X; break; @@ -1895,56 +1941,46 @@ COMMAND_HANDLER(dsp563xx_mem_command) } if (CMD_ARGC > 0) - { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); - } - if (read_mem == 0) - { + if (read_mem == 0) { if (CMD_ARGC < 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } if (CMD_ARGC > 1) - { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], pattern); - } if (CMD_ARGC > 2) - { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count); - } } - if (read_mem == 1) - { + if (read_mem == 1) { if (CMD_ARGC < 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } if (CMD_ARGC > 1) - { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count); - } } buffer = calloc(count, sizeof(uint32_t)); - if (read_mem == 1) - { - if ((err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t), count, buffer)) == ERROR_OK) + if (read_mem == 1) { + err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t), + count, buffer); + if (err == ERROR_OK) handle_md_output(CMD_CTX, target, address, sizeof(uint32_t), count, buffer); - } - else - { + + } else { b = buffer; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { target_buffer_set_u32(target, b, pattern); b += 4; } - err = dsp563xx_write_memory(target, mem_type, address, sizeof(uint32_t), count, buffer); + err = dsp563xx_write_memory(target, + mem_type, + address, + sizeof(uint32_t), + count, + buffer); } free(buffer); @@ -1954,47 +1990,47 @@ COMMAND_HANDLER(dsp563xx_mem_command) static const struct command_registration dsp563xx_command_handlers[] = { { - .name = "mwwx", - .handler = dsp563xx_mem_command, - .mode = COMMAND_EXEC, - .help = "write x memory words", - .usage = "mwwx address value [count]", - }, - { - .name = "mwwy", - .handler = dsp563xx_mem_command, - .mode = COMMAND_EXEC, - .help = "write y memory words", - .usage = "mwwy address value [count]", - }, - { - .name = "mwwp", - .handler = dsp563xx_mem_command, - .mode = COMMAND_EXEC, - .help = "write p memory words", - .usage = "mwwp address value [count]", - }, - { - .name = "mdwx", - .handler = dsp563xx_mem_command, - .mode = COMMAND_EXEC, - .help = "display x memory words", - .usage = "mdwx address [count]", - }, - { - .name = "mdwy", - .handler = dsp563xx_mem_command, - .mode = COMMAND_EXEC, - .help = "display y memory words", - .usage = "mdwy address [count]", - }, - { - .name = "mdwp", - .handler = dsp563xx_mem_command, - .mode = COMMAND_EXEC, - .help = "display p memory words", - .usage = "mdwp address [count]", - }, + .name = "mwwx", + .handler = dsp563xx_mem_command, + .mode = COMMAND_EXEC, + .help = "write x memory words", + .usage = "mwwx address value [count]", + }, + { + .name = "mwwy", + .handler = dsp563xx_mem_command, + .mode = COMMAND_EXEC, + .help = "write y memory words", + .usage = "mwwy address value [count]", + }, + { + .name = "mwwp", + .handler = dsp563xx_mem_command, + .mode = COMMAND_EXEC, + .help = "write p memory words", + .usage = "mwwp address value [count]", + }, + { + .name = "mdwx", + .handler = dsp563xx_mem_command, + .mode = COMMAND_EXEC, + .help = "display x memory words", + .usage = "mdwx address [count]", + }, + { + .name = "mdwy", + .handler = dsp563xx_mem_command, + .mode = COMMAND_EXEC, + .help = "display y memory words", + .usage = "mdwy address [count]", + }, + { + .name = "mdwp", + .handler = dsp563xx_mem_command, + .mode = COMMAND_EXEC, + .help = "display p memory words", + .usage = "mdwp address [count]", + }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/dsp563xx.h b/src/target/dsp563xx.h index 67ff8d5..cb7c4b1 100644 --- a/src/target/dsp563xx.h +++ b/src/target/dsp563xx.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef DSP563XX_H #define DSP563XX_H @@ -26,25 +27,22 @@ #define DSP563XX_NUMCOREREGS 54 #define DSP563XX_NUMONCEREGS 25 -struct mcu_jtag -{ +struct mcu_jtag { struct jtag_tap *tap; }; -struct dsp563xx_common -{ +struct dsp563xx_common { struct mcu_jtag jtag_info; struct reg_cache *core_cache; uint32_t core_regs[DSP563XX_NUMCOREREGS]; struct once_reg once_regs[DSP563XX_NUMONCEREGS]; /* register cache to processor synchronization */ - int (*read_core_reg) (struct target * target, int num); - int (*write_core_reg) (struct target * target, int num); + int (*read_core_reg) (struct target *target, int num); + int (*write_core_reg) (struct target *target, int num); }; -struct dsp563xx_core_reg -{ +struct dsp563xx_core_reg { uint32_t num; const char *name; uint32_t size; diff --git a/src/target/dsp563xx_once.c b/src/target/dsp563xx_once.c index 267f475..8d62b48 100644 --- a/src/target/dsp563xx_once.c +++ b/src/target/dsp563xx_once.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -63,7 +64,7 @@ static inline int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * dr_in, ui /** */ static inline int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out, int dr_len, int rti) { - return dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti); + return dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) &dr_out, dr_len, rti); } /** single word instruction */ @@ -71,9 +72,10 @@ static inline int dsp563xx_once_ir_exec(struct jtag_tap *tap, int flush, uint8_t { int err; - if ((err = dsp563xx_write_dr_u8(tap, 0, instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u8(tap, 0, instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0); + if (err != ERROR_OK) return err; - if ( flush ) + if (flush) err = jtag_execute_queue(); return err; } @@ -102,13 +104,15 @@ int dsp563xx_once_target_status(struct jtag_tap *tap) int err; uint8_t jtag_status; - if ((err = dsp563xx_jtag_sendinstr(tap, &jtag_status, JTAG_INSTR_ENABLE_ONCE)) != ERROR_OK) + err = dsp563xx_jtag_sendinstr(tap, &jtag_status, JTAG_INSTR_ENABLE_ONCE); + if (err != ERROR_OK) return TARGET_UNKNOWN; - if ((err = jtag_execute_queue()) != ERROR_OK) + err = jtag_execute_queue(); + if (err != ERROR_OK) return TARGET_UNKNOWN; /* verify correct static status pattern */ - if ( (jtag_status & JTAG_STATUS_STATIC_MASK) != JTAG_STATUS_STATIC_VALUE ) + if ((jtag_status & JTAG_STATUS_STATIC_MASK) != JTAG_STATUS_STATIC_VALUE) return TARGET_UNKNOWN; if (jtag_status != JTAG_STATUS_DEBUG) @@ -127,59 +131,50 @@ int dsp563xx_once_request_debug(struct jtag_tap *tap, int reset_state) /* in reset state we only get a ACK * from the interface */ if (reset_state) - { pattern = 1; - } else - { pattern = JTAG_STATUS_DEBUG; - } /* wait until we get the ack */ - while (ir_in != pattern) - { - if ((err = dsp563xx_jtag_sendinstr(tap, &ir_in, JTAG_INSTR_DEBUG_REQUEST)) != ERROR_OK) + while (ir_in != pattern) { + err = dsp563xx_jtag_sendinstr(tap, &ir_in, JTAG_INSTR_DEBUG_REQUEST); + if (err != ERROR_OK) return err; - if ((err = jtag_execute_queue()) != ERROR_OK) + err = jtag_execute_queue(); + if (err != ERROR_OK) return err; LOG_DEBUG("debug request: %02X", ir_in); if (retry++ == 100) - { return ERROR_TARGET_FAILURE; - } } /* we cant enable the once in reset state */ if (pattern == 1) - { return ERROR_OK; - } /* try to enable once */ retry = 0; ir_in = 0; - while (ir_in != pattern) - { - if ((err = dsp563xx_jtag_sendinstr(tap, &ir_in, JTAG_INSTR_ENABLE_ONCE)) != ERROR_OK) + while (ir_in != pattern) { + err = dsp563xx_jtag_sendinstr(tap, &ir_in, JTAG_INSTR_ENABLE_ONCE); + if (err != ERROR_OK) return err; - if ((err = jtag_execute_queue()) != ERROR_OK) + err = jtag_execute_queue(); + if (err != ERROR_OK) return err; LOG_DEBUG("enable once: %02X", ir_in); - if (retry++ == 100) - { + if (retry++ == 100) { LOG_DEBUG("error"); return ERROR_TARGET_FAILURE; } } if (ir_in != JTAG_STATUS_DEBUG) - { return ERROR_TARGET_FAILURE; - } return ERROR_OK; } @@ -190,13 +185,13 @@ int dsp563xx_once_read_register(struct jtag_tap *tap, int flush, struct once_reg int i; int err = ERROR_OK; - for (i = 0; i < len; i++) - { - if ((err = dsp563xx_once_reg_read_ex(tap, flush, regs[i].addr, regs[i].len, ®s[i].reg)) != ERROR_OK) + for (i = 0; i < len; i++) { + err = dsp563xx_once_reg_read_ex(tap, flush, regs[i].addr, regs[i].len, ®s[i].reg); + if (err != ERROR_OK) return err; } - if ( flush ) + if (flush) err = jtag_execute_queue(); return err; } @@ -206,11 +201,13 @@ int dsp563xx_once_reg_read_ex(struct jtag_tap *tap, int flush, uint8_t reg, uint { int err; - if ((err = dsp563xx_once_ir_exec(tap, 1, reg, 1, 0, 0)) != ERROR_OK) + err = dsp563xx_once_ir_exec(tap, 1, reg, 1, 0, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_dr_u32(tap, data, 0x00, len, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u32(tap, data, 0x00, len, 0); + if (err != ERROR_OK) return err; - if ( flush ) + if (flush) err = jtag_execute_queue(); return err; } @@ -220,11 +217,13 @@ int dsp563xx_once_reg_read(struct jtag_tap *tap, int flush, uint8_t reg, uint32_ { int err; - if ((err = dsp563xx_once_ir_exec(tap, flush, reg, 1, 0, 0)) != ERROR_OK) + err = dsp563xx_once_ir_exec(tap, flush, reg, 1, 0, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_dr_u32(tap, data, 0x00, 24, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u32(tap, data, 0x00, 24, 0); + if (err != ERROR_OK) return err; - if ( flush ) + if (flush) err = jtag_execute_queue(); return err; } @@ -234,11 +233,13 @@ int dsp563xx_once_reg_write(struct jtag_tap *tap, int flush, uint8_t reg, uint32 { int err; - if ((err = dsp563xx_once_ir_exec(tap, flush, reg, 0, 0, 0)) != ERROR_OK) + err = dsp563xx_once_ir_exec(tap, flush, reg, 0, 0, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_dr_u32(tap, 0x00, data, 24, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u32(tap, 0x00, data, 24, 0); + if (err != ERROR_OK) return err; - if ( flush ) + if (flush) err = jtag_execute_queue(); return err; } @@ -248,11 +249,13 @@ int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, int flush, uint32_t opcode { int err; - if ((err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 1, 0)) != ERROR_OK) + err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 1, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + if (err != ERROR_OK) return err; - if ( flush ) + if (flush) err = jtag_execute_queue(); return err; } @@ -262,21 +265,29 @@ int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, int flush, uint32_t opcode { int err; - if ((err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 0, 0)) != ERROR_OK) + err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 0, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + if (err != ERROR_OK) return err; - if ( flush ) - if ((err = jtag_execute_queue()) != ERROR_OK) + if (flush) { + err = jtag_execute_queue(); + if (err != ERROR_OK) return err; + } - if ((err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 1, 0)) != ERROR_OK) + err = dsp563xx_once_ir_exec(tap, flush, DSP563XX_ONCE_OPDBR, 0, 1, 0); + if (err != ERROR_OK) return err; - if ((err = dsp563xx_write_dr_u32(tap, 0, operand, 24, 0)) != ERROR_OK) + err = dsp563xx_write_dr_u32(tap, 0, operand, 24, 0); + if (err != ERROR_OK) return err; - if ( flush ) - if ((err = jtag_execute_queue()) != ERROR_OK) + if (flush) { + err = jtag_execute_queue(); + if (err != ERROR_OK) return err; + } return ERROR_OK; } diff --git a/src/target/dsp563xx_once.h b/src/target/dsp563xx_once.h index 1ba9c1e..a2a0737 100644 --- a/src/target/dsp563xx_once.h +++ b/src/target/dsp563xx_once.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef DSP563XX_ONCE_H #define DSP563XX_ONCE_H @@ -57,8 +58,7 @@ #define DSP563XX_ONCE_OPABF11 0x012 /* trace buffer/inc ptr */ #define DSP563XX_ONCE_NOREG 0x01F /* no register selected */ -struct once_reg -{ +struct once_reg { uint8_t num; uint8_t addr; uint8_t len; diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c index 7b43313..5a25846 100644 --- a/src/target/dsp5680xx.c +++ b/src/target/dsp5680xx.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -1542,7 +1543,7 @@ static int perl_crc(uint8_t *buff8, uint32_t word_count) data = (buff8[2 * i] | (buff8[2 * i + 1] << 8)); fbmisr = (checksum & 2) >> 1 ^ (checksum & 4) >> 2 ^ (checksum & 16) - >> 4 ^ (checksum & 0x8000) >> 15; + >> 4 ^ (checksum & 0x8000) >> 15; checksum = (data ^ ((checksum << 1) | fbmisr)); } i--; @@ -1978,13 +1979,13 @@ int dsp5680xx_f_erase(struct target *target, int first, int last) */ const uint16_t pgm_write_pflash[] = { 0x8A46, 0x0013, 0x807D, 0xE700, - 0xE700, 0x8A44, 0xFFFE, 0x017B, - 0xE700, 0xF514, 0x8563, 0x8646, - 0x0020, 0x0014, 0x8646, 0x0080, - 0x0013, 0xF042, 0x0013, 0x8B40, - 0x2004, 0x8246, 0x0013, 0x0020, - 0xA967, 0x8B40, 0x1065, 0x8246, - 0x0013, 0x0010, 0xA961 + 0xE700, 0x8A44, 0xFFFE, 0x017B, + 0xE700, 0xF514, 0x8563, 0x8646, + 0x0020, 0x0014, 0x8646, 0x0080, + 0x0013, 0xF042, 0x0013, 0x8B40, + 0x2004, 0x8246, 0x0013, 0x0020, + 0xA967, 0x8B40, 0x1065, 0x8246, + 0x0013, 0x0010, 0xA961 }; const uint32_t pgm_write_pflash_length = 31; diff --git a/src/target/dsp5680xx.h b/src/target/dsp5680xx.h index 71405d4..a607a5b 100644 --- a/src/target/dsp5680xx.h +++ b/src/target/dsp5680xx.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef DSP5680XX_H #define DSP5680XX_H @@ -29,12 +30,12 @@ * @file dsp5680xx.h * @author Rodrigo Rosa <rodrigorosa.LG@gmail.com> * @date Thu Jun 9 18:54:38 2011 - * + * * @brief Basic support for the 5680xx DSP from Freescale. * The chip has two taps in the JTAG chain, the Master tap and the Core tap. * In this code the Master tap is only used to unlock the flash memory by executing a JTAG instruction. - * - * + * + * */ #define S_FILE_DATA_OFFSET 0x200000 @@ -153,7 +154,7 @@ * ---------------------------------------------------------------- */ -#define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well. +#define FLUSH_COUNT_READ_WRITE 8192 /* This value works, higher values (and lower...) may work as well. */ #define FLUSH_COUNT_FLASH 8192 /** ---------------------------------------------------------------- * HFM (flash module) Commands (ref:MC56F801xRM.pdf@159) @@ -201,7 +202,7 @@ /** * The value used on for the FM clock is important to prevent flashing errors and to prevent deterioration of the FM. * This value was calculated using a spreadsheet tool available on the Freescale website under FAQ 25464. - * + * */ #define HFM_CLK_DEFAULT 0x27 /* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */ @@ -299,73 +300,86 @@ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target return target->arch_info; } -/** +/** * Writes to flash memory. - * Does not check if flash is erased, it's up to the user to erase the flash before running this function. - * The flashing algorithm runs from RAM, reading from a register to which this function writes to. The algorithm is open loop, there is no control to verify that the FM read the register before writing the next data. A closed loop approach was much slower, and the current implementation does not fail, and if it did the crc check would detect it, allowing to flash again. - * - * @param target - * @param buffer + * Does not check if flash is erased, it's up to the user to erase the flash before running + * this function. + * The flashing algorithm runs from RAM, reading from a register to which this function + * writes to. The algorithm is open loop, there is no control to verify that the FM read + * the register before writing the next data. A closed loop approach was much slower, + * and the current implementation does not fail, and if it did the crc check would detect it, + * allowing to flash again. + * + * @param target + * @param buffer * @param address Word addressing. - * @param count In bytes. - * @param verify_flash Execute a CRC check after flashing. - * - * @return + * @param count In bytes. + * @param verify_flash Execute a CRC check after flashing. + * + * @return */ int dsp5680xx_f_wr(struct target *target, uint8_t * buffer, uint32_t address, - uint32_t count, int is_flash_lock); + uint32_t count, int is_flash_lock); -/** - * The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis. - * - * @param target - * @param erased - * @param sector This parameter is ignored because the FM does not support checking if individual sectors are erased. - * - * @return +/** + * The FM has the funcionality of checking if the flash array is erased. This function + * executes it. It does not support individual sector analysis. + * + * @param target + * @param erased + * @param sector This parameter is ignored because the FM does not support checking if + * individual sectors are erased. + * + * @return */ int dsp5680xx_f_erase_check(struct target *target, uint8_t * erased, - uint32_t sector); + uint32_t sector); -/** - * Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if @first == 0 and @last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased. - * - * @param target - * @param first - * @param last - * - * @return +/** + * Erases either a sector or the complete flash array. If either the range first-last covers + * the complete array or if @first == 0 and @last == 0 then a mass erase command is executed + * on the FM. If not, then individual sectors are erased. + * + * @param target + * @param first + * @param last + * + * @return */ int dsp5680xx_f_erase(struct target *target, int first, int last); -/** - * Reads the memory mapped protection register. A 1 implies the sector is protected, a 0 implies the sector is not protected. - * - * @param target +/** + * Reads the memory mapped protection register. A 1 implies the sector is protected, + * a 0 implies the sector is not protected. + * + * @param target * @param protected Data read from the protection register. - * - * @return + * + * @return */ int dsp5680xx_f_protect_check(struct target *target, uint16_t * protected); -/** - * Writes the flash security words with a specific value. The chip's security will be enabled after the first reset following the execution of this function. - * - * @param target - * - * @return +/** + * Writes the flash security words with a specific value. The chip's security will be + * enabled after the first reset following the execution of this function. + * + * @param target + * + * @return */ int dsp5680xx_f_lock(struct target *target); -/** +/** * Executes a mass erase command. The must be done from the Master tap. - * It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp) before running this function. - * The flash array will be unsecured (and erased) after the first reset following the execution of this function. - * - * @param target - * - * @return + * It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp) + * before running this function. + * The flash array will be unsecured (and erased) after the first reset following + * the execution of this function. + * + * @param target + * + * @return */ int dsp5680xx_f_unlock(struct target *target); -#endif /* dsp5680xx.h */ +#endif /* dsp5680xx.h */ diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 77e85df..a795695 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -87,7 +88,7 @@ static const struct { .addr = 9, .width = 32, }, - [EICE_W0_DATA_VALUE ] = { + [EICE_W0_DATA_VALUE] = { .name = "watch_0_data_value", .addr = 10, .width = 32, @@ -145,14 +146,16 @@ static const struct { }, }; - static int embeddedice_get_reg(struct reg *reg) { - int retval; - - if ((retval = embeddedice_read_reg(reg)) != ERROR_OK) + int retval = embeddedice_read_reg(reg); + if (retval != ERROR_OK) { LOG_ERROR("error queueing EmbeddedICE register read"); - else if ((retval = jtag_execute_queue()) != ERROR_OK) + return retval; + } + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) LOG_ERROR("EmbeddedICE register read failed"); return retval; @@ -168,8 +171,8 @@ static const struct reg_arch_type eice_reg_type = { * Different versions of the modules have different capabilities, such as * hardware support for vector_catch, single stepping, and monitor mode. */ -struct reg_cache * -embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) +struct reg_cache *embeddedice_build_reg_cache(struct target *target, + struct arm7_9_common *arm7_9) { int retval; struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); @@ -200,8 +203,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) */ /* set up registers */ - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { reg_list[i].name = eice_regs[i].name; reg_list[i].size = eice_regs[i].width; reg_list[i].dirty = 0; @@ -215,12 +217,10 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { for (i = 0; i < num_regs; i++) - { free(reg_list[i].value); - } free(reg_list); free(reg_cache); free(arch_info); @@ -230,8 +230,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4); LOG_INFO("Embedded ICE version %d", eice_version); - switch (eice_version) - { + switch (eice_version) { case 1: /* ARM7TDMI r3, ARM7TDMI-S r3 * @@ -290,7 +289,7 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9) * and do the appropriate setup itself. */ if (strcmp(target_type_name(target), "feroceon") == 0 || - strcmp(target_type_name(target), "dragonite") == 0) + strcmp(target_type_name(target), "dragonite") == 0) break; LOG_ERROR("unknown EmbeddedICE version " "(comms ctrl: 0x%8.8" PRIx32 ")", @@ -318,12 +317,12 @@ int embeddedice_setup(struct target *target) * that manages break requests. ARM's "Angel Debug Monitor" is one * common example of such code. */ - if (arm7_9->has_monitor_mode) - { + if (arm7_9->has_monitor_mode) { struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; buf_set_u32(dbg_ctrl->value, 4, 1, 0); embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); @@ -350,7 +349,8 @@ int embeddedice_read_reg_w_check(struct reg *reg, if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(ice_reg->jtag_info, + ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -435,8 +435,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); - while (size > 0) - { + while (size > 0) { /* when reading the last item, set the register address to the DCC control reg, * to avoid reading additional data from the DCC data reg */ @@ -486,7 +485,8 @@ static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) int retval; embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size)); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) LOG_ERROR("register write failed"); return retval; } @@ -555,8 +555,7 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) fields[2].in_value = NULL; - while (size > 0) - { + while (size > 0) { buf_set_u32(field0_out, 0, 32, *data); jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); @@ -586,8 +585,7 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou hsact = 1; else if (hsbit == EICE_COMM_CTRL_RBIT) hsact = 0; - else - { + else { LOG_ERROR("Invalid arguments"); return ERROR_COMMAND_SYNTAX_ERROR; } @@ -617,7 +615,8 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou gettimeofday(&lap, NULL); do { jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; if (buf_get_u32(field0_in, hsbit, 1) == hsact) @@ -640,8 +639,7 @@ void embeddedice_write_dcc(struct jtag_tap *tap, { int i; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little)); buffer += 4; diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index 66fef0a..58a5fa9 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -23,13 +23,13 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef EMBEDDED_ICE_H #define EMBEDDED_ICE_H #include "arm7_9_common.h" -enum -{ +enum { EICE_DBG_CTRL = 0, EICE_DBG_STAT = 1, EICE_COMMS_CTRL = 2, @@ -49,8 +49,7 @@ enum EICE_VEC_CATCH = 16 }; -enum -{ +enum { EICE_DBG_CONTROL_ICEDIS = 5, EICE_DBG_CONTROL_MONEN = 4, EICE_DBG_CONTROL_INTDIS = 2, @@ -58,8 +57,7 @@ enum EICE_DBG_CONTROL_DBGACK = 0, }; -enum -{ +enum { EICE_DBG_STATUS_IJBIT = 5, EICE_DBG_STATUS_ITBIT = 4, EICE_DBG_STATUS_SYSCOMP = 3, @@ -68,8 +66,7 @@ enum EICE_DBG_STATUS_DBGACK = 0 }; -enum -{ +enum { EICE_W_CTRL_ENABLE = 0x100, EICE_W_CTRL_RANGE = 0x80, EICE_W_CTRL_CHAIN = 0x40, @@ -81,26 +78,24 @@ enum EICE_W_CTRL_nRW = 0x1 }; -enum -{ +enum { EICE_COMM_CTRL_WBIT = 1, EICE_COMM_CTRL_RBIT = 0 }; -struct embeddedice_reg -{ +struct embeddedice_reg { int addr; struct arm_jtag *jtag_info; }; -struct reg_cache* embeddedice_build_reg_cache(struct target *target, +struct reg_cache *embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9); int embeddedice_setup(struct target *target); int embeddedice_read_reg(struct reg *reg); int embeddedice_read_reg_w_check(struct reg *reg, - uint8_t* check_value, uint8_t* check_mask); + uint8_t *check_value, uint8_t *check_mask); void embeddedice_write_reg(struct reg *reg, uint32_t value); void embeddedice_store_reg(struct reg *reg); @@ -112,10 +107,10 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size); int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeout); -/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of - * embeddedice_write_reg +/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be + * this faster version of embeddedice_write_reg */ -static __inline__ void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value) +static inline void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value) { static const int embeddedice_num_bits[] = {32, 6}; uint32_t values[2]; @@ -123,13 +118,10 @@ static __inline__ void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg values[0] = value; values[1] = (1 << 5) | reg_addr; - jtag_add_dr_out(tap, - 2, - embeddedice_num_bits, - values, - TAP_IDLE); + jtag_add_dr_out(tap, 2, embeddedice_num_bits, values, TAP_IDLE); } -void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, int little, int count); +void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, const uint8_t *buffer, + int little, int count); #endif /* EMBEDDED_ICE_H */ diff --git a/src/target/etb.c b/src/target/etb.c index 974ab2b..bc38b3a 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -26,9 +27,7 @@ #include "etb.h" #include "register.h" - -static char* etb_reg_list[] = -{ +static char *etb_reg_list[] = { "ETB_identification", "ETB_ram_depth", "ETB_ram_width", @@ -50,12 +49,11 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr) if (tap == NULL) return ERROR_FAIL; - if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) - { + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { struct scan_field field; field.num_bits = tap->ir_length; - void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); field.out_value = t; buf_set_u32(t, 0, field.num_bits, new_instr); @@ -71,12 +69,11 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr) static int etb_scann(struct etb *etb, uint32_t new_scan_chain) { - if (etb->cur_scan_chain != new_scan_chain) - { + if (etb->cur_scan_chain != new_scan_chain) { struct scan_field field; field.num_bits = 5; - void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); + void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1); field.out_value = t; buf_set_u32(t, 0, field.num_bits, new_scan_chain); @@ -106,14 +103,14 @@ static int etb_get_reg(struct reg *reg) { int retval; - if ((retval = etb_read_reg(reg)) != ERROR_OK) - { + retval = etb_read_reg(reg); + if (retval != ERROR_OK) { LOG_ERROR("BUG: error scheduling ETB register read"); return retval; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("ETB register read failed"); return retval; } @@ -126,7 +123,7 @@ static const struct reg_arch_type etb_reg_type = { .set = etb_set_reg_w_exec, }; -struct reg_cache* etb_build_reg_cache(struct etb *etb) +struct reg_cache *etb_build_reg_cache(struct etb *etb) { struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = NULL; @@ -145,8 +142,7 @@ struct reg_cache* etb_build_reg_cache(struct etb *etb) reg_cache->num_regs = num_regs; /* set up registers */ - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { reg_list[i].name = etb_reg_list[i]; reg_list[i].size = 32; reg_list[i].dirty = 0; @@ -196,8 +192,7 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames) jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE); - for (i = 0; i < num_frames; i++) - { + for (i = 0; i < num_frames; i++) { /* ensure nR/W reamins set to read */ buf_set_u32(&temp2, 0, 1, 0); @@ -219,7 +214,7 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames) } static int etb_read_reg_w_check(struct reg *reg, - uint8_t* check_value, uint8_t* check_mask) + uint8_t *check_value, uint8_t *check_mask) { struct etb_reg *etb_reg = reg->arch_info; uint8_t reg_addr = etb_reg->addr & 0x7f; @@ -273,8 +268,8 @@ static int etb_set_reg(struct reg *reg, uint32_t value) { int retval; - if ((retval = etb_write_reg(reg, value)) != ERROR_OK) - { + retval = etb_write_reg(reg, value); + if (retval != ERROR_OK) { LOG_ERROR("BUG: error scheduling ETB register write"); return retval; } @@ -292,8 +287,8 @@ static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf) etb_set_reg(reg, buf_get_u32(buf, 0, reg->size)); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("ETB: register write failed"); return retval; } @@ -341,34 +336,28 @@ COMMAND_HANDLER(handle_etb_config_command) struct arm *arm; if (CMD_ARGC != 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } target = get_target(CMD_ARGV[0]); - if (!target) - { + if (!target) { LOG_ERROR("ETB: target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]); return ERROR_FAIL; } tap = jtag_tap_by_string(CMD_ARGV[1]); - if (tap == NULL) - { + if (tap == NULL) { command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]); return ERROR_FAIL; } - if (arm->etm) - { + if (arm->etm) { struct etb *etb = malloc(sizeof(struct etb)); arm->etm->capture_driver_priv = etb; @@ -378,9 +367,7 @@ COMMAND_HANDLER(handle_etb_config_command) etb->reg_cache = NULL; etb->ram_width = 0; etb->ram_depth = 0; - } - else - { + } else { LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured"); return ERROR_FAIL; } @@ -397,8 +384,7 @@ COMMAND_HANDLER(handle_etb_trigger_percent_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETB: current target isn't an ARM"); return ERROR_FAIL; } @@ -426,7 +412,7 @@ COMMAND_HANDLER(handle_etb_trigger_percent_command) } command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger", - etb->trigger_percent); + etb->trigger_percent); return ERROR_OK; } @@ -550,13 +536,13 @@ static int etb_read_trace(struct etm_context *etm_ctx) * i.e. don't read invalid entries */ if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1)) - { - first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32); - } + first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, + 0, + 32); else - { - num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32); - } + num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, + 0, + 32); etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame); @@ -565,9 +551,7 @@ static int etb_read_trace(struct etm_context *etm_ctx) etb_read_ram(etb, trace_data, num_frames); if (etm_ctx->trace_depth > 0) - { free(etm_ctx->trace_data); - } if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) etm_ctx->trace_depth = num_frames * 3; @@ -578,21 +562,17 @@ static int etb_read_trace(struct etm_context *etm_ctx) etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth); - for (i = 0, j = 0; i < num_frames; i++) - { - if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) - { + for (i = 0, j = 0; i < num_frames; i++) { + if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT) { /* trace word j */ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7; etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3; etm_ctx->trace_data[j].flags = 0; if ((trace_data[i] & 0x80) >> 7) - { etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[j].pipestat == STAT_TR) - { - etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7; + if (etm_ctx->trace_data[j].pipestat == STAT_TR) { + etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & + 0x7; etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE; } @@ -601,12 +581,10 @@ static int etb_read_trace(struct etm_context *etm_ctx) etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7800) >> 11; etm_ctx->trace_data[j + 1].flags = 0; if ((trace_data[i] & 0x8000) >> 15) - { etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) - { - etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7; + if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) { + etm_ctx->trace_data[j + + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7; etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE; } @@ -615,30 +593,24 @@ static int etb_read_trace(struct etm_context *etm_ctx) etm_ctx->trace_data[j + 2].packet = (trace_data[i] & 0x780000) >> 19; etm_ctx->trace_data[j + 2].flags = 0; if ((trace_data[i] & 0x800000) >> 23) - { etm_ctx->trace_data[j + 2].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR) - { - etm_ctx->trace_data[j + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7; + if (etm_ctx->trace_data[j + 2].pipestat == STAT_TR) { + etm_ctx->trace_data[j + + 2].pipestat = etm_ctx->trace_data[j + 2].packet & 0x7; etm_ctx->trace_data[j + 2].flags |= ETMV1_TRIGGER_CYCLE; } j += 3; - } - else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) - { + } else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) { /* trace word j */ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7; etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3; etm_ctx->trace_data[j].flags = 0; if ((trace_data[i] & 0x800) >> 11) - { etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[j].pipestat == STAT_TR) - { - etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7; + if (etm_ctx->trace_data[j].pipestat == STAT_TR) { + etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & + 0x7; etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE; } @@ -647,30 +619,24 @@ static int etb_read_trace(struct etm_context *etm_ctx) etm_ctx->trace_data[j + 1].packet = (trace_data[i] & 0x7f8000) >> 15; etm_ctx->trace_data[j + 1].flags = 0; if ((trace_data[i] & 0x800000) >> 23) - { etm_ctx->trace_data[j + 1].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) - { - etm_ctx->trace_data[j + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7; + if (etm_ctx->trace_data[j + 1].pipestat == STAT_TR) { + etm_ctx->trace_data[j + + 1].pipestat = etm_ctx->trace_data[j + 1].packet & 0x7; etm_ctx->trace_data[j + 1].flags |= ETMV1_TRIGGER_CYCLE; } j += 2; - } - else - { + } else { /* trace word j */ etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7; etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3; etm_ctx->trace_data[j].flags = 0; if ((trace_data[i] & 0x80000) >> 19) - { etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[j].pipestat == STAT_TR) - { - etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7; + if (etm_ctx->trace_data[j].pipestat == STAT_TR) { + etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & + 0x7; etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE; } @@ -689,10 +655,8 @@ static int etb_start_capture(struct etm_context *etm_ctx) uint32_t etb_ctrl_value = 0x1; uint32_t trigger_count; - if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) - { - if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT) - { + if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED) { + if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT) { LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port"); return ERROR_ETM_PORTMODE_NOT_SUPPORTED; } @@ -731,8 +695,7 @@ static int etb_stop_capture(struct etm_context *etm_ctx) return ERROR_OK; } -struct etm_capture_driver etb_capture_driver = -{ +struct etm_capture_driver etb_capture_driver = { .name = "etb", .commands = etb_command_handlers, .init = etb_init, diff --git a/src/target/etb.h b/src/target/etb.h index dfffb68..0ac6413 100644 --- a/src/target/etb.h +++ b/src/target/etb.h @@ -17,12 +17,12 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ETB_H #define ETB_H /* ETB registers */ -enum -{ +enum { ETB_ID = 0x00, ETB_RAM_DEPTH = 0x01, ETB_RAM_WIDTH = 0x02, @@ -34,8 +34,7 @@ enum ETB_CTRL = 0x08, }; -struct etb -{ +struct etb { struct etm_context *etm_ctx; struct jtag_tap *tap; uint32_t cur_scan_chain; @@ -49,14 +48,13 @@ struct etb unsigned trigger_percent; }; -struct etb_reg -{ +struct etb_reg { uint32_t addr; struct etb *etb; }; extern struct etm_capture_driver etb_capture_driver; -struct reg_cache* etb_build_reg_cache(struct etb *etb); +struct reg_cache *etb_build_reg_cache(struct etb *etb); #endif /* ETB_H */ diff --git a/src/target/etm.c b/src/target/etm.c index de8bb8a..8da1a5d 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -63,11 +63,11 @@ enum { }; struct etm_reg_info { - uint8_t addr; - uint8_t size; /* low-N of 32 bits */ - uint8_t mode; /* RO, WO, RW */ - uint8_t bcd_vers; /* 1.0, 2.0, etc */ - char *name; + uint8_t addr; + uint8_t size; /* low-N of 32 bits */ + uint8_t mode; /* RO, WO, RW */ + uint8_t bcd_vers; /* 1.0, 2.0, etc */ + char *name; }; /* @@ -221,7 +221,7 @@ static const struct etm_reg_info etm_outputs[] = { static int etm_get_reg(struct reg *reg); static int etm_read_reg_w_check(struct reg *reg, - uint8_t* check_value, uint8_t* check_mask); + uint8_t *check_value, uint8_t *check_mask); static int etm_register_user_commands(struct command_context *cmd_ctx); static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf); static int etm_write_reg(struct reg *reg, uint32_t value); @@ -246,15 +246,15 @@ static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id) return &cache->reg_list[i]; } - /* caller asking for nonexistent register is a bug! */ - /* REVISIT say which of the N targets was involved */ + /* caller asking for nonexistent register is a bug! + * REVISIT say which of the N targets was involved */ LOG_ERROR("ETM: register 0x%02x not available", id); return NULL; } static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info, - struct reg_cache *cache, struct etm_reg *ereg, - const struct etm_reg_info *r, unsigned nreg) + struct reg_cache *cache, struct etm_reg *ereg, + const struct etm_reg_info *r, unsigned nreg) { struct reg *reg = cache->reg_list; @@ -285,7 +285,7 @@ static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info, } struct reg_cache *etm_build_reg_cache(struct target *target, - struct arm_jtag *jtag_info, struct etm_context *etm_ctx) + struct arm_jtag *jtag_info, struct etm_context *etm_ctx) { struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = NULL; @@ -306,7 +306,7 @@ struct reg_cache *etm_build_reg_cache(struct target *target, * which other registers exist in this ETM */ etm_reg_add(0x10, jtag_info, reg_cache, arch_info, - etm_core, 1); + etm_core, 1); etm_get_reg(reg_list); etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32); @@ -322,7 +322,7 @@ struct reg_cache *etm_build_reg_cache(struct target *target, * and include any context ID comparator registers. */ etm_reg_add(0x20, jtag_info, reg_cache, arch_info, - etm_core + 1, 1); + etm_core + 1, 1); etm_get_reg(reg_list + 1); etm_ctx->id = buf_get_u32( (void *)&arch_info[1].value, 0, 32); @@ -331,41 +331,41 @@ struct reg_cache *etm_build_reg_cache(struct target *target, } else { switch (config >> 28) { - case 7: - case 5: - case 3: - bcd_vers = 0x13; - break; - case 4: - case 2: - bcd_vers = 0x12; - break; - case 1: - bcd_vers = 0x11; - break; - case 0: - bcd_vers = 0x10; - break; - default: - LOG_WARNING("Bad ETMv1 protocol %d", config >> 28); - goto fail; + case 7: + case 5: + case 3: + bcd_vers = 0x13; + break; + case 4: + case 2: + bcd_vers = 0x12; + break; + case 1: + bcd_vers = 0x11; + break; + case 0: + bcd_vers = 0x10; + break; + default: + LOG_WARNING("Bad ETMv1 protocol %d", config >> 28); + goto fail; } } etm_ctx->bcd_vers = bcd_vers; LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf); etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_basic, ARRAY_SIZE(etm_basic)); + etm_basic, ARRAY_SIZE(etm_basic)); /* address and data comparators; counters; outputs */ etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_addr_comp, 4 * (0x0f & (config >> 0))); + etm_addr_comp, 4 * (0x0f & (config >> 0))); etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_data_comp, 2 * (0x0f & (config >> 4))); + etm_data_comp, 2 * (0x0f & (config >> 4))); etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_counters, 4 * (0x07 & (config >> 13))); + etm_counters, 4 * (0x07 & (config >> 13))); etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_outputs, (0x07 & (config >> 20))); + etm_outputs, (0x07 & (config >> 20))); /* FIFOFULL presence is optional * REVISIT for ETMv1.2 and later, don't bother adding this @@ -373,24 +373,22 @@ struct reg_cache *etm_build_reg_cache(struct target *target, */ if (config & (1 << 23)) etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_fifofull, ARRAY_SIZE(etm_fifofull)); + etm_fifofull, ARRAY_SIZE(etm_fifofull)); /* sequencer is optional (for state-dependant triggering) */ if (config & (1 << 16)) etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info, - etm_sequencer, ARRAY_SIZE(etm_sequencer)); + etm_sequencer, ARRAY_SIZE(etm_sequencer)); /* REVISIT could realloc and likely save half the memory * in the two chunks we allocated... */ /* the ETM might have an ETB connected */ - if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) - { + if (strcmp(etm_ctx->capture_driver->name, "etb") == 0) { struct etb *etb = etm_ctx->capture_driver_priv; - if (!etb) - { + if (!etb) { LOG_ERROR("etb selected as etm capture driver, but no ETB configured"); goto fail; } @@ -443,10 +441,10 @@ int etm_setup(struct target *target) * for older modules clocking (13) */ etm_ctrl_value = (etm_ctrl_value - & ~ETM_PORT_WIDTH_MASK - & ~ETM_PORT_MODE_MASK - & ~ETM_CTRL_DBGRQ - & ~ETM_PORT_CLOCK_MASK) + & ~ETM_PORT_WIDTH_MASK + & ~ETM_PORT_MODE_MASK + & ~ETM_CTRL_DBGRQ + & ~ETM_PORT_CLOCK_MASK) | etm_ctx->control; buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value); @@ -454,15 +452,16 @@ int etm_setup(struct target *target) etm_ctx->control = etm_ctrl_value; - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; /* REVISIT for ETMv3.0 and later, read ETM_sys_config to * verify that those width and mode settings are OK ... */ - if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK) - { + retval = etm_ctx->capture_driver->init(etm_ctx); + if (retval != ERROR_OK) { LOG_ERROR("ETM capture driver initialization failed"); return retval; } @@ -473,14 +472,14 @@ static int etm_get_reg(struct reg *reg) { int retval; - if ((retval = etm_read_reg(reg)) != ERROR_OK) - { + retval = etm_read_reg(reg); + if (retval != ERROR_OK) { LOG_ERROR("BUG: error scheduling etm register read"); return retval; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } @@ -489,7 +488,7 @@ static int etm_get_reg(struct reg *reg) } static int etm_read_reg_w_check(struct reg *reg, - uint8_t* check_value, uint8_t* check_mask) + uint8_t *check_value, uint8_t *check_mask) { struct etm_reg *etm_reg = reg->arch_info; const struct etm_reg_info *r = etm_reg->reg_info; @@ -507,7 +506,10 @@ static int etm_read_reg_w_check(struct reg *reg, retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE); if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(etm_reg->jtag_info, + etm_reg->jtag_info->intest_instr, + NULL, + TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -546,10 +548,8 @@ static int etm_read_reg_w_check(struct reg *reg, static int etm_set_reg(struct reg *reg, uint32_t value) { - int retval; - - if ((retval = etm_write_reg(reg, value)) != ERROR_OK) - { + int retval = etm_write_reg(reg, value); + if (retval != ERROR_OK) { LOG_ERROR("BUG: error scheduling etm register write"); return retval; } @@ -567,8 +567,8 @@ static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf) etm_set_reg(reg, buf_get_u32(buf, 0, reg->size)); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("register write failed"); return retval; } @@ -593,7 +593,10 @@ static int etm_write_reg(struct reg *reg, uint32_t value) retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE); if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(etm_reg->jtag_info, + etm_reg->jtag_info->intest_instr, + NULL, + TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -623,8 +626,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value) /* ETM trace analysis functionality */ -static struct etm_capture_driver *etm_capture_drivers[] = -{ +static struct etm_capture_driver *etm_capture_drivers[] = { &etb_capture_driver, &etm_dummy_capture_driver, #if BUILD_OOCD_TRACE == 1 @@ -645,55 +647,48 @@ static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction return ERROR_TRACE_IMAGE_UNAVAILABLE; /* search for the section the current instruction belongs to */ - for (i = 0; i < ctx->image->num_sections; i++) - { + for (i = 0; i < ctx->image->num_sections; i++) { if ((ctx->image->sections[i].base_address <= ctx->current_pc) && - (ctx->image->sections[i].base_address + ctx->image->sections[i].size > ctx->current_pc)) - { + (ctx->image->sections[i].base_address + ctx->image->sections[i].size > + ctx->current_pc)) { section = i; break; } } - if (section == -1) - { + if (section == -1) { /* current instruction couldn't be found in the image */ return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } - if (ctx->core_state == ARM_STATE_ARM) - { + if (ctx->core_state == ARM_STATE_ARM) { uint8_t buf[4]; - if ((retval = image_read_section(ctx->image, section, - ctx->current_pc - ctx->image->sections[section].base_address, - 4, buf, &size_read)) != ERROR_OK) - { + retval = image_read_section(ctx->image, section, + ctx->current_pc - + ctx->image->sections[section].base_address, + 4, buf, &size_read); + if (retval != ERROR_OK) { LOG_ERROR("error while reading instruction"); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u32(ctx->target, buf); arm_evaluate_opcode(opcode, ctx->current_pc, instruction); - } - else if (ctx->core_state == ARM_STATE_THUMB) - { + } else if (ctx->core_state == ARM_STATE_THUMB) { uint8_t buf[2]; - if ((retval = image_read_section(ctx->image, section, - ctx->current_pc - ctx->image->sections[section].base_address, - 2, buf, &size_read)) != ERROR_OK) - { + retval = image_read_section(ctx->image, section, + ctx->current_pc - + ctx->image->sections[section].base_address, + 2, buf, &size_read); + if (retval != ERROR_OK) { LOG_ERROR("error while reading instruction"); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u16(ctx->target, buf); thumb_evaluate_opcode(opcode, ctx->current_pc, instruction); - } - else if (ctx->core_state == ARM_STATE_JAZELLE) - { + } else if (ctx->core_state == ARM_STATE_JAZELLE) { LOG_ERROR("BUG: tracing of jazelle code not supported"); return ERROR_FAIL; - } - else - { + } else { LOG_ERROR("BUG: unknown core state encountered"); return ERROR_FAIL; } @@ -703,17 +698,14 @@ static int etm_read_instruction(struct etm_context *ctx, struct arm_instruction static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo) { - while (ctx->data_index < ctx->trace_depth) - { + while (ctx->data_index < ctx->trace_depth) { /* if the caller specified an address packet offset, skip until the * we reach the n-th cycle marked with tracesync */ - if (apo > 0) - { + if (apo > 0) { if (ctx->trace_data[ctx->data_index].flags & ETMV1_TRACESYNC_CYCLE) apo--; - if (apo > 0) - { + if (apo > 0) { ctx->data_index++; ctx->data_half = 0; } @@ -723,35 +715,26 @@ static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo) /* no tracedata output during a TD cycle * or in a trigger cycle */ if ((ctx->trace_data[ctx->data_index].pipestat == STAT_TD) - || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) - { + || (ctx->trace_data[ctx->data_index].flags & ETMV1_TRIGGER_CYCLE)) { ctx->data_index++; ctx->data_half = 0; continue; } /* FIXME there are more port widths than these... */ - if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) - { - if (ctx->data_half == 0) - { + if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT) { + if (ctx->data_half == 0) { *packet = ctx->trace_data[ctx->data_index].packet & 0xff; ctx->data_half = 1; - } - else - { + } else { *packet = (ctx->trace_data[ctx->data_index].packet & 0xff00) >> 8; ctx->data_half = 0; ctx->data_index++; } - } - else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) - { + } else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT) { *packet = ctx->trace_data[ctx->data_index].packet & 0xff; ctx->data_index++; - } - else - { + } else { /* on a 4-bit port, a packet will be output during two consecutive cycles */ if (ctx->data_index > (ctx->trace_depth - 2)) return -1; @@ -794,15 +777,15 @@ static int etmv1_branch_address(struct etm_context *ctx) /* count number of tracesync cycles between current pipe_index and data_index * i.e. the number of tracesyncs that data_index already passed by * to subtract them from the APO */ - for (i = ctx->pipe_index; i < ctx->data_index; i++) - { + for (i = ctx->pipe_index; i < ctx->data_index; i++) { if (ctx->trace_data[ctx->pipe_index + 1].pipestat & ETMV1_TRACESYNC_CYCLE) apo--; } /* extract up to four 7-bit packets */ do { - if ((retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0)) != 0) + retval = etmv1_next_packet(ctx, &packet, (shift == 0) ? apo + 1 : 0); + if (retval != 0) return -1; ctx->last_branch &= ~(0x7f << shift); ctx->last_branch |= (packet & 0x7f) << shift; @@ -810,41 +793,30 @@ static int etmv1_branch_address(struct etm_context *ctx) } while ((packet & 0x80) && (shift < 28)); /* one last packet holding 4 bits of the address, plus the branch reason code */ - if ((shift == 28) && (packet & 0x80)) - { - if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0) + if ((shift == 28) && (packet & 0x80)) { + retval = etmv1_next_packet(ctx, &packet, 0); + if (retval != 0) return -1; ctx->last_branch &= 0x0fffffff; ctx->last_branch |= (packet & 0x0f) << 28; ctx->last_branch_reason = (packet & 0x70) >> 4; shift += 4; - } - else - { + } else ctx->last_branch_reason = 0; - } if (shift == 32) - { ctx->pc_ok = 1; - } /* if a full address was output, we might have branched into Jazelle state */ if ((shift == 32) && (packet & 0x80)) - { ctx->core_state = ARM_STATE_JAZELLE; - } - else - { + else { /* if we didn't branch into Jazelle state, the current processor state is * encoded in bit 0 of the branch target address */ - if (ctx->last_branch & 0x1) - { + if (ctx->last_branch & 0x1) { ctx->core_state = ARM_STATE_THUMB; ctx->last_branch &= ~0x1; - } - else - { + } else { ctx->core_state = ARM_STATE_ARM; ctx->last_branch &= ~0x3; } @@ -859,18 +831,16 @@ static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data) uint8_t buf[4]; int retval; - for (j = 0; j < size; j++) - { - if ((retval = etmv1_next_packet(ctx, &buf[j], 0)) != 0) + for (j = 0; j < size; j++) { + retval = etmv1_next_packet(ctx, &buf[j], 0); + if (retval != 0) return -1; } - if (size == 8) - { + if (size == 8) { LOG_ERROR("TODO: add support for 64-bit values"); return -1; - } - else if (size == 4) + } else if (size == 4) *data = target_buffer_get_u32(ctx->target, buf); else if (size == 2) *data = target_buffer_get_u16(ctx->target, buf); @@ -905,8 +875,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * ctx->pc_ok = 0; ctx->ptr_ok = 0; - while (ctx->pipe_index < ctx->trace_depth) - { + while (ctx->pipe_index < ctx->trace_depth) { uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat; uint32_t next_pc = ctx->current_pc; uint32_t old_data_index = ctx->data_index; @@ -917,17 +886,14 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * int current_pc_ok = ctx->pc_ok; if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE) - { command_print(cmd_ctx, "--- trigger ---"); - } /* instructions execute in IE/D or BE/D cycles */ if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) ctx->last_instruction = ctx->pipe_index; /* if we don't have a valid pc skip until we reach an indirect branch */ - if ((!ctx->pc_ok) && (pipestat != STAT_BE)) - { + if ((!ctx->pc_ok) && (pipestat != STAT_BE)) { ctx->pipe_index++; continue; } @@ -936,8 +902,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * * - the branch reason code could indicate a trace discontinuity * - a branch to the exception vectors indicates an exception */ - if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) - { + if ((pipestat == STAT_BE) || (pipestat == STAT_BD)) { /* backup current data index, to be able to consume the branch address * before examining data address and values */ @@ -946,8 +911,8 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * ctx->last_instruction = ctx->pipe_index; - if ((retval = etmv1_branch_address(ctx)) != 0) - { + retval = etmv1_branch_address(ctx); + if (retval != 0) { /* negative return value from etmv1_branch_address means we ran out of packets, * quit analysing the trace */ if (retval < 0) @@ -956,7 +921,8 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * /* a positive return values means the current branch was abandoned, * and a new branch was encountered in cycle ctx->pipe_index + retval; */ - LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain"); + LOG_WARNING( + "abandoned branch encountered, correctnes of analysis uncertain"); ctx->pipe_index += retval; continue; } @@ -964,25 +930,30 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * /* skip over APO cycles */ ctx->pipe_index += 2; - switch (ctx->last_branch_reason) - { + switch (ctx->last_branch_reason) { case 0x0: /* normal PC change */ next_pc = ctx->last_branch; break; case 0x1: /* tracing enabled */ - command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch); + command_print(cmd_ctx, + "--- tracing enabled at 0x%8.8" PRIx32 " ---", + ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; break; case 0x2: /* trace restarted after FIFO overflow */ - command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch); + command_print(cmd_ctx, + "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", + ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; break; case 0x3: /* exit from debug state */ - command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch); + command_print(cmd_ctx, + "--- exit from debug state at 0x%8.8" PRIx32 " ---", + ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; @@ -992,16 +963,19 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * /* if we had no valid PC prior to this synchronization point, * we have to move on with the next trace cycle */ - if (!current_pc_ok) - { - command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc); + if (!current_pc_ok) { + command_print(cmd_ctx, + "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", + next_pc); ctx->current_pc = next_pc; ctx->pipe_index++; continue; } break; default: /* reserved */ - LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason); + LOG_ERROR( + "BUG: branch reason code 0x%" PRIx32 " is reserved", + ctx->last_branch_reason); return ERROR_FAIL; } @@ -1014,15 +988,14 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * /* indirect branch to the exception vector means an exception occured */ if ((ctx->last_branch <= 0x20) - || ((ctx->last_branch >= 0xffff0000) && (ctx->last_branch <= 0xffff0020))) - { + || ((ctx->last_branch >= 0xffff0000) && + (ctx->last_branch <= 0xffff0020))) { if ((ctx->last_branch & 0xff) == 0x10) - { command_print(cmd_ctx, "data abort"); - } - else - { - command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch); + else { + command_print(cmd_ctx, + "exception vector 0x%2.2" PRIx32 "", + ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; @@ -1034,17 +1007,13 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * * retrieve it from the image for displaying */ if (ctx->pc_ok && (pipestat != STAT_WT) && (pipestat != STAT_TD) && !(((pipestat == STAT_BE) || (pipestat == STAT_BD)) && - ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) - { - if ((retval = etm_read_instruction(ctx, &instruction)) != ERROR_OK) - { + ((ctx->last_branch_reason != 0x0) && (ctx->last_branch_reason != 0x4)))) { + retval = etm_read_instruction(ctx, &instruction); + if (retval != ERROR_OK) { /* can't continue tracing with no image available */ if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE) - { return retval; - } - else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) - { + else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE) { /* TODO: handle incomplete images * for now we just quit the analsysis*/ return retval; @@ -1054,26 +1023,24 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * cycles = old_index - last_instruction; } - if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) - { + if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) { uint32_t new_data_index = ctx->data_index; uint32_t new_data_half = ctx->data_half; /* in case of a branch with data, the branch target address was consumed before * we temporarily go back to the saved data index */ - if (pipestat == STAT_BD) - { + if (pipestat == STAT_BD) { ctx->data_index = old_data_index; ctx->data_half = old_data_half; } - if (ctx->control & ETM_CTRL_TRACE_ADDR) - { + if (ctx->control & ETM_CTRL_TRACE_ADDR) { uint8_t packet; int shift = 0; do { - if ((retval = etmv1_next_packet(ctx, &packet, 0)) != 0) + retval = etmv1_next_packet(ctx, &packet, 0); + if (retval != 0) return ERROR_ETM_ANALYSIS_FAILED; ctx->last_ptr &= ~(0x7f << shift); ctx->last_ptr |= (packet & 0x7f) << shift; @@ -1084,75 +1051,64 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * ctx->ptr_ok = 1; if (ctx->ptr_ok) - { - command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr); - } + command_print(cmd_ctx, + "address: 0x%8.8" PRIx32 "", + ctx->last_ptr); } - if (ctx->control & ETM_CTRL_TRACE_DATA) - { - if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM)) - { + if (ctx->control & ETM_CTRL_TRACE_DATA) { + if ((instruction.type == ARM_LDM) || + (instruction.type == ARM_STM)) { int i; - for (i = 0; i < 16; i++) - { - if (instruction.info.load_store_multiple.register_list & (1 << i)) - { + for (i = 0; i < 16; i++) { + if (instruction.info.load_store_multiple. + register_list & (1 << i)) { uint32_t data; if (etmv1_data(ctx, 4, &data) != 0) return ERROR_ETM_ANALYSIS_FAILED; - command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data); + command_print(cmd_ctx, + "data: 0x%8.8" PRIx32 "", + data); } } - } - else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH)) - { + } else if ((instruction.type >= ARM_LDR) && + (instruction.type <= ARM_STRH)) { uint32_t data; - if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0) + if (etmv1_data(ctx, arm_access_size(&instruction), + &data) != 0) return ERROR_ETM_ANALYSIS_FAILED; command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data); } } /* restore data index after consuming BD address and data */ - if (pipestat == STAT_BD) - { + if (pipestat == STAT_BD) { ctx->data_index = new_data_index; ctx->data_half = new_data_half; } } /* adjust PC */ - if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) - { + if ((pipestat == STAT_IE) || (pipestat == STAT_ID)) { if (((instruction.type == ARM_B) || - (instruction.type == ARM_BL) || - (instruction.type == ARM_BLX)) && - (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)) - { + (instruction.type == ARM_BL) || + (instruction.type == ARM_BLX)) && + (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)) next_pc = instruction.info.b_bl_bx_blx.target_address; - } else - { next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2; - } - } - else if (pipestat == STAT_IN) - { + } else if (pipestat == STAT_IN) next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2; - } - if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) - { + if ((pipestat != STAT_TD) && (pipestat != STAT_WT)) { char cycles_text[32] = ""; /* if the trace was captured with cycle accurate tracing enabled, * output the number of cycles since the last executed instruction */ - if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) - { + if (ctx->control & ETM_CTRL_CYCLE_ACCURATE) { snprintf(cycles_text, 32, " (%i %s)", - (int)cycles, + (int)cycles, (cycles == 1) ? "cycle" : "cycles"); } @@ -1166,8 +1122,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * /* packets for an instruction don't start on or before the preceding * functional pipestat (i.e. other than WT or TD) */ - if (ctx->data_index <= ctx->pipe_index) - { + if (ctx->data_index <= ctx->pipe_index) { ctx->data_index = ctx->pipe_index + 1; ctx->data_half = 0; } @@ -1180,7 +1135,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context * } static COMMAND_HELPER(handle_etm_tracemode_command_update, - uint32_t *mode) + uint32_t *mode) { uint32_t tracemode; @@ -1193,31 +1148,29 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update, tracemode = ETM_CTRL_TRACE_ADDR; else if (strcmp(CMD_ARGV[0], "all") == 0) tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR; - else - { + else { command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]); return ERROR_COMMAND_SYNTAX_ERROR; } uint8_t context_id; COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id); - switch (context_id) - { - case 0: - tracemode |= ETM_CTRL_CONTEXTID_NONE; - break; - case 8: - tracemode |= ETM_CTRL_CONTEXTID_8; - break; - case 16: - tracemode |= ETM_CTRL_CONTEXTID_16; - break; - case 32: - tracemode |= ETM_CTRL_CONTEXTID_32; - break; - default: - command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]); - return ERROR_COMMAND_SYNTAX_ERROR; + switch (context_id) { + case 0: + tracemode |= ETM_CTRL_CONTEXTID_NONE; + break; + case 8: + tracemode |= ETM_CTRL_CONTEXTID_8; + break; + case 16: + tracemode |= ETM_CTRL_CONTEXTID_16; + break; + case 32: + tracemode |= ETM_CTRL_CONTEXTID_32; + break; + default: + command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]); + return ERROR_COMMAND_SYNTAX_ERROR; } bool etmv1_cycle_accurate; @@ -1259,16 +1212,15 @@ COMMAND_HANDLER(handle_etm_tracemode_command) uint32_t tracemode = etm->control; - switch (CMD_ARGC) - { - case 0: - break; - case 4: - CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, + switch (CMD_ARGC) { + case 0: + break; + case 4: + CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, &tracemode); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } /** @@ -1278,8 +1230,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command) command_print(CMD_CTX, "current tracemode configuration:"); - switch (tracemode & ETM_CTRL_TRACE_MASK) - { + switch (tracemode & ETM_CTRL_TRACE_MASK) { default: command_print(CMD_CTX, "data tracing: none"); break; @@ -1294,8 +1245,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command) break; } - switch (tracemode & ETM_CTRL_CONTEXTID_MASK) - { + switch (tracemode & ETM_CTRL_CONTEXTID_MASK) { case ETM_CTRL_CONTEXTID_NONE: command_print(CMD_CTX, "contextid tracing: none"); break; @@ -1311,33 +1261,24 @@ COMMAND_HANDLER(handle_etm_tracemode_command) } if (tracemode & ETM_CTRL_CYCLE_ACCURATE) - { command_print(CMD_CTX, "cycle-accurate tracing enabled"); - } else - { command_print(CMD_CTX, "cycle-accurate tracing disabled"); - } if (tracemode & ETM_CTRL_BRANCH_OUTPUT) - { command_print(CMD_CTX, "full branch address output enabled"); - } else - { command_print(CMD_CTX, "full branch address output disabled"); - } #define TRACEMODE_MASK ( \ - ETM_CTRL_CONTEXTID_MASK \ - | ETM_CTRL_BRANCH_OUTPUT \ - | ETM_CTRL_CYCLE_ACCURATE \ - | ETM_CTRL_TRACE_MASK \ - ) + ETM_CTRL_CONTEXTID_MASK \ + | ETM_CTRL_BRANCH_OUTPUT \ + | ETM_CTRL_CYCLE_ACCURATE \ + | ETM_CTRL_TRACE_MASK \ + ) /* only update ETM_CTRL register if tracemode changed */ - if ((etm->control & TRACEMODE_MASK) != tracemode) - { + if ((etm->control & TRACEMODE_MASK) != tracemode) { struct reg *etm_ctrl_reg; etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL); @@ -1352,8 +1293,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command) /* invalidate old trace data */ etm->capture_status = TRACE_IDLE; - if (etm->trace_depth > 0) - { + if (etm->trace_depth > 0) { free(etm->trace_data); etm->trace_data = NULL; } @@ -1377,8 +1317,7 @@ COMMAND_HANDLER(handle_etm_config_command) return ERROR_COMMAND_SYNTAX_ERROR; target = get_target(CMD_ARGV[0]); - if (!target) - { + if (!target) { LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } @@ -1386,8 +1325,8 @@ COMMAND_HANDLER(handle_etm_config_command) arm = target_to_arm(target); if (!is_arm(arm)) { command_print(CMD_CTX, "target '%s' is '%s'; not an ARM", - target_name(target), - target_type_name(target)); + target_name(target), + target_type_name(target)); return ERROR_FAIL; } @@ -1405,8 +1344,7 @@ COMMAND_HANDLER(handle_etm_config_command) */ uint8_t port_width; COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width); - switch (port_width) - { + switch (port_width) { /* before ETMv3.0 */ case 4: portmode |= ETM_PORT_4BIT; @@ -1443,34 +1381,26 @@ COMMAND_HANDLER(handle_etm_config_command) } if (strcmp("normal", CMD_ARGV[2]) == 0) - { portmode |= ETM_PORT_NORMAL; - } else if (strcmp("multiplexed", CMD_ARGV[2]) == 0) - { portmode |= ETM_PORT_MUXED; - } else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0) - { portmode |= ETM_PORT_DEMUXED; - } - else - { - command_print(CMD_CTX, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", CMD_ARGV[2]); + else { + command_print(CMD_CTX, + "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", + CMD_ARGV[2]); return ERROR_FAIL; } if (strcmp("half", CMD_ARGV[3]) == 0) - { portmode |= ETM_PORT_HALF_CLOCK; - } else if (strcmp("full", CMD_ARGV[3]) == 0) - { portmode |= ETM_PORT_FULL_CLOCK; - } - else - { - command_print(CMD_CTX, "unsupported ETM port clocking '%s', must be 'full' or 'half'", CMD_ARGV[3]); + else { + command_print(CMD_CTX, + "unsupported ETM port clocking '%s', must be 'full' or 'half'", + CMD_ARGV[3]); return ERROR_FAIL; } @@ -1480,14 +1410,11 @@ COMMAND_HANDLER(handle_etm_config_command) return ERROR_FAIL; } - for (i = 0; etm_capture_drivers[i]; i++) - { - if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) - { + for (i = 0; etm_capture_drivers[i]; i++) { + if (strcmp(CMD_ARGV[4], etm_capture_drivers[i]->name) == 0) { int retval = register_commands(CMD_CTX, NULL, etm_capture_drivers[i]->commands); - if (ERROR_OK != retval) - { + if (ERROR_OK != retval) { free(etm_ctx); return retval; } @@ -1498,8 +1425,7 @@ COMMAND_HANDLER(handle_etm_config_command) } } - if (!etm_capture_drivers[i]) - { + if (!etm_capture_drivers[i]) { /* no supported capture driver found, don't register an ETM */ free(etm_ctx); LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV[4]); @@ -1527,48 +1453,46 @@ COMMAND_HANDLER(handle_etm_info_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm = arm->etm; - if (!etm) - { + if (!etm) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } command_print(CMD_CTX, "ETM v%d.%d", - etm->bcd_vers >> 4, etm->bcd_vers & 0xf); + etm->bcd_vers >> 4, etm->bcd_vers & 0xf); command_print(CMD_CTX, "pairs of address comparators: %i", - (int) (etm->config >> 0) & 0x0f); + (int) (etm->config >> 0) & 0x0f); command_print(CMD_CTX, "data comparators: %i", - (int) (etm->config >> 4) & 0x0f); + (int) (etm->config >> 4) & 0x0f); command_print(CMD_CTX, "memory map decoders: %i", - (int) (etm->config >> 8) & 0x1f); + (int) (etm->config >> 8) & 0x1f); command_print(CMD_CTX, "number of counters: %i", - (int) (etm->config >> 13) & 0x07); + (int) (etm->config >> 13) & 0x07); command_print(CMD_CTX, "sequencer %spresent", - (int) (etm->config & (1 << 16)) ? "" : "not "); + (int) (etm->config & (1 << 16)) ? "" : "not "); command_print(CMD_CTX, "number of ext. inputs: %i", - (int) (etm->config >> 17) & 0x07); + (int) (etm->config >> 17) & 0x07); command_print(CMD_CTX, "number of ext. outputs: %i", - (int) (etm->config >> 20) & 0x07); + (int) (etm->config >> 20) & 0x07); command_print(CMD_CTX, "FIFO full %spresent", - (int) (etm->config & (1 << 23)) ? "" : "not "); + (int) (etm->config & (1 << 23)) ? "" : "not "); if (etm->bcd_vers < 0x20) command_print(CMD_CTX, "protocol version: %i", - (int) (etm->config >> 28) & 0x07); + (int) (etm->config >> 28) & 0x07); else { command_print(CMD_CTX, - "coprocessor and memory access %ssupported", - (etm->config & (1 << 26)) ? "" : "not "); + "coprocessor and memory access %ssupported", + (etm->config & (1 << 26)) ? "" : "not "); command_print(CMD_CTX, "trace start/stop %spresent", - (etm->config & (1 << 26)) ? "" : "not "); + (etm->config & (1 << 26)) ? "" : "not "); command_print(CMD_CTX, "number of context comparators: %i", - (int) (etm->config >> 24) & 0x03); + (int) (etm->config >> 24) & 0x03); } /* SYS_CONFIG isn't present before ETMv1.2 */ @@ -1584,8 +1508,7 @@ COMMAND_HANDLER(handle_etm_info_command) max_port_size = config & 0x7; if (etm->bcd_vers >= 0x30) max_port_size |= (config >> 6) & 0x08; - switch (max_port_size) - { + switch (max_port_size) { /* before ETMv3.0 */ case 0: max_port_size = 4; @@ -1623,27 +1546,27 @@ COMMAND_HANDLER(handle_etm_info_command) if (etm->bcd_vers < 0x30) { command_print(CMD_CTX, "half-rate clocking %ssupported", - (config & (1 << 3)) ? "" : "not "); + (config & (1 << 3)) ? "" : "not "); command_print(CMD_CTX, "full-rate clocking %ssupported", - (config & (1 << 4)) ? "" : "not "); + (config & (1 << 4)) ? "" : "not "); command_print(CMD_CTX, "normal trace format %ssupported", - (config & (1 << 5)) ? "" : "not "); + (config & (1 << 5)) ? "" : "not "); command_print(CMD_CTX, "multiplex trace format %ssupported", - (config & (1 << 6)) ? "" : "not "); + (config & (1 << 6)) ? "" : "not "); command_print(CMD_CTX, "demultiplex trace format %ssupported", - (config & (1 << 7)) ? "" : "not "); + (config & (1 << 7)) ? "" : "not "); } else { /* REVISIT show which size and format are selected ... */ command_print(CMD_CTX, "current port size %ssupported", - (config & (1 << 10)) ? "" : "not "); + (config & (1 << 10)) ? "" : "not "); command_print(CMD_CTX, "current trace format %ssupported", - (config & (1 << 11)) ? "" : "not "); + (config & (1 << 11)) ? "" : "not "); } if (etm->bcd_vers >= 0x21) command_print(CMD_CTX, "fetch comparisons %ssupported", - (config & (1 << 17)) ? "not " : ""); + (config & (1 << 17)) ? "not " : ""); command_print(CMD_CTX, "FIFO full %ssupported", - (config & (1 << 8)) ? "" : "not "); + (config & (1 << 8)) ? "" : "not "); return ERROR_OK; } @@ -1657,15 +1580,13 @@ COMMAND_HANDLER(handle_etm_status_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm = arm->etm; - if (!etm) - { + if (!etm) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } @@ -1683,26 +1604,23 @@ COMMAND_HANDLER(handle_etm_status_command) command_print(CMD_CTX, "etm: %s%s%s%s", /* bit(1) == progbit */ (etm->bcd_vers >= 0x12) - ? ((s & (1 << 1)) - ? "disabled" : "enabled") - : "?", + ? ((s & (1 << 1)) + ? "disabled" : "enabled") + : "?", ((s & (1 << 3)) && etm->bcd_vers >= 0x31) - ? " triggered" : "", + ? " triggered" : "", ((s & (1 << 2)) && etm->bcd_vers >= 0x12) - ? " start/stop" : "", + ? " start/stop" : "", ((s & (1 << 0)) && etm->bcd_vers >= 0x11) - ? " untraced-overflow" : ""); - } /* else ignore and try showing trace port status */ + ? " untraced-overflow" : ""); + } /* else ignore and try showing trace port status */ } /* Trace Port Driver status */ trace_status = etm->capture_driver->status(etm); if (trace_status == TRACE_IDLE) - { command_print(CMD_CTX, "%s: idle", etm->capture_driver->name); - } - else - { + else { static char *completed = " completed"; static char *running = " is running"; static char *overflowed = ", overflowed"; @@ -1714,10 +1632,9 @@ COMMAND_HANDLER(handle_etm_status_command) (trace_status & TRACE_OVERFLOWED) ? overflowed : "", (trace_status & TRACE_TRIGGERED) ? triggered : ""); - if (etm->trace_depth > 0) - { + if (etm->trace_depth > 0) { command_print(CMD_CTX, "%i frames of trace data read", - (int)(etm->trace_depth)); + (int)(etm->trace_depth)); } } @@ -1731,27 +1648,22 @@ COMMAND_HANDLER(handle_etm_image_command) struct etm_context *etm_ctx; if (CMD_ARGC < 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm_ctx = arm->etm; - if (!etm_ctx) - { + if (!etm_ctx) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } - if (etm_ctx->image) - { + if (etm_ctx->image) { image_close(etm_ctx->image); free(etm_ctx->image); command_print(CMD_CTX, "previously loaded image found and closed"); @@ -1762,18 +1674,14 @@ COMMAND_HANDLER(handle_etm_image_command) etm_ctx->image->start_address_set = 0; /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */ - if (CMD_ARGC >= 2) - { + if (CMD_ARGC >= 2) { etm_ctx->image->base_address_set = 1; COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], etm_ctx->image->base_address); - } - else - { + } else etm_ctx->image->base_address_set = 0; - } - if (image_open(etm_ctx->image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) - { + if (image_open(etm_ctx->image, CMD_ARGV[0], + (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) { free(etm_ctx->image); etm_ctx->image = NULL; return ERROR_FAIL; @@ -1791,33 +1699,27 @@ COMMAND_HANDLER(handle_etm_dump_command) uint32_t i; if (CMD_ARGC != 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm_ctx = arm->etm; - if (!etm_ctx) - { + if (!etm_ctx) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } - if (etm_ctx->capture_driver->status == TRACE_IDLE) - { + if (etm_ctx->capture_driver->status == TRACE_IDLE) { command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured"); return ERROR_OK; } - if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) - { + if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) { /* TODO: if on-the-fly capture is to be supported, this needs to be changed */ command_print(CMD_CTX, "trace capture not completed"); return ERROR_FAIL; @@ -1828,16 +1730,13 @@ COMMAND_HANDLER(handle_etm_dump_command) etm_ctx->capture_driver->read_trace(etm_ctx); if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) - { return ERROR_FAIL; - } fileio_write_u32(&file, etm_ctx->capture_status); fileio_write_u32(&file, etm_ctx->control); fileio_write_u32(&file, etm_ctx->trace_depth); - for (i = 0; i < etm_ctx->trace_depth; i++) - { + for (i = 0; i < etm_ctx->trace_depth; i++) { fileio_write_u32(&file, etm_ctx->trace_data[i].pipestat); fileio_write_u32(&file, etm_ctx->trace_data[i].packet); fileio_write_u32(&file, etm_ctx->trace_data[i].flags); @@ -1857,73 +1756,61 @@ COMMAND_HANDLER(handle_etm_load_command) uint32_t i; if (CMD_ARGC != 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm_ctx = arm->etm; - if (!etm_ctx) - { + if (!etm_ctx) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } - if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) - { + if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) { command_print(CMD_CTX, "trace capture running, stop first"); return ERROR_FAIL; } if (fileio_open(&file, CMD_ARGV[0], FILEIO_READ, FILEIO_BINARY) != ERROR_OK) - { return ERROR_FAIL; - } int filesize; int retval = fileio_size(&file, &filesize); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { fileio_close(&file); return retval; } - if (filesize % 4) - { + if (filesize % 4) { command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data"); fileio_close(&file); return ERROR_FAIL; } - if (etm_ctx->trace_depth > 0) - { + if (etm_ctx->trace_depth > 0) { free(etm_ctx->trace_data); etm_ctx->trace_data = NULL; } { - uint32_t tmp; - fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp; - fileio_read_u32(&file, &tmp); etm_ctx->control = tmp; - fileio_read_u32(&file, &etm_ctx->trace_depth); + uint32_t tmp; + fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp; + fileio_read_u32(&file, &tmp); etm_ctx->control = tmp; + fileio_read_u32(&file, &etm_ctx->trace_depth); } etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth); - if (etm_ctx->trace_data == NULL) - { + if (etm_ctx->trace_data == NULL) { command_print(CMD_CTX, "not enough memory to perform operation"); fileio_close(&file); return ERROR_FAIL; } - for (i = 0; i < etm_ctx->trace_depth; i++) - { + for (i = 0; i < etm_ctx->trace_depth; i++) { uint32_t pipestat, packet, flags; fileio_read_u32(&file, &pipestat); fileio_read_u32(&file, &packet); @@ -1947,23 +1834,20 @@ COMMAND_HANDLER(handle_etm_start_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm_ctx = arm->etm; - if (!etm_ctx) - { + if (!etm_ctx) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } /* invalidate old tracing data */ etm_ctx->capture_status = TRACE_IDLE; - if (etm_ctx->trace_depth > 0) - { + if (etm_ctx->trace_depth > 0) { free(etm_ctx->trace_data); etm_ctx->trace_data = NULL; } @@ -1995,15 +1879,13 @@ COMMAND_HANDLER(handle_etm_stop_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm_ctx = arm->etm; - if (!etm_ctx) - { + if (!etm_ctx) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } @@ -2033,18 +1915,16 @@ COMMAND_HANDLER(handle_etm_trigger_debug_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: %s isn't an ARM", - target_name(target)); + target_name(target)); return ERROR_FAIL; } etm = arm->etm; - if (!etm) - { + if (!etm) { command_print(CMD_CTX, "ETM: no ETM configured for %s", - target_name(target)); + target_name(target)); return ERROR_FAIL; } @@ -2069,9 +1949,9 @@ COMMAND_HANDLER(handle_etm_trigger_debug_command) } command_print(CMD_CTX, "ETM: %s debug halt", - (etm->control & ETM_CTRL_DBGRQ) - ? "triggers" - : "does not trigger"); + (etm->control & ETM_CTRL_DBGRQ) + ? "triggers" + : "does not trigger"); return ERROR_OK; } @@ -2084,29 +1964,28 @@ COMMAND_HANDLER(handle_etm_analyze_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "ETM: current target isn't an ARM"); return ERROR_FAIL; } etm_ctx = arm->etm; - if (!etm_ctx) - { + if (!etm_ctx) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } - if ((retval = etmv1_analyze_trace(etm_ctx, CMD_CTX)) != ERROR_OK) - { + retval = etmv1_analyze_trace(etm_ctx, CMD_CTX); + if (retval != ERROR_OK) { /* FIX! error should be reported inside etmv1_analyze_trace() */ - switch (retval) - { + switch (retval) { case ERROR_ETM_ANALYSIS_FAILED: - command_print(CMD_CTX, "further analysis failed (corrupted trace data or just end of data"); + command_print(CMD_CTX, + "further analysis failed (corrupted trace data or just end of data"); break; case ERROR_TRACE_INSTRUCTION_UNAVAILABLE: - command_print(CMD_CTX, "no instruction for current address available, analysis aborted"); + command_print(CMD_CTX, + "no instruction for current address available, analysis aborted"); break; case ERROR_TRACE_IMAGE_UNAVAILABLE: command_print(CMD_CTX, "no image available for trace analysis"); diff --git a/src/target/etm.h b/src/target/etm.h index 4224de6..0834095 100644 --- a/src/target/etm.h +++ b/src/target/etm.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ETM_H #define ETM_H @@ -29,8 +30,7 @@ struct image; /* ETM registers (JTAG protocol) */ -enum -{ +enum { ETM_CTRL = 0x00, ETM_CONFIG = 0x01, ETM_TRIG_EVENT = 0x02, @@ -71,8 +71,7 @@ enum ETM_ID = 0x79, }; -struct etm_reg -{ +struct etm_reg { uint32_t value; const struct etm_reg_info *reg_info; struct arm_jtag *jtag_info; @@ -84,8 +83,7 @@ struct etm_reg * * NOTE that these have evolved since the ~v1.3 defns ... */ -enum -{ +enum { ETM_CTRL_POWERDOWN = (1 << 0), ETM_CTRL_MONITOR_CPRT = (1 << 1), @@ -118,7 +116,7 @@ enum ETM_PORT_HALF_CLOCK = (1 << 13), ETM_PORT_CLOCK_MASK = (1 << 13), - // bits 15:14 == context ID size used in tracing + /* bits 15:14 == context ID size used in tracing */ ETM_CTRL_CONTEXTID_NONE = (0 << 14), ETM_CTRL_CONTEXTID_8 = (1 << 14), ETM_CTRL_CONTEXTID_16 = (2 << 14), @@ -131,14 +129,13 @@ enum ETM_PORT_DEMUXED = (2 << 16), ETM_PORT_MODE_MASK = (3 << 16), - // bits 31:18 defined in v3.0 and later (e.g. ARM11+) + /* bits 31:18 defined in v3.0 and later (e.g. ARM11+) */ }; /* forward-declare ETM context */ struct etm_context; -struct etm_capture_driver -{ +struct etm_capture_driver { const char *name; const struct command_registration *commands; int (*init)(struct etm_context *etm_ctx); @@ -148,14 +145,12 @@ struct etm_capture_driver int (*stop_capture)(struct etm_context *etm_ctx); }; -enum -{ +enum { ETMV1_TRACESYNC_CYCLE = 0x1, ETMV1_TRIGGER_CYCLE = 0x2, }; -struct etmv1_trace_data -{ +struct etmv1_trace_data { uint8_t pipestat; /* bits 0-2 pipeline status */ uint16_t packet; /* packet data (4, 8 or 16 bit) */ int flags; /* ETMV1_TRACESYNC_CYCLE, ETMV1_TRIGGER_CYCLE */ @@ -166,8 +161,7 @@ struct etmv1_trace_data * this will have to be split into version independent elements * and a version specific part */ -struct etm_context -{ +struct etm_context { struct target *target; /* target this ETM is connected to */ struct reg_cache *reg_cache; /* ETM register cache */ struct etm_capture_driver *capture_driver; /* driver used to access ETM data */ @@ -194,8 +188,7 @@ struct etm_context }; /* PIPESTAT values */ -typedef enum -{ +typedef enum { STAT_IE = 0x0, STAT_ID = 0x1, STAT_IN = 0x2, @@ -207,8 +200,7 @@ typedef enum } etmv1_pipestat_t; /* branch reason values */ -typedef enum -{ +typedef enum { BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */ BR_ENABLE = 0x1, /* Trace has been enabled */ BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */ @@ -219,7 +211,7 @@ typedef enum BR_RSVD7 = 0x7, /* reserved */ } etmv1_branch_reason_t; -struct reg_cache* etm_build_reg_cache(struct target *target, +struct reg_cache *etm_build_reg_cache(struct target *target, struct arm_jtag *jtag_info, struct etm_context *etm_ctx); int etm_setup(struct target *target); diff --git a/src/target/etm_dummy.c b/src/target/etm_dummy.c index f9c6fe7..f8e0fef 100644 --- a/src/target/etm_dummy.c +++ b/src/target/etm_dummy.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -24,7 +25,6 @@ #include "arm.h" #include "etm_dummy.h" - COMMAND_HANDLER(handle_etm_dummy_config_command) { struct target *target; @@ -32,25 +32,20 @@ COMMAND_HANDLER(handle_etm_dummy_config_command) target = get_target(CMD_ARGV[0]); - if (!target) - { + if (!target) { LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "target '%s' isn't an ARM", CMD_ARGV[0]); return ERROR_FAIL; } if (arm->etm) - { arm->etm->capture_driver_priv = NULL; - } - else - { + else { LOG_ERROR("target has no ETM defined, ETM dummy left unconfigured"); return ERROR_FAIL; } @@ -102,8 +97,7 @@ static int etm_dummy_stop_capture(struct etm_context *etm_ctx) return ERROR_OK; } -struct etm_capture_driver etm_dummy_capture_driver = -{ +struct etm_capture_driver etm_dummy_capture_driver = { .name = "dummy", .commands = etm_dummy_command_handlers, .init = etm_dummy_init, diff --git a/src/target/etm_dummy.h b/src/target/etm_dummy.h index 2673e4f..610ed92 100644 --- a/src/target/etm_dummy.h +++ b/src/target/etm_dummy.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef ETM_DUMMY_H #define ETM_DUMMY_H diff --git a/src/target/fa526.c b/src/target/fa526.c index d9d5d43..c08ee7c 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -41,7 +41,7 @@ static void fa526_change_to_arm(struct target *target, uint32_t *r0, uint32_t *p } static void fa526_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]) + uint32_t mask, uint32_t *core_regs[16]) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -59,8 +59,7 @@ static void fa526_read_core_regs(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ arm9tdmi_clock_data_in(jtag_info, core_regs[i]); @@ -68,7 +67,7 @@ static void fa526_read_core_regs(struct target *target, } static void fa526_read_core_regs_target_buffer(struct target *target, - uint32_t mask, void* buffer, int size) + uint32_t mask, void *buffer, int size) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -90,12 +89,10 @@ static void fa526_read_core_regs_target_buffer(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -188,8 +185,7 @@ static void fa526_write_xpsr_im8(struct target *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* rot == 4 writes flags, which takes only one cycle */ - if (rot != 4) - { + if (rot != 4) { /* nothing fetched, MSR in EXECUTE (2) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* nothing fetched, MSR in EXECUTE (3) */ @@ -216,8 +212,7 @@ static void fa526_write_core_regs(struct target *target, /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); @@ -346,14 +341,13 @@ static int fa526_init_arch_info(struct target *target, static int fa526_target_create(struct target *target, Jim_Interp *interp) { - struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common)); + struct arm920t_common *arm920t = calloc(1, sizeof(struct arm920t_common)); return fa526_init_arch_info(target, arm920t, target->tap); } /** Holds methods for FA526 targets. */ -struct target_type fa526_target = -{ +struct target_type fa526_target = { .name = "fa526", .poll = arm7_9_poll, diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 3617b2b..1a358b2 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -58,7 +58,6 @@ #include "register.h" #include "arm_opcodes.h" - static int feroceon_assert_reset(struct target *target) { struct arm *arm = target->arch_info; @@ -160,7 +159,7 @@ static void feroceon_change_to_arm(struct target *target, uint32_t *r0, } static void feroceon_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]) + uint32_t mask, uint32_t *core_regs[16]) { int i; struct arm *arm = target->arch_info; @@ -180,7 +179,7 @@ static void feroceon_read_core_regs(struct target *target, } static void feroceon_read_core_regs_target_buffer(struct target *target, - uint32_t mask, void* buffer, int size) + uint32_t mask, void *buffer, int size) { int i; struct arm *arm = target->arch_info; @@ -195,11 +194,9 @@ static void feroceon_read_core_regs_target_buffer(struct target *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) { - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -350,7 +347,7 @@ static void feroceon_branch_resume_thumb(struct target *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); // add r0,pc,#1 + arm9tdmi_clock_out(jtag_info, 0xE28F0001, 0, NULL, 0); /* add r0,pc,#1 */ arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -452,9 +449,7 @@ static int feroceon_examine_debug_reason(struct target *target) { /* the MOE is not implemented */ if (target->debug_reason != DBG_REASON_SINGLESTEP) - { target->debug_reason = DBG_REASON_DBGRQ; - } return ERROR_OK; } @@ -473,8 +468,7 @@ static int feroceon_bulk_write_memory(struct target *target, * We can't use the dcc flow control bits, so let's transfer data * with 31 bits and flip the MSB each time a new data word is sent. */ - static uint32_t dcc_code[] = - { + static uint32_t dcc_code[] = { 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ 0xe3a0301e, /* 1: mov r3, #30 */ 0xe3a04002, /* mov r4, #2 */ @@ -503,13 +497,11 @@ static int feroceon_bulk_write_memory(struct target *target, return target_write_memory(target, address, 4, count, buffer); /* regrab previously allocated working_area, or allocate a new one */ - if (!arm7_9->dcc_working_area) - { + if (!arm7_9->dcc_working_area) { uint8_t dcc_code_buf[dcc_size]; /* make sure we have a working area */ - if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) - { + if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); return target_write_memory(target, address, 4, count, buffer); } @@ -519,10 +511,10 @@ static int feroceon_bulk_write_memory(struct target *target, target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); /* write DCC code to working area */ - if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf)) != ERROR_OK) - { + retval = target_write_memory(target, + arm7_9->dcc_working_area->address, 4, dcc_size/4, dcc_code_buf); + if (retval != ERROR_OK) return retval; - } } /* backup clobbered processor state */ @@ -543,14 +535,12 @@ static int feroceon_bulk_write_memory(struct target *target, x = 0; flip = 0; shift = 1; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { uint32_t y = target_buffer_get_u32(target, buffer); uint32_t z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = y << (32 - shift); - if (++shift >= 32 || i + 1 >= count) - { + if (++shift >= 32 || i + 1 >= count) { z = (x >> 1) | (flip ^= 0x80000000); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = 0; @@ -563,20 +553,19 @@ static int feroceon_bulk_write_memory(struct target *target, if (retval == ERROR_OK) retval = target_wait_state(target, TARGET_HALTED, 500); if (retval == ERROR_OK) { - uint32_t endaddress = + uint32_t endaddress = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); if (endaddress != address + count*4) { LOG_ERROR("DCC write failed," " expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", - address + count*4, endaddress); + address + count*4, endaddress); retval = ERROR_FAIL; } } /* restore target state */ - for (i = 0; i <= 5; i++) - { + for (i = 0; i <= 5; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); arm->core_cache->reg_list[i].valid = 1; arm->core_cache->reg_list[i].dirty = 1; @@ -631,7 +620,7 @@ static void feroceon_common_setup(struct target *target) static int feroceon_target_create(struct target *target, Jim_Interp *interp) { - struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common)); + struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); arm926ejs_init_arch_info(target, arm926ejs, target->tap); feroceon_common_setup(target); @@ -645,7 +634,7 @@ static int feroceon_target_create(struct target *target, Jim_Interp *interp) static int dragonite_target_create(struct target *target, Jim_Interp *interp) { - struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common)); + struct arm966e_common *arm966e = calloc(1, sizeof(struct arm966e_common)); arm966e_init_arch_info(target, arm966e, target->tap); feroceon_common_setup(target); @@ -687,8 +676,7 @@ static int feroceon_examine(struct target *target) return ERROR_OK; } -struct target_type feroceon_target = -{ +struct target_type feroceon_target = { .name = "feroceon", .poll = arm7_9_poll, @@ -726,8 +714,7 @@ struct target_type feroceon_target = .examine = feroceon_examine, }; -struct target_type dragonite_target = -{ +struct target_type dragonite_target = { .name = "dragonite", .poll = arm7_9_poll, @@ -764,4 +751,3 @@ struct target_type dragonite_target = .init_target = feroceon_init_target, .examine = feroceon_examine, }; - diff --git a/src/target/image.c b/src/target/image.c index c0aabec..4a4a7cc 100644 --- a/src/target/image.c +++ b/src/target/image.c @@ -26,6 +26,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -34,15 +35,14 @@ #include "target.h" #include <helper/log.h> - /* convert ELF header field to host endianness */ -#define field16(elf,field)\ - ((elf->endianness == ELFDATA2LSB)? \ - le_to_h_u16((uint8_t*)&field):be_to_h_u16((uint8_t*)&field)) +#define field16(elf, field) \ + ((elf->endianness == ELFDATA2LSB) ? \ + le_to_h_u16((uint8_t *)&field) : be_to_h_u16((uint8_t *)&field)) -#define field32(elf,field)\ - ((elf->endianness == ELFDATA2LSB)? \ - le_to_h_u32((uint8_t*)&field):be_to_h_u32((uint8_t*)&field)) +#define field32(elf, field) \ + ((elf->endianness == ELFDATA2LSB) ? \ + le_to_h_u32((uint8_t *)&field) : be_to_h_u32((uint8_t *)&field)) static int autodetect_image_type(struct image *image, const char *url) { @@ -52,18 +52,14 @@ static int autodetect_image_type(struct image *image, const char *url) uint8_t buffer[9]; /* read the first 4 bytes of image */ - if ((retval = fileio_open(&fileio, url, FILEIO_READ, FILEIO_BINARY)) != ERROR_OK) - { + retval = fileio_open(&fileio, url, FILEIO_READ, FILEIO_BINARY); + if (retval != ERROR_OK) return retval; - } retval = fileio_read(&fileio, 9, buffer, &read_bytes); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { if (read_bytes != 9) - { retval = ERROR_FILEIO_OPERATION_FAILED; - } } fileio_close(&fileio); @@ -71,83 +67,59 @@ static int autodetect_image_type(struct image *image, const char *url) return retval; /* check header against known signatures */ - if (strncmp((char*)buffer,ELFMAG,SELFMAG) == 0) - { + if (strncmp((char *)buffer, ELFMAG, SELFMAG) == 0) { LOG_DEBUG("ELF image detected."); image->type = IMAGE_ELF; - } - else if ((buffer[0]==':') /* record start byte */ - &&(isxdigit(buffer[1])) - &&(isxdigit(buffer[2])) - &&(isxdigit(buffer[3])) - &&(isxdigit(buffer[4])) - &&(isxdigit(buffer[5])) - &&(isxdigit(buffer[6])) - &&(buffer[7]=='0') /* record type : 00 -> 05 */ - &&(buffer[8]>='0') && (buffer[8]<'6')) - { + } else if ((buffer[0] == ':') /* record start byte */ + && (isxdigit(buffer[1])) + && (isxdigit(buffer[2])) + && (isxdigit(buffer[3])) + && (isxdigit(buffer[4])) + && (isxdigit(buffer[5])) + && (isxdigit(buffer[6])) + && (buffer[7] == '0') /* record type : 00 -> 05 */ + && (buffer[8] >= '0') && (buffer[8] < '6')) { LOG_DEBUG("IHEX image detected."); image->type = IMAGE_IHEX; - } - else if ((buffer[0] == 'S') /* record start byte */ - &&(isxdigit(buffer[1])) - &&(isxdigit(buffer[2])) - &&(isxdigit(buffer[3])) - &&(buffer[1] >= '0') && (buffer[1] < '9')) - { + } else if ((buffer[0] == 'S') /* record start byte */ + && (isxdigit(buffer[1])) + && (isxdigit(buffer[2])) + && (isxdigit(buffer[3])) + && (buffer[1] >= '0') && (buffer[1] < '9')) { LOG_DEBUG("S19 image detected."); image->type = IMAGE_SRECORD; - } - else - { + } else image->type = IMAGE_BINARY; - } return ERROR_OK; } static int identify_image_type(struct image *image, const char *type_string, const char *url) { - if (type_string) - { + if (type_string) { if (!strcmp(type_string, "bin")) - { image->type = IMAGE_BINARY; - } else if (!strcmp(type_string, "ihex")) - { image->type = IMAGE_IHEX; - } else if (!strcmp(type_string, "elf")) - { image->type = IMAGE_ELF; - } else if (!strcmp(type_string, "mem")) - { image->type = IMAGE_MEMORY; - } else if (!strcmp(type_string, "s19")) - { image->type = IMAGE_SRECORD; - } else if (!strcmp(type_string, "build")) - { image->type = IMAGE_BUILDER; - } else - { return ERROR_IMAGE_TYPE_UNKNOWN; - } - } - else - { + } else return autodetect_image_type(image, url); - } return ERROR_OK; } -static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, struct imagesection *section) +static int image_ihex_buffer_complete_inner(struct image *image, + char *lpszLine, + struct imagesection *section) { struct image_ihex *ihex = image->type_private; struct fileio *fileio = &ihex->fileio; @@ -172,8 +144,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) - { + while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) { uint32_t count; uint32_t address; uint32_t record_type; @@ -181,10 +152,9 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, uint8_t cal_checksum = 0; size_t bytes_read = 0; - if (sscanf(&lpszLine[bytes_read], ":%2" SCNx32 "%4" SCNx32 "%2" SCNx32 , &count, &address, &record_type) != 3) - { + if (sscanf(&lpszLine[bytes_read], ":%2" SCNx32 "%4" SCNx32 "%2" SCNx32, &count, + &address, &record_type) != 3) return ERROR_IMAGE_FORMAT_ERROR; - } bytes_read += 9; cal_checksum += (uint8_t)count; @@ -192,34 +162,30 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, cal_checksum += (uint8_t)address; cal_checksum += (uint8_t)record_type; - if (record_type == 0) /* Data Record */ - { - if ((full_address & 0xffff) != address) - { + if (record_type == 0) { /* Data Record */ + if ((full_address & 0xffff) != address) { /* we encountered a nonconsecutive location, create a new section, * unless the current section has zero size, in which case this specifies * the current section's base address */ - if (section[image->num_sections].size != 0) - { + if (section[image->num_sections].size != 0) { image->num_sections++; - if (image->num_sections >= IMAGE_MAX_SECTIONS) - { + if (image->num_sections >= IMAGE_MAX_SECTIONS) { /* too many sections */ LOG_ERROR("Too many sections found in IHEX file"); return ERROR_IMAGE_FORMAT_ERROR; } section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - section[image->num_sections].private = &ihex->buffer[cooked_bytes]; + section[image->num_sections].private = + &ihex->buffer[cooked_bytes]; } section[image->num_sections].base_address = (full_address & 0xffff0000) | address; full_address = (full_address & 0xffff0000) | address; } - while (count-- > 0) - { + while (count-- > 0) { unsigned value; sscanf(&lpszLine[bytes_read], "%2x", &value); ihex->buffer[cooked_bytes] = (uint8_t)value; @@ -229,16 +195,13 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, section[image->num_sections].size += 1; full_address++; } - } - else if (record_type == 1) /* End of File Record */ - { + } else if (record_type == 1) { /* End of File Record */ /* finish the current section */ image->num_sections++; /* copy section information */ image->sections = malloc(sizeof(struct imagesection) * image->num_sections); - for (i = 0; i < image->num_sections; i++) - { + for (i = 0; i < image->num_sections; i++) { image->sections[i].private = section[i].private; image->sections[i].base_address = section[i].base_address; image->sections[i].size = section[i].size; @@ -246,9 +209,7 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, } return ERROR_OK; - } - else if (record_type == 2) /* Linear Address Record */ - { + } else if (record_type == 2) { /* Linear Address Record */ uint16_t upper_address; sscanf(&lpszLine[bytes_read], "%4hx", &upper_address); @@ -256,45 +217,38 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, cal_checksum += (uint8_t)upper_address; bytes_read += 4; - if ((full_address >> 4) != upper_address) - { + if ((full_address >> 4) != upper_address) { /* we encountered a nonconsecutive location, create a new section, * unless the current section has zero size, in which case this specifies * the current section's base address */ - if (section[image->num_sections].size != 0) - { + if (section[image->num_sections].size != 0) { image->num_sections++; - if (image->num_sections >= IMAGE_MAX_SECTIONS) - { + if (image->num_sections >= IMAGE_MAX_SECTIONS) { /* too many sections */ LOG_ERROR("Too many sections found in IHEX file"); return ERROR_IMAGE_FORMAT_ERROR; } section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - section[image->num_sections].private = &ihex->buffer[cooked_bytes]; + section[image->num_sections].private = + &ihex->buffer[cooked_bytes]; } section[image->num_sections].base_address = (full_address & 0xffff) | (upper_address << 4); full_address = (full_address & 0xffff) | (upper_address << 4); } - } - else if (record_type == 3) /* Start Segment Address Record */ - { + } else if (record_type == 3) { /* Start Segment Address Record */ uint32_t dummy; - /* "Start Segment Address Record" will not be supported */ - /* but we must consume it, and do not create an error. */ - while (count-- > 0) - { - sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &dummy); + /* "Start Segment Address Record" will not be supported + * but we must consume it, and do not create an error. */ + while (count-- > 0) { + sscanf(&lpszLine[bytes_read], "%2" SCNx32, &dummy); cal_checksum += (uint8_t)dummy; bytes_read += 2; } - } - else if (record_type == 4) /* Extended Linear Address Record */ - { + } else if (record_type == 4) { /* Extended Linear Address Record */ uint16_t upper_address; sscanf(&lpszLine[bytes_read], "%4hx", &upper_address); @@ -302,32 +256,28 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, cal_checksum += (uint8_t)upper_address; bytes_read += 4; - if ((full_address >> 16) != upper_address) - { + if ((full_address >> 16) != upper_address) { /* we encountered a nonconsecutive location, create a new section, * unless the current section has zero size, in which case this specifies * the current section's base address */ - if (section[image->num_sections].size != 0) - { + if (section[image->num_sections].size != 0) { image->num_sections++; - if (image->num_sections >= IMAGE_MAX_SECTIONS) - { + if (image->num_sections >= IMAGE_MAX_SECTIONS) { /* too many sections */ LOG_ERROR("Too many sections found in IHEX file"); return ERROR_IMAGE_FORMAT_ERROR; } section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - section[image->num_sections].private = &ihex->buffer[cooked_bytes]; + section[image->num_sections].private = + &ihex->buffer[cooked_bytes]; } section[image->num_sections].base_address = (full_address & 0xffff) | (upper_address << 16); full_address = (full_address & 0xffff) | (upper_address << 16); } - } - else if (record_type == 5) /* Start Linear Address Record */ - { + } else if (record_type == 5) { /* Start Linear Address Record */ uint32_t start_address; sscanf(&lpszLine[bytes_read], "%8" SCNx32, &start_address); @@ -338,18 +288,15 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, bytes_read += 8; image->start_address_set = 1; - image->start_address = be_to_h_u32((uint8_t*)&start_address); - } - else - { - LOG_ERROR("unhandled IHEX record type: %i", (int)record_type); + image->start_address = be_to_h_u32((uint8_t *)&start_address); + } else { + LOG_ERROR("unhandled IHEX record type: %i", (int)record_type); return ERROR_IMAGE_FORMAT_ERROR; } - sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &checksum); + sscanf(&lpszLine[bytes_read], "%2" SCNx32, &checksum); - if ((uint8_t)checksum != (uint8_t)(~cal_checksum + 1)) - { + if ((uint8_t)checksum != (uint8_t)(~cal_checksum + 1)) { /* checksum failed */ LOG_ERROR("incorrect record checksum found in IHEX file"); return ERROR_IMAGE_CHECKSUM; @@ -367,14 +314,12 @@ static int image_ihex_buffer_complete_inner(struct image *image, char *lpszLine, static int image_ihex_buffer_complete(struct image *image) { char *lpszLine = malloc(1023); - if (lpszLine == NULL) - { + if (lpszLine == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } struct imagesection *section = malloc(sizeof(struct imagesection) * IMAGE_MAX_SECTIONS); - if (section == NULL) - { + if (section == NULL) { free(lpszLine); LOG_ERROR("Out of memory"); return ERROR_FAIL; @@ -393,83 +338,78 @@ static int image_elf_read_headers(struct image *image) { struct image_elf *elf = image->type_private; size_t read_bytes; - uint32_t i,j; + uint32_t i, j; int retval; - uint32_t nload,load_to_vaddr=0; + uint32_t nload, load_to_vaddr = 0; elf->header = malloc(sizeof(Elf32_Ehdr)); - if (elf->header == NULL) - { + if (elf->header == NULL) { LOG_ERROR("insufficient memory to perform operation "); return ERROR_FILEIO_OPERATION_FAILED; } - if ((retval = fileio_read(&elf->fileio, sizeof(Elf32_Ehdr), (uint8_t*)elf->header, &read_bytes)) != ERROR_OK) - { + retval = fileio_read(&elf->fileio, sizeof(Elf32_Ehdr), (uint8_t *)elf->header, &read_bytes); + if (retval != ERROR_OK) { LOG_ERROR("cannot read ELF file header, read failed"); return ERROR_FILEIO_OPERATION_FAILED; } - if (read_bytes != sizeof(Elf32_Ehdr)) - { + if (read_bytes != sizeof(Elf32_Ehdr)) { LOG_ERROR("cannot read ELF file header, only partially read"); return ERROR_FILEIO_OPERATION_FAILED; } - if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG) != 0) - { + if (strncmp((char *)elf->header->e_ident, ELFMAG, SELFMAG) != 0) { LOG_ERROR("invalid ELF file, bad magic number"); return ERROR_IMAGE_FORMAT_ERROR; } - if (elf->header->e_ident[EI_CLASS]!=ELFCLASS32) - { + if (elf->header->e_ident[EI_CLASS] != ELFCLASS32) { LOG_ERROR("invalid ELF file, only 32bits files are supported"); return ERROR_IMAGE_FORMAT_ERROR; } elf->endianness = elf->header->e_ident[EI_DATA]; if ((elf->endianness != ELFDATA2LSB) - &&(elf->endianness != ELFDATA2MSB)) - { + && (elf->endianness != ELFDATA2MSB)) { LOG_ERROR("invalid ELF file, unknown endianness setting"); return ERROR_IMAGE_FORMAT_ERROR; } - elf->segment_count = field16(elf,elf->header->e_phnum); - if (elf->segment_count == 0) - { + elf->segment_count = field16(elf, elf->header->e_phnum); + if (elf->segment_count == 0) { LOG_ERROR("invalid ELF file, no program headers"); return ERROR_IMAGE_FORMAT_ERROR; } - if ((retval = fileio_seek(&elf->fileio, field32(elf,elf->header->e_phoff))) != ERROR_OK) - { + retval = fileio_seek(&elf->fileio, field32(elf, elf->header->e_phoff)); + if (retval != ERROR_OK) { LOG_ERROR("cannot seek to ELF program header table, read failed"); return retval; } elf->segments = malloc(elf->segment_count*sizeof(Elf32_Phdr)); - if (elf->segments == NULL) - { + if (elf->segments == NULL) { LOG_ERROR("insufficient memory to perform operation "); return ERROR_FILEIO_OPERATION_FAILED; } - if ((retval = fileio_read(&elf->fileio, elf->segment_count*sizeof(Elf32_Phdr), (uint8_t*)elf->segments, &read_bytes)) != ERROR_OK) - { + retval = fileio_read(&elf->fileio, elf->segment_count*sizeof(Elf32_Phdr), + (uint8_t *)elf->segments, &read_bytes); + if (retval != ERROR_OK) { LOG_ERROR("cannot read ELF segment headers, read failed"); return retval; } - if (read_bytes != elf->segment_count*sizeof(Elf32_Phdr)) - { + if (read_bytes != elf->segment_count*sizeof(Elf32_Phdr)) { LOG_ERROR("cannot read ELF segment headers, only partially read"); return ERROR_FILEIO_OPERATION_FAILED; } /* count useful segments (loadable), ignore BSS section */ image->num_sections = 0; - for (i = 0;i < elf->segment_count;i++) - if ((field32(elf, elf->segments[i].p_type) == PT_LOAD) && (field32(elf, elf->segments[i].p_filesz) != 0)) + for (i = 0; i < elf->segment_count; i++) + if ((field32(elf, + elf->segments[i].p_type) == PT_LOAD) && + (field32(elf, elf->segments[i].p_filesz) != 0)) image->num_sections++; assert(image->num_sections > 0); @@ -487,7 +427,9 @@ static int image_elf_read_headers(struct image *image) for (nload = 0, i = 0; i < elf->segment_count; i++) if (elf->segments[i].p_paddr != 0) break; - else if ((field32(elf, elf->segments[i].p_type) == PT_LOAD) && (field32(elf, elf->segments[i].p_memsz) != 0)) + else if ((field32(elf, + elf->segments[i].p_type) == PT_LOAD) && + (field32(elf, elf->segments[i].p_memsz) != 0)) ++nload; if (i >= elf->segment_count && nload > 1) @@ -495,53 +437,59 @@ static int image_elf_read_headers(struct image *image) /* alloc and fill sections array with loadable segments */ image->sections = malloc(image->num_sections * sizeof(struct imagesection)); - for (i = 0,j = 0;i < elf->segment_count;i++) - { - if ((field32(elf, elf->segments[i].p_type) == PT_LOAD) && (field32(elf, elf->segments[i].p_filesz) != 0)) - { - image->sections[j].size = field32(elf,elf->segments[i].p_filesz); + for (i = 0, j = 0; i < elf->segment_count; i++) { + if ((field32(elf, + elf->segments[i].p_type) == PT_LOAD) && + (field32(elf, elf->segments[i].p_filesz) != 0)) { + image->sections[j].size = field32(elf, elf->segments[i].p_filesz); if (load_to_vaddr) - image->sections[j].base_address = field32(elf,elf->segments[i].p_vaddr); + image->sections[j].base_address = field32(elf, + elf->segments[i].p_vaddr); else - image->sections[j].base_address = field32(elf,elf->segments[i].p_paddr); + image->sections[j].base_address = field32(elf, + elf->segments[i].p_paddr); image->sections[j].private = &elf->segments[i]; - image->sections[j].flags = field32(elf,elf->segments[i].p_flags); + image->sections[j].flags = field32(elf, elf->segments[i].p_flags); j++; } } image->start_address_set = 1; - image->start_address = field32(elf,elf->header->e_entry); + image->start_address = field32(elf, elf->header->e_entry); return ERROR_OK; } -static int image_elf_read_section(struct image *image, int section, uint32_t offset, uint32_t size, uint8_t *buffer, size_t *size_read) +static int image_elf_read_section(struct image *image, + int section, + uint32_t offset, + uint32_t size, + uint8_t *buffer, + size_t *size_read) { struct image_elf *elf = image->type_private; Elf32_Phdr *segment = (Elf32_Phdr *)image->sections[section].private; - size_t read_size,really_read; + size_t read_size, really_read; int retval; *size_read = 0; - LOG_DEBUG("load segment %d at 0x%" PRIx32 " (sz = 0x%" PRIx32 ")",section,offset,size); + LOG_DEBUG("load segment %d at 0x%" PRIx32 " (sz = 0x%" PRIx32 ")", section, offset, size); /* read initialized data in current segment if any */ - if (offset < field32(elf,segment->p_filesz)) - { + if (offset < field32(elf, segment->p_filesz)) { /* maximal size present in file for the current segment */ - read_size = MIN(size, field32(elf,segment->p_filesz)-offset); + read_size = MIN(size, field32(elf, segment->p_filesz) - offset); LOG_DEBUG("read elf: size = 0x%zu at 0x%" PRIx32 "", read_size, - field32(elf,segment->p_offset) + offset); + field32(elf, segment->p_offset) + offset); /* read initialized area of the segment */ - if ((retval = fileio_seek(&elf->fileio, field32(elf,segment->p_offset) + offset)) != ERROR_OK) - { + retval = fileio_seek(&elf->fileio, field32(elf, segment->p_offset) + offset); + if (retval != ERROR_OK) { LOG_ERROR("cannot find ELF segment content, seek failed"); return retval; } - if ((retval = fileio_read(&elf->fileio, read_size, buffer, &really_read)) != ERROR_OK) - { + retval = fileio_read(&elf->fileio, read_size, buffer, &really_read); + if (retval != ERROR_OK) { LOG_ERROR("cannot read ELF segment content, read failed"); return retval; } @@ -555,7 +503,9 @@ static int image_elf_read_section(struct image *image, int section, uint32_t off return ERROR_OK; } -static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, struct imagesection *section) +static int image_mot_buffer_complete_inner(struct image *image, + char *lpszLine, + struct imagesection *section) { struct image_mot *mot = image->type_private; struct fileio *fileio = &mot->fileio; @@ -580,8 +530,7 @@ static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) - { + while (fileio_fgets(fileio, 1023, lpszLine) == ERROR_OK) { uint32_t count; uint32_t address; uint32_t record_type; @@ -590,19 +539,17 @@ static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, uint32_t bytes_read = 0; /* get record type and record length */ - if (sscanf(&lpszLine[bytes_read], "S%1" SCNx32 "%2" SCNx32 , &record_type, &count) != 2) - { + if (sscanf(&lpszLine[bytes_read], "S%1" SCNx32 "%2" SCNx32, &record_type, + &count) != 2) return ERROR_IMAGE_FORMAT_ERROR; - } bytes_read += 4; cal_checksum += (uint8_t)count; /* skip checksum byte */ - count -=1; + count -= 1; - if (record_type == 0) - { + if (record_type == 0) { /* S0 - starting record (optional) */ int iValue; @@ -611,62 +558,57 @@ static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, cal_checksum += (uint8_t)iValue; bytes_read += 2; } - } - else if (record_type >= 1 && record_type <= 3) - { - switch (record_type) - { + } else if (record_type >= 1 && record_type <= 3) { + switch (record_type) { case 1: /* S1 - 16 bit address data record */ sscanf(&lpszLine[bytes_read], "%4" SCNx32, &address); cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)address; bytes_read += 4; - count -=2; + count -= 2; break; case 2: /* S2 - 24 bit address data record */ - sscanf(&lpszLine[bytes_read], "%6" SCNx32 , &address); + sscanf(&lpszLine[bytes_read], "%6" SCNx32, &address); cal_checksum += (uint8_t)(address >> 16); cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)address; bytes_read += 6; - count -=3; + count -= 3; break; case 3: /* S3 - 32 bit address data record */ - sscanf(&lpszLine[bytes_read], "%8" SCNx32 , &address); + sscanf(&lpszLine[bytes_read], "%8" SCNx32, &address); cal_checksum += (uint8_t)(address >> 24); cal_checksum += (uint8_t)(address >> 16); cal_checksum += (uint8_t)(address >> 8); cal_checksum += (uint8_t)address; bytes_read += 8; - count -=4; + count -= 4; break; } - if (full_address != address) - { + if (full_address != address) { /* we encountered a nonconsecutive location, create a new section, * unless the current section has zero size, in which case this specifies * the current section's base address */ - if (section[image->num_sections].size != 0) - { + if (section[image->num_sections].size != 0) { image->num_sections++; section[image->num_sections].size = 0x0; section[image->num_sections].flags = 0; - section[image->num_sections].private = &mot->buffer[cooked_bytes]; + section[image->num_sections].private = + &mot->buffer[cooked_bytes]; } section[image->num_sections].base_address = address; full_address = address; } - while (count-- > 0) - { + while (count-- > 0) { unsigned value; sscanf(&lpszLine[bytes_read], "%2x", &value); mot->buffer[cooked_bytes] = (uint8_t)value; @@ -676,28 +618,22 @@ static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, section[image->num_sections].size += 1; full_address++; } - } - else if (record_type == 5) - { + } else if (record_type == 5) { /* S5 is the data count record, we ignore it */ uint32_t dummy; - while (count-- > 0) - { - sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &dummy); + while (count-- > 0) { + sscanf(&lpszLine[bytes_read], "%2" SCNx32, &dummy); cal_checksum += (uint8_t)dummy; bytes_read += 2; } - } - else if (record_type >= 7 && record_type <= 9) - { + } else if (record_type >= 7 && record_type <= 9) { /* S7, S8, S9 - ending records for 32, 24 and 16bit */ image->num_sections++; /* copy section information */ image->sections = malloc(sizeof(struct imagesection) * image->num_sections); - for (i = 0; i < image->num_sections; i++) - { + for (i = 0; i < image->num_sections; i++) { image->sections[i].private = section[i].private; image->sections[i].base_address = section[i].base_address; image->sections[i].size = section[i].size; @@ -705,19 +641,16 @@ static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, } return ERROR_OK; - } - else - { - LOG_ERROR("unhandled S19 record type: %i", (int)(record_type)); + } else { + LOG_ERROR("unhandled S19 record type: %i", (int)(record_type)); return ERROR_IMAGE_FORMAT_ERROR; } /* account for checksum, will always be 0xFF */ - sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &checksum); + sscanf(&lpszLine[bytes_read], "%2" SCNx32, &checksum); cal_checksum += (uint8_t)checksum; - if (cal_checksum != 0xFF) - { + if (cal_checksum != 0xFF) { /* checksum failed */ LOG_ERROR("incorrect record checksum found in S19 file"); return ERROR_IMAGE_CHECKSUM; @@ -735,14 +668,12 @@ static int image_mot_buffer_complete_inner(struct image *image, char *lpszLine, static int image_mot_buffer_complete(struct image *image) { char *lpszLine = malloc(1023); - if (lpszLine == NULL) - { + if (lpszLine == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } struct imagesection *section = malloc(sizeof(struct imagesection) * IMAGE_MAX_SECTIONS); - if (section == NULL) - { + if (section == NULL) { free(lpszLine); LOG_ERROR("Out of memory"); return ERROR_FAIL; @@ -757,30 +688,25 @@ static int image_mot_buffer_complete(struct image *image) return retval; } - int image_open(struct image *image, const char *url, const char *type_string) { int retval = ERROR_OK; - if ((retval = identify_image_type(image, type_string, url)) != ERROR_OK) - { + retval = identify_image_type(image, type_string, url); + if (retval != ERROR_OK) return retval; - } - if (image->type == IMAGE_BINARY) - { + if (image->type == IMAGE_BINARY) { struct image_binary *image_binary; image_binary = image->type_private = malloc(sizeof(struct image_binary)); - if ((retval = fileio_open(&image_binary->fileio, url, FILEIO_READ, FILEIO_BINARY)) != ERROR_OK) - { + retval = fileio_open(&image_binary->fileio, url, FILEIO_READ, FILEIO_BINARY); + if (retval != ERROR_OK) return retval; - } int filesize; retval = fileio_size(&image_binary->fileio, &filesize); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { fileio_close(&image_binary->fileio); return retval; } @@ -790,48 +716,40 @@ int image_open(struct image *image, const char *url, const char *type_string) image->sections[0].base_address = 0x0; image->sections[0].size = filesize; image->sections[0].flags = 0; - } - else if (image->type == IMAGE_IHEX) - { + } else if (image->type == IMAGE_IHEX) { struct image_ihex *image_ihex; image_ihex = image->type_private = malloc(sizeof(struct image_ihex)); - if ((retval = fileio_open(&image_ihex->fileio, url, FILEIO_READ, FILEIO_TEXT)) != ERROR_OK) - { + retval = fileio_open(&image_ihex->fileio, url, FILEIO_READ, FILEIO_TEXT); + if (retval != ERROR_OK) return retval; - } - if ((retval = image_ihex_buffer_complete(image)) != ERROR_OK) - { - LOG_ERROR("failed buffering IHEX image, check daemon output for additional information"); + retval = image_ihex_buffer_complete(image); + if (retval != ERROR_OK) { + LOG_ERROR( + "failed buffering IHEX image, check daemon output for additional information"); fileio_close(&image_ihex->fileio); return retval; } - } - else if (image->type == IMAGE_ELF) - { + } else if (image->type == IMAGE_ELF) { struct image_elf *image_elf; image_elf = image->type_private = malloc(sizeof(struct image_elf)); - if ((retval = fileio_open(&image_elf->fileio, url, FILEIO_READ, FILEIO_BINARY)) != ERROR_OK) - { + retval = fileio_open(&image_elf->fileio, url, FILEIO_READ, FILEIO_BINARY); + if (retval != ERROR_OK) return retval; - } - if ((retval = image_elf_read_headers(image)) != ERROR_OK) - { + retval = image_elf_read_headers(image); + if (retval != ERROR_OK) { fileio_close(&image_elf->fileio); return retval; } - } - else if (image->type == IMAGE_MEMORY) - { + } else if (image->type == IMAGE_MEMORY) { struct target *target = get_target(url); - if (target == NULL) - { + if (target == NULL) { LOG_ERROR("target '%s' not defined", url); return ERROR_FAIL; } @@ -849,43 +767,36 @@ int image_open(struct image *image, const char *url, const char *type_string) image_memory->target = target; image_memory->cache = NULL; image_memory->cache_address = 0x0; - } - else if (image->type == IMAGE_SRECORD) - { + } else if (image->type == IMAGE_SRECORD) { struct image_mot *image_mot; image_mot = image->type_private = malloc(sizeof(struct image_mot)); - if ((retval = fileio_open(&image_mot->fileio, url, FILEIO_READ, FILEIO_TEXT)) != ERROR_OK) - { + retval = fileio_open(&image_mot->fileio, url, FILEIO_READ, FILEIO_TEXT); + if (retval != ERROR_OK) return retval; - } - if ((retval = image_mot_buffer_complete(image)) != ERROR_OK) - { - LOG_ERROR("failed buffering S19 image, check daemon output for additional information"); + retval = image_mot_buffer_complete(image); + if (retval != ERROR_OK) { + LOG_ERROR( + "failed buffering S19 image, check daemon output for additional information"); fileio_close(&image_mot->fileio); return retval; } - } - else if (image->type == IMAGE_BUILDER) - { + } else if (image->type == IMAGE_BUILDER) { image->num_sections = 0; image->sections = NULL; image->type_private = NULL; } - if (image->base_address_set) - { + if (image->base_address_set) { /* relocate */ int section; for (section = 0; section < image->num_sections; section++) - { image->sections[section].base_address += image->base_address; - } - /* we're done relocating. The two statements below are mainly - * for documenation purposes: stop anyone from empirically - * thinking they should use these values henceforth. */ + /* we're done relocating. The two statements below are mainly + * for documenation purposes: stop anyone from empirically + * thinking they should use these values henceforth. */ image->base_address = 0; image->base_address_set = 0; } @@ -893,20 +804,26 @@ int image_open(struct image *image, const char *url, const char *type_string) return retval; }; -int image_read_section(struct image *image, int section, uint32_t offset, uint32_t size, uint8_t *buffer, size_t *size_read) +int image_read_section(struct image *image, + int section, + uint32_t offset, + uint32_t size, + uint8_t *buffer, + size_t *size_read) { int retval; /* don't read past the end of a section */ - if (offset + size > image->sections[section].size) - { - LOG_DEBUG("read past end of section: 0x%8.8" PRIx32 " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32 "", - offset, size, image->sections[section].size); + if (offset + size > image->sections[section].size) { + LOG_DEBUG( + "read past end of section: 0x%8.8" PRIx32 " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32 "", + offset, + size, + image->sections[section].size); return ERROR_COMMAND_SYNTAX_ERROR; } - if (image->type == IMAGE_BINARY) - { + if (image->type == IMAGE_BINARY) { struct image_binary *image_binary = image->type_private; /* only one section in a plain binary */ @@ -914,77 +831,66 @@ int image_read_section(struct image *image, int section, uint32_t offset, uint32 return ERROR_COMMAND_SYNTAX_ERROR; /* seek to offset */ - if ((retval = fileio_seek(&image_binary->fileio, offset)) != ERROR_OK) - { + retval = fileio_seek(&image_binary->fileio, offset); + if (retval != ERROR_OK) return retval; - } /* return requested bytes */ - if ((retval = fileio_read(&image_binary->fileio, size, buffer, size_read)) != ERROR_OK) - { + retval = fileio_read(&image_binary->fileio, size, buffer, size_read); + if (retval != ERROR_OK) return retval; - } - } - else if (image->type == IMAGE_IHEX) - { - memcpy(buffer, (uint8_t*)image->sections[section].private + offset, size); + } else if (image->type == IMAGE_IHEX) { + memcpy(buffer, (uint8_t *)image->sections[section].private + offset, size); *size_read = size; return ERROR_OK; - } - else if (image->type == IMAGE_ELF) - { + } else if (image->type == IMAGE_ELF) return image_elf_read_section(image, section, offset, size, buffer, size_read); - } - else if (image->type == IMAGE_MEMORY) - { + else if (image->type == IMAGE_MEMORY) { struct image_memory *image_memory = image->type_private; uint32_t address = image->sections[section].base_address + offset; *size_read = 0; - while ((size - *size_read) > 0) - { + while ((size - *size_read) > 0) { uint32_t size_in_cache; if (!image_memory->cache || (address < image_memory->cache_address) - || (address >= (image_memory->cache_address + IMAGE_MEMORY_CACHE_SIZE))) - { + || (address >= + (image_memory->cache_address + IMAGE_MEMORY_CACHE_SIZE))) { if (!image_memory->cache) image_memory->cache = malloc(IMAGE_MEMORY_CACHE_SIZE); - if (target_read_buffer(image_memory->target, address & ~(IMAGE_MEMORY_CACHE_SIZE - 1), - IMAGE_MEMORY_CACHE_SIZE, image_memory->cache) != ERROR_OK) - { + if (target_read_buffer(image_memory->target, address & + ~(IMAGE_MEMORY_CACHE_SIZE - 1), + IMAGE_MEMORY_CACHE_SIZE, image_memory->cache) != ERROR_OK) { free(image_memory->cache); image_memory->cache = NULL; return ERROR_IMAGE_TEMPORARILY_UNAVAILABLE; } - image_memory->cache_address = address & ~(IMAGE_MEMORY_CACHE_SIZE - 1); + image_memory->cache_address = address & + ~(IMAGE_MEMORY_CACHE_SIZE - 1); } - size_in_cache = (image_memory->cache_address + IMAGE_MEMORY_CACHE_SIZE) - address; + size_in_cache = + (image_memory->cache_address + IMAGE_MEMORY_CACHE_SIZE) - address; memcpy(buffer + *size_read, image_memory->cache + (address - image_memory->cache_address), (size_in_cache > size) ? size : size_in_cache -); + ); *size_read += (size_in_cache > size) ? size : size_in_cache; address += (size_in_cache > size) ? size : size_in_cache; } - } - else if (image->type == IMAGE_SRECORD) - { - memcpy(buffer, (uint8_t*)image->sections[section].private + offset, size); + } else if (image->type == IMAGE_SRECORD) { + memcpy(buffer, (uint8_t *)image->sections[section].private + offset, size); *size_read = size; return ERROR_OK; - } - else if (image->type == IMAGE_BUILDER) - { - memcpy(buffer, (uint8_t*)image->sections[section].private + offset, size); + } else if (image->type == IMAGE_BUILDER) { + memcpy(buffer, (uint8_t *)image->sections[section].private + offset, size); *size_read = size; return ERROR_OK; @@ -1002,16 +908,15 @@ int image_add_section(struct image *image, uint32_t base, uint32_t size, int fla return ERROR_COMMAND_SYNTAX_ERROR; /* see if there's a previous section */ - if (image->num_sections) - { + if (image->num_sections) { section = &image->sections[image->num_sections - 1]; /* see if it's enough to extend the last section, * adding data to previous sections or merging is not supported */ - if (((section->base_address + section->size) == base) && (section->flags == flags)) - { + if (((section->base_address + section->size) == base) && + (section->flags == flags)) { section->private = realloc(section->private, section->size + size); - memcpy((uint8_t*)section->private + section->size, data, size); + memcpy((uint8_t *)section->private + section->size, data, size); section->size += size; return ERROR_OK; } @@ -1019,116 +924,96 @@ int image_add_section(struct image *image, uint32_t base, uint32_t size, int fla /* allocate new section */ image->num_sections++; - image->sections = realloc(image->sections, sizeof(struct imagesection) * image->num_sections); + image->sections = + realloc(image->sections, sizeof(struct imagesection) * image->num_sections); section = &image->sections[image->num_sections - 1]; section->base_address = base; section->size = size; section->flags = flags; section->private = malloc(sizeof(uint8_t) * size); - memcpy((uint8_t*)section->private, data, size); + memcpy((uint8_t *)section->private, data, size); return ERROR_OK; } void image_close(struct image *image) { - if (image->type == IMAGE_BINARY) - { + if (image->type == IMAGE_BINARY) { struct image_binary *image_binary = image->type_private; fileio_close(&image_binary->fileio); - } - else if (image->type == IMAGE_IHEX) - { + } else if (image->type == IMAGE_IHEX) { struct image_ihex *image_ihex = image->type_private; fileio_close(&image_ihex->fileio); - if (image_ihex->buffer) - { + if (image_ihex->buffer) { free(image_ihex->buffer); image_ihex->buffer = NULL; } - } - else if (image->type == IMAGE_ELF) - { + } else if (image->type == IMAGE_ELF) { struct image_elf *image_elf = image->type_private; fileio_close(&image_elf->fileio); - if (image_elf->header) - { + if (image_elf->header) { free(image_elf->header); image_elf->header = NULL; } - if (image_elf->segments) - { + if (image_elf->segments) { free(image_elf->segments); image_elf->segments = NULL; } - } - else if (image->type == IMAGE_MEMORY) - { + } else if (image->type == IMAGE_MEMORY) { struct image_memory *image_memory = image->type_private; - if (image_memory->cache) - { + if (image_memory->cache) { free(image_memory->cache); image_memory->cache = NULL; } - } - else if (image->type == IMAGE_SRECORD) - { + } else if (image->type == IMAGE_SRECORD) { struct image_mot *image_mot = image->type_private; fileio_close(&image_mot->fileio); - if (image_mot->buffer) - { + if (image_mot->buffer) { free(image_mot->buffer); image_mot->buffer = NULL; } - } - else if (image->type == IMAGE_BUILDER) - { + } else if (image->type == IMAGE_BUILDER) { int i; - for (i = 0; i < image->num_sections; i++) - { + for (i = 0; i < image->num_sections; i++) { free(image->sections[i].private); image->sections[i].private = NULL; } } - if (image->type_private) - { + if (image->type_private) { free(image->type_private); image->type_private = NULL; } - if (image->sections) - { + if (image->sections) { free(image->sections); image->sections = NULL; } } -int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, uint32_t* checksum) +int image_calculate_checksum(uint8_t *buffer, uint32_t nbytes, uint32_t *checksum) { uint32_t crc = 0xffffffff; LOG_DEBUG("Calculating checksum"); static uint32_t crc32_table[256]; - static bool first_init = false; - if (!first_init) - { + static bool first_init; + if (!first_init) { /* Initialize the CRC table and the decoding table. */ int i, j; unsigned int c; - for (i = 0; i < 256; i++) - { + for (i = 0; i < 256; i++) { /* as per gdb */ for (c = i << 24, j = 8; j > 0; --j) c = c & 0x80000000 ? (c << 1) ^ 0x04c11db7 : (c << 1); @@ -1138,16 +1023,12 @@ int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, uint32_t* checksu first_init = true; } - while (nbytes > 0) - { + while (nbytes > 0) { int run = nbytes; if (run > 32768) - { run = 32768; - } nbytes -= run; - while (run--) - { + while (run--) { /* as per gdb */ crc = (crc << 8) ^ crc32_table[((crc >> 24) ^ *buffer++) & 255]; } diff --git a/src/target/image.h b/src/target/image.h index 27f3186..19993fa 100644 --- a/src/target/image.h +++ b/src/target/image.h @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef IMAGE_H #define IMAGE_H @@ -37,8 +38,7 @@ #define IMAGE_MEMORY_CACHE_SIZE (2048) -enum image_type -{ +enum image_type { IMAGE_BINARY, /* plain binary */ IMAGE_IHEX, /* intel hex-record format */ IMAGE_MEMORY, /* target-memory pseudo-image */ @@ -47,16 +47,14 @@ enum image_type IMAGE_BUILDER, /* when building a new image */ }; -struct imagesection -{ +struct imagesection { uint32_t base_address; uint32_t size; int flags; void *private; /* private data */ }; -struct image -{ +struct image { enum image_type type; /* image type (plain, ihex, ...) */ void *type_private; /* type private data */ int num_sections; /* number of sections contained in the image */ @@ -67,26 +65,22 @@ struct image uint32_t start_address; /* start address, if one is set */ }; -struct image_binary -{ +struct image_binary { struct fileio fileio; }; -struct image_ihex -{ +struct image_ihex { struct fileio fileio; uint8_t *buffer; }; -struct image_memory -{ +struct image_memory { struct target *target; uint8_t *cache; uint32_t cache_address; }; -struct image_elf -{ +struct image_elf { struct fileio fileio; Elf32_Ehdr *header; Elf32_Phdr *segments; @@ -94,8 +88,7 @@ struct image_elf uint8_t endianness; }; -struct image_mot -{ +struct image_mot { struct fileio fileio; uint8_t *buffer; }; @@ -108,8 +101,8 @@ void image_close(struct image *image); int image_add_section(struct image *image, uint32_t base, uint32_t size, int flags, uint8_t *data); -int image_calculate_checksum(uint8_t* buffer, uint32_t nbytes, - uint32_t* checksum); +int image_calculate_checksum(uint8_t *buffer, uint32_t nbytes, + uint32_t *checksum); #define ERROR_IMAGE_FORMAT_ERROR (-1400) #define ERROR_IMAGE_TYPE_UNKNOWN (-1401) diff --git a/src/target/mips32.c b/src/target/mips32.c index 26e0c5d..5682e3f 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -25,6 +25,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -34,8 +35,7 @@ #include "algorithm.h" #include "register.h" -static char* mips32_core_reg_list[] = -{ +static char *mips32_core_reg_list[] = { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", @@ -43,13 +43,11 @@ static char* mips32_core_reg_list[] = "status", "lo", "hi", "badvaddr", "cause", "pc" }; -static const char *mips_isa_strings[] = -{ +static const char *mips_isa_strings[] = { "MIPS32", "MIPS16e" }; -static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = -{ +static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] = { {0, NULL, NULL}, {1, NULL, NULL}, {2, NULL, NULL}, @@ -94,12 +92,11 @@ static struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] /* number of mips dummy fp regs fp0 - fp31 + fsr and fir * we also add 18 unknown registers to handle gdb requests */ -#define MIPS32NUMFPREGS 34 + 18 +#define MIPS32NUMFPREGS (34 + 18) static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0}; -static struct reg mips32_gdb_dummy_fp_reg = -{ +static struct reg mips32_gdb_dummy_fp_reg = { .name = "GDB dummy floating-point register", .value = mips32_gdb_dummy_fp_value, .dirty = 0, @@ -116,9 +113,7 @@ static int mips32_get_core_reg(struct reg *reg) struct mips32_common *mips32_target = target_to_mips32(target); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } retval = mips32_target->read_core_reg(target, mips32_reg->num); @@ -132,9 +127,7 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf) uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) - { return ERROR_TARGET_NOT_HALTED; - } buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; @@ -188,18 +181,14 @@ int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int /* include floating point registers */ *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS; - *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size)); for (i = 0; i < MIPS32NUMCOREREGS; i++) - { (*reg_list)[i] = &mips32->core_cache->reg_list[i]; - } /* add dummy floating points regs */ for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++) - { (*reg_list)[i] = &mips32_gdb_dummy_fp_reg; - } return ERROR_OK; } @@ -215,12 +204,9 @@ int mips32_save_context(struct target *target) /* read core registers */ mips32_pracc_read_regs(ejtag_info, mips32->core_regs); - for (i = 0; i < MIPS32NUMCOREREGS; i++) - { + for (i = 0; i < MIPS32NUMCOREREGS; i++) { if (!mips32->core_cache->reg_list[i].valid) - { mips32->read_core_reg(target, i); - } } return ERROR_OK; @@ -234,12 +220,9 @@ int mips32_restore_context(struct target *target) struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - for (i = 0; i < MIPS32NUMCOREREGS; i++) - { + for (i = 0; i < MIPS32NUMCOREREGS; i++) { if (mips32->core_cache->reg_list[i].dirty) - { mips32->write_core_reg(target, i); - } } /* write core regs */ @@ -287,8 +270,7 @@ struct reg_cache *mips32_build_reg_cache(struct target *target) (*cache_p) = cache; mips32->core_cache = cache; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { arch_info[i] = mips32_core_reg_list_arch_info[i]; arch_info[i].target = target; arch_info[i].mips32_common = mips32; @@ -329,27 +311,24 @@ static int mips32_run_and_wait(struct target *target, uint32_t entry_point, int retval; /* This code relies on the target specific resume() and poll()->debug_entry() * sequence to write register values to the processor and the read them back */ - if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK) - { + retval = target_resume(target, 0, entry_point, 0, 1); + if (retval != ERROR_OK) return retval; - } retval = target_wait_state(target, TARGET_HALTED, timeout_ms); /* If the target fails to halt due to the breakpoint, force a halt */ - if (retval != ERROR_OK || target->state != TARGET_HALTED) - { - if ((retval = target_halt(target)) != ERROR_OK) + if (retval != ERROR_OK || target->state != TARGET_HALTED) { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) - { + retval = target_wait_state(target, TARGET_HALTED, 500); + if (retval != ERROR_OK) return retval; - } return ERROR_TARGET_TIMEOUT; } pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); - if (exit_point && (pc != exit_point)) - { + if (exit_point && (pc != exit_point)) { LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc); return ERROR_TARGET_TIMEOUT; } @@ -375,47 +354,39 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint * at the exit point */ - if (mips32->common_magic != MIPS32_COMMON_MAGIC) - { + if (mips32->common_magic != MIPS32_COMMON_MAGIC) { LOG_ERROR("current target isn't a MIPS32 target"); return ERROR_TARGET_INVALID; } - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } /* refresh core register cache */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) - { + for (i = 0; i < MIPS32NUMCOREREGS; i++) { if (!mips32->core_cache->reg_list[i].valid) mips32->read_core_reg(target, i); context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); } - for (i = 0; i < num_mem_params; i++) - { - if ((retval = target_write_buffer(target, mem_params[i].address, - mem_params[i].size, mem_params[i].value)) != ERROR_OK) - { + for (i = 0; i < num_mem_params; i++) { + retval = target_write_buffer(target, mem_params[i].address, + mem_params[i].size, mem_params[i].value); + if (retval != ERROR_OK) return retval; - } } - for (i = 0; i < num_reg_params; i++) - { + for (i = 0; i < num_reg_params; i++) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { + if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; @@ -431,31 +402,24 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, if (retval != ERROR_OK) return retval; - for (i = 0; i < num_mem_params; i++) - { - if (mem_params[i].direction != PARAM_OUT) - { - if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, - mem_params[i].value)) != ERROR_OK) - { + for (i = 0; i < num_mem_params; i++) { + if (mem_params[i].direction != PARAM_OUT) { + retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, + mem_params[i].value); + if (retval != ERROR_OK) return retval; - } } } - for (i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { + for (i = 0; i < num_reg_params; i++) { + if (reg_params[i].direction != PARAM_OUT) { struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { + if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; } - if (reg->size != reg_params[i].size) - { + if (reg->size != reg_params[i].size) { LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); return ERROR_COMMAND_SYNTAX_ERROR; @@ -466,12 +430,10 @@ int mips32_run_algorithm(struct target *target, int num_mem_params, } /* restore everything we saved before */ - for (i = 0; i < MIPS32NUMCOREREGS; i++) - { + for (i = 0; i < MIPS32NUMCOREREGS; i++) { uint32_t regvalue; regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32); - if (regvalue != context[i]) - { + if (regvalue != context[i]) { LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, mips32->core_cache->reg_list[i].name, context[i]); buf_set_u32(mips32->core_cache->reg_list[i].value, @@ -490,8 +452,7 @@ int mips32_examine(struct target *target) { struct mips32_common *mips32 = target_to_mips32(target); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { target_set_examined(target); /* we will configure later */ @@ -517,53 +478,50 @@ int mips32_configure_break_unit(struct target *target) return ERROR_OK; /* get info about breakpoint support */ - if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) + retval = target_read_u32(target, EJTAG_DCR, &dcr); + if (retval != ERROR_OK) return retval; - if (dcr & EJTAG_DCR_IB) - { + if (dcr & EJTAG_DCR_IB) { /* get number of inst breakpoints */ - if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK) + retval = target_read_u32(target, EJTAG_IBS, &bpinfo); + if (retval != ERROR_OK) return retval; mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F; mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints; mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator)); for (i = 0; i < mips32->num_inst_bpoints; i++) - { mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i); - } /* clear IBIS reg */ - if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK) + retval = target_write_u32(target, EJTAG_IBS, 0); + if (retval != ERROR_OK) return retval; } - if (dcr & EJTAG_DCR_DB) - { + if (dcr & EJTAG_DCR_DB) { /* get number of data breakpoints */ - if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK) + retval = target_read_u32(target, EJTAG_DBS, &bpinfo); + if (retval != ERROR_OK) return retval; mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F; mips32->num_data_bpoints_avail = mips32->num_data_bpoints; mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator)); for (i = 0; i < mips32->num_data_bpoints; i++) - { mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i); - } /* clear DBIS reg */ - if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK) + retval = target_write_u32(target, EJTAG_DBS, 0); + if (retval != ERROR_OK) return retval; } /* check if target endianness settings matches debug control register */ - if ( ( (dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN) ) || - ( !(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN) ) ) - { + if (((dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_LITTLE_ENDIAN)) || + (!(dcr & EJTAG_DCR_ENM) && (target->endianness == TARGET_BIG_ENDIAN))) LOG_WARNING("DCR endianness settings does not match target settings"); - } LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints); @@ -580,31 +538,27 @@ int mips32_enable_interrupts(struct target *target, int enable) uint32_t dcr; /* read debug control register */ - if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK) + retval = target_read_u32(target, EJTAG_DCR, &dcr); + if (retval != ERROR_OK) return retval; - if (enable) - { - if (!(dcr & EJTAG_DCR_INTE)) - { + if (enable) { + if (!(dcr & EJTAG_DCR_INTE)) { /* enable interrupts */ dcr |= EJTAG_DCR_INTE; update = 1; } - } - else - { - if (dcr & EJTAG_DCR_INTE) - { + } else { + if (dcr & EJTAG_DCR_INTE) { /* disable interrupts */ dcr &= ~EJTAG_DCR_INTE; update = 1; } } - if (update) - { - if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK) + if (update) { + retval = target_write_u32(target, EJTAG_DCR, dcr); + if (retval != ERROR_OK) return retval; } @@ -612,7 +566,7 @@ int mips32_enable_interrupts(struct target *target, int enable) } int mips32_checksum_memory(struct target *target, uint32_t address, - uint32_t count, uint32_t* checksum) + uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; struct reg_param reg_params[2]; @@ -622,9 +576,8 @@ int mips32_checksum_memory(struct target *target, uint32_t address, /* see contib/loaders/checksum/mips32.s for src */ - static const uint32_t mips_crc_code[] = - { - 0x248C0000, /* addiu $t4, $a0, 0 */ + static const uint32_t mips_crc_code[] = { + 0x248C0000, /* addiu $t4, $a0, 0 */ 0x24AA0000, /* addiu $t2, $a1, 0 */ 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */ 0x10000010, /* beq $zero, $zero, ncomp */ @@ -654,9 +607,7 @@ int mips32_checksum_memory(struct target *target, uint32_t address, /* make sure we have a working area */ if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK) - { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++) @@ -673,10 +624,10 @@ int mips32_checksum_memory(struct target *target, uint32_t address, int timeout = 20000 * (1 + (count / (1024 * 1024))); - if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, + retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), timeout, - &mips32_info)) != ERROR_OK) - { + &mips32_info); + if (retval != ERROR_OK) { destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); target_free_working_area(target, crc_algorithm); @@ -695,7 +646,7 @@ int mips32_checksum_memory(struct target *target, uint32_t address, /** Checks whether a memory region is zeroed. */ int mips32_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* blank) + uint32_t address, uint32_t count, uint32_t *blank) { struct working_area *erase_check_algorithm; struct reg_param reg_params[3]; @@ -703,8 +654,7 @@ int mips32_blank_check_memory(struct target *target, int retval; uint32_t i; - static const uint32_t erase_check_code[] = - { + static const uint32_t erase_check_code[] = { /* nbyte: */ 0x80880000, /* lb $t0, ($a0) */ 0x00C83024, /* and $a2, $a2, $t0 */ @@ -716,13 +666,10 @@ int mips32_blank_check_memory(struct target *target, /* make sure we have a working area */ if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) - { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) - { + for (i = 0; i < ARRAY_SIZE(erase_check_code); i++) { target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i]); } @@ -739,11 +686,11 @@ int mips32_blank_check_memory(struct target *target, init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT); buf_set_u32(reg_params[2].value, 0, 32, 0xff); - if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, + retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), - 10000, &mips32_info)) != ERROR_OK) - { + 10000, &mips32_info); + if (retval != ERROR_OK) { destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); destroy_reg_param(®_params[2]); @@ -788,48 +735,40 @@ COMMAND_HANDLER(mips32_handle_cp0_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* two or more argument, access a single register/select (write if third argument is given) */ if (CMD_ARGC < 2) - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - else - { + return ERROR_COMMAND_SYNTAX_ERROR; + else { uint32_t cp0_reg, cp0_sel; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); - if (CMD_ARGC == 2) - { + if (CMD_ARGC == 2) { uint32_t value; - if ((retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel)) != ERROR_OK) - { + retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %" PRIi32, cp0_reg); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, cp0_reg, cp0_sel, value); - } - else if (CMD_ARGC == 3) - { + } else if (CMD_ARGC == 3) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); - if ((retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel)) != ERROR_OK) - { + retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32, cp0_reg, cp0_sel); @@ -864,4 +803,3 @@ const struct command_registration mips32_command_handlers[] = { }, COMMAND_REGISTRATION_DONE }; - diff --git a/src/target/mips32.h b/src/target/mips32.h index 5d5aa46..a5bccdc 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -64,27 +64,23 @@ #define MIPS32_ARCH_REL2 0x1 /* offsets into mips32 core register cache */ -enum -{ +enum { MIPS32_PC = 37, MIPS32NUMCOREREGS }; -enum mips32_isa_mode -{ +enum mips32_isa_mode { MIPS32_ISA_MIPS32 = 0, MIPS32_ISA_MIPS16E = 1, }; -struct mips32_comparator -{ +struct mips32_comparator { int used; uint32_t bp_value; uint32_t reg_address; }; -struct mips32_common -{ +struct mips32_common { uint32_t common_magic; void *arch_info; struct reg_cache *core_cache; @@ -114,15 +110,13 @@ target_to_mips32(struct target *target) return target->arch_info; } -struct mips32_core_reg -{ +struct mips32_core_reg { uint32_t num; struct target *target; struct mips32_common *mips32_common; }; -struct mips32_algorithm -{ +struct mips32_algorithm { int common_magic; enum mips32_isa_mode isa_mode; }; @@ -164,9 +158,11 @@ struct mips32_algorithm #define MIPS32_COP0_MF 0x00 #define MIPS32_COP0_MT 0x04 -#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct)) -#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd)) -#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr)) +#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \ + (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct)) +#define MIPS32_I_INST(opcode, rs, rt, immd) \ + (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd)) +#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr)) #define MIPS32_NOP 0 #define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val) @@ -176,7 +172,7 @@ struct mips32_algorithm #define MIPS32_B(off) MIPS32_BEQ(0, 0, off) #define MIPS32_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off) #define MIPS32_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off) -#define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) +#define MIPS32_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off) #define MIPS32_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off) #define MIPS32_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR) #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel) @@ -245,8 +241,8 @@ int mips32_register_commands(struct command_context *cmd_ctx); int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size); int mips32_checksum_memory(struct target *target, uint32_t address, - uint32_t count, uint32_t* checksum); + uint32_t count, uint32_t *checksum); int mips32_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t* blank); + uint32_t address, uint32_t count, uint32_t *blank); #endif /*MIPS32_H*/ diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index 19a2f64..42979d7 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -22,6 +22,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -84,13 +85,11 @@ begin_ejtag_dma_read: mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read; - } - else + } else LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -113,7 +112,8 @@ begin_ejtag_dma_read_h: /* Initiate DMA Read & set DSTRT */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); - ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; + ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | + EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ @@ -130,13 +130,11 @@ begin_ejtag_dma_read_h: mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read_h; - } - else + } else LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -182,13 +180,11 @@ begin_ejtag_dma_read_b: mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr); goto begin_ejtag_dma_read_b; - } - else + } else LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -245,13 +241,11 @@ begin_ejtag_dma_write: mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write; - } - else + } else LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -296,13 +290,11 @@ begin_ejtag_dma_write_h: mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write_h; - } - else + } else LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -348,13 +340,11 @@ begin_ejtag_dma_write_b: mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_ctrl & EJTAG_CTRL_DERR) - { + if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr); goto begin_ejtag_dma_write_b; - } - else + } else LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr); return ERROR_JTAG_DEVICE_ERROR; } @@ -364,14 +354,13 @@ begin_ejtag_dma_write_b: int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { - switch (size) - { + switch (size) { case 1: - return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf); + return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); case 2: - return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf); + return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); case 4: - return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf); + return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); } return ERROR_OK; @@ -383,7 +372,8 @@ static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_read(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK) + retval = ejtag_dma_read(ejtag_info, addr + i * sizeof(*buf), &buf[i]); + if (retval != ERROR_OK) return retval; } @@ -396,7 +386,8 @@ static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_read_h(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK) + retval = ejtag_dma_read_h(ejtag_info, addr + i * sizeof(*buf), &buf[i]); + if (retval != ERROR_OK) return retval; } @@ -409,7 +400,8 @@ static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_read_b(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK) + retval = ejtag_dma_read_b(ejtag_info, addr + i * sizeof(*buf), &buf[i]); + if (retval != ERROR_OK) return retval; } @@ -418,14 +410,13 @@ static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { - switch (size) - { + switch (size) { case 1: - return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); + return mips32_dmaacc_write_mem8(ejtag_info, addr, count, (uint8_t *)buf); case 2: - return mips32_dmaacc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); + return mips32_dmaacc_write_mem16(ejtag_info, addr, count, (uint16_t *)buf); case 4: - return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); + return mips32_dmaacc_write_mem32(ejtag_info, addr, count, (uint32_t *)buf); } return ERROR_OK; @@ -437,7 +428,8 @@ static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t add int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_write(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK) + retval = ejtag_dma_write(ejtag_info, addr + i * sizeof(*buf), buf[i]); + if (retval != ERROR_OK) return retval; } @@ -450,7 +442,8 @@ static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t add int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_write_h(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK) + retval = ejtag_dma_write_h(ejtag_info, addr + i * sizeof(*buf), buf[i]); + if (retval != ERROR_OK) return retval; } @@ -463,7 +456,8 @@ static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr int retval; for (i = 0; i < count; i++) { - if ((retval = ejtag_dma_write_b(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK) + retval = ejtag_dma_write_b(ejtag_info, addr + i * sizeof(*buf), buf[i]); + if (retval != ERROR_OK) return retval; } diff --git a/src/target/mips32_dmaacc.h b/src/target/mips32_dmaacc.h index fdf8cae..ecb2674 100644 --- a/src/target/mips32_dmaacc.h +++ b/src/target/mips32_dmaacc.h @@ -22,6 +22,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef MIPS32_DMAACC_H #define MIPS32_DMAACC_H diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index 7160f8e..267a4ff 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -26,52 +26,51 @@ ***************************************************************************/ /* -This version has optimized assembly routines for 32 bit operations: -- read word -- write word -- write array of words - -One thing to be aware of is that the MIPS32 cpu will execute the -instruction after a branch instruction (one delay slot). - -For example: - - LW $2, ($5 +10) - B foo - LW $1, ($2 +100) - -The LW $1, ($2 +100) instruction is also executed. If this is -not wanted a NOP can be inserted: - - LW $2, ($5 +10) - B foo - NOP - LW $1, ($2 +100) - -or the code can be changed to: - - B foo - LW $2, ($5 +10) - LW $1, ($2 +100) - -The original code contained NOPs. I have removed these and moved -the branches. - -I also moved the PRACC_STACK to 0xFF204000. This allows -the use of 16 bits offsets to get pointers to the input -and output area relative to the stack. Note that the stack -isn't really a stack (the stack pointer is not 'moving') -but a FIFO simulated in software. - -These changes result in a 35% speed increase when programming an -external flash. - -More improvement could be gained if the registers do no need -to be preserved but in that case the routines should be aware -OpenOCD is used as a flash programmer or as a debug tool. - -Nico Coesel -*/ + * This version has optimized assembly routines for 32 bit operations: + * - read word + * - write word + * - write array of words + * + * One thing to be aware of is that the MIPS32 cpu will execute the + * instruction after a branch instruction (one delay slot). + * + * For example: + * LW $2, ($5 +10) + * B foo + * LW $1, ($2 +100) + * + * The LW $1, ($2 +100) instruction is also executed. If this is + * not wanted a NOP can be inserted: + * + * LW $2, ($5 +10) + * B foo + * NOP + * LW $1, ($2 +100) + * + * or the code can be changed to: + * + * B foo + * LW $2, ($5 +10) + * LW $1, ($2 +100) + * + * The original code contained NOPs. I have removed these and moved + * the branches. + * + * I also moved the PRACC_STACK to 0xFF204000. This allows + * the use of 16 bits offsets to get pointers to the input + * and output area relative to the stack. Note that the stack + * isn't really a stack (the stack pointer is not 'moving') + * but a FIFO simulated in software. + * + * These changes result in a 35% speed increase when programming an + * external flash. + * + * More improvement could be gained if the registers do no need + * to be preserved but in that case the routines should be aware + * OpenOCD is used as a flash programmer or as a debug tool. + * + * Nico Coesel + */ #ifdef HAVE_CONFIG_H #include "config.h" @@ -82,8 +81,7 @@ Nico Coesel #include "mips32.h" #include "mips32_pracc.h" -struct mips32_pracc_context -{ +struct mips32_pracc_context { uint32_t *local_iparam; int num_iparam; uint32_t *local_oparam; @@ -116,7 +114,7 @@ static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, uint32_t start_addr, uint32_t end_addr); static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, - uint32_t start_addr, uint32_t end_addr); + uint32_t start_addr, uint32_t end_addr); static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { @@ -129,8 +127,7 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; - while (1) - { + while (1) { retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); if (retval != ERROR_OK) return retval; @@ -138,8 +135,8 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; - if ( (timeout = timeval_ms()-then) > 1000 ) - { + timeout = timeval_ms() - then; + if (timeout > 1000) { LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); return ERROR_JTAG_DEVICE_ERROR; } @@ -156,30 +153,21 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add uint32_t ejtag_ctrl, data; if ((address >= MIPS32_PRACC_PARAM_IN) - && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) - { + && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_IN) / 4; data = ctx->local_iparam[offset]; - } - else if ((address >= MIPS32_PRACC_PARAM_OUT) - && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) - { + } else if ((address >= MIPS32_PRACC_PARAM_OUT) + && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_OUT) / 4; data = ctx->local_oparam[offset]; - } - else if ((address >= MIPS32_PRACC_TEXT) - && (address <= MIPS32_PRACC_TEXT + ctx->code_len * 4)) - { + } else if ((address >= MIPS32_PRACC_TEXT) + && (address <= MIPS32_PRACC_TEXT + ctx->code_len * 4)) { offset = (address - MIPS32_PRACC_TEXT) / 4; data = ctx->code[offset]; - } - else if (address == MIPS32_PRACC_STACK) - { + } else if (address == MIPS32_PRACC_STACK) { /* save to our debug stack */ data = ctx->stack[--ctx->stack_offset]; - } - else - { + } else { /* TODO: send JMP 0xFF200000 instruction. Hopefully processor jump back * to start of debug vector */ @@ -201,7 +189,7 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t address) { - uint32_t ejtag_ctrl,data; + uint32_t ejtag_ctrl, data; int offset; struct mips_ejtag *ejtag_info = ctx->ejtag_info; int retval; @@ -221,24 +209,17 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad return retval; if ((address >= MIPS32_PRACC_PARAM_IN) - && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) - { + && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_IN) / 4; ctx->local_iparam[offset] = data; - } - else if ((address >= MIPS32_PRACC_PARAM_OUT) - && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) - { + } else if ((address >= MIPS32_PRACC_PARAM_OUT) + && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_OUT) / 4; ctx->local_oparam[offset] = data; - } - else if (address == MIPS32_PRACC_STACK) - { + } else if (address == MIPS32_PRACC_STACK) { /* save data onto our stack */ ctx->stack[ctx->stack_offset++] = data; - } - else - { + } else { LOG_ERROR("Error writing unexpected address 0x%8.8" PRIx32 "", address); return ERROR_JTAG_DEVICE_ERROR; } @@ -264,9 +245,9 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ ctx.ejtag_info = ejtag_info; ctx.stack_offset = 0; - while (1) - { - if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + while (1) { + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) return retval; address = data = 0; @@ -276,22 +257,19 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ return retval; /* Check for read or write */ - if (ejtag_ctrl & EJTAG_CTRL_PRNW) - { - if ((retval = mips32_pracc_exec_write(&ctx, address)) != ERROR_OK) + if (ejtag_ctrl & EJTAG_CTRL_PRNW) { + retval = mips32_pracc_exec_write(&ctx, address); + if (retval != ERROR_OK) return retval; - } - else - { + } else { /* Check to see if its reading at the debug vector. The first pass through * the module is always read at the vector, so the first one we allow. When * the second read from the vector occurs we are done and just exit. */ if ((address == MIPS32_PRACC_TEXT) && (pass++)) - { break; - } - if ((retval = mips32_pracc_exec_read(&ctx, address)) != ERROR_OK) + retval = mips32_pracc_exec_read(&ctx, address); + if (retval != ERROR_OK) return retval; } @@ -301,26 +279,23 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ /* stack sanity check */ if (ctx.stack_offset != 0) - { LOG_DEBUG("Pracc Stack not zero"); - } return ERROR_OK; } int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { - switch (size) - { + switch (size) { case 1: - return mips32_pracc_read_mem8(ejtag_info, addr, count, (uint8_t*)buf); + return mips32_pracc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); case 2: - return mips32_pracc_read_mem16(ejtag_info, addr, count, (uint16_t*)buf); + return mips32_pracc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); case 4: if (count == 1) - return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t*)buf); + return mips32_pracc_read_u32(ejtag_info, addr, (uint32_t *)buf); else - return mips32_pracc_read_mem32(ejtag_info, addr, count, (uint32_t*)buf); + return mips32_pracc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); } return ERROR_OK; @@ -330,40 +305,40 @@ static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* $9 = mem[$8]; read addr */ - MIPS32_LW(10,4,8), /* $10 = mem[$8 + 4]; read count */ - MIPS32_LUI(11,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(11,11,LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* $9 = mem[$8]; read addr */ + MIPS32_LW(10, 4, 8), /* $10 = mem[$8 + 4]; read count */ + MIPS32_LUI(11, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(11, 11, LOWER16(MIPS32_PRACC_PARAM_OUT)), /* loop: */ - MIPS32_BEQ(0,10,8), /* beq 0, $10, end */ + MIPS32_BEQ(0, 10, 8), /* beq 0, $10, end */ MIPS32_NOP, - MIPS32_LW(8,0,9), /* lw $8,0($9), Load $8 with the word @mem[$9] */ - MIPS32_SW(8,0,11), /* sw $8,0($11) */ + MIPS32_LW(8, 0, 9), /* lw $8,0($9), Load $8 with the word @mem[$9] */ + MIPS32_SW(8, 0, 11), /* sw $8,0($11) */ - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,4), /* $1 += 4 */ - MIPS32_ADDI(11,11,4), /* $11 += 4 */ + MIPS32_ADDI(10, 10, NEG16(1)), /* $10-- */ + MIPS32_ADDI(9, 9, 4), /* $1 += 4 */ + MIPS32_ADDI(11, 11, 4), /* $11 += 4 */ MIPS32_B(NEG16(8)), /* b loop */ MIPS32_NOP, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(27)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; int retval = ERROR_OK; @@ -373,8 +348,7 @@ static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, bytesread = 0; - while (count > 0) - { + while (count > 0) { blocksize = count; if (count > 0x400) blocksize = 0x400; @@ -382,11 +356,10 @@ static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, param_in[0] = addr; param_in[1] = blocksize; - if ((retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, - ARRAY_SIZE(param_in), param_in, blocksize, &buf[bytesread], 1)) != ERROR_OK) - { + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, + ARRAY_SIZE(param_in), param_in, blocksize, &buf[bytesread], 1); + if (retval != ERROR_OK) return retval; - } count -= blocksize; addr += blocksize; @@ -400,19 +373,19 @@ static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, u { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ - MIPS32_LW(8,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN),15), /* load R8 @ param_in[0] = address */ + MIPS32_LW(8, NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN), 15), /* load R8 @ param_in[0] = address */ - MIPS32_LW(8,0,8), /* lw $8,0($8), Load $8 with the word @mem[$8] */ - MIPS32_SW(8,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_OUT),15), /* store R8 @ param_out[0] */ + MIPS32_LW(8, 0, 8), /* lw $8,0($8), Load $8 with the word @mem[$8] */ + MIPS32_SW(8, NEG16(MIPS32_PRACC_STACK - MIPS32_PRACC_PARAM_OUT), 15), /* store R8 @ param_out[0] */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(9)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; int retval = ERROR_OK; @@ -420,11 +393,10 @@ static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, u param_in[0] = addr; - if ((retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, - ARRAY_SIZE(param_in), param_in, 1, buf, 1)) != ERROR_OK) - { + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, + ARRAY_SIZE(param_in), param_in, 1, buf, 1); + if (retval != ERROR_OK) return retval; - } return retval; } @@ -433,39 +405,39 @@ static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* $9 = mem[$8]; read addr */ - MIPS32_LW(10,4,8), /* $10 = mem[$8 + 4]; read count */ - MIPS32_LUI(11,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(11,11,LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* $9 = mem[$8]; read addr */ + MIPS32_LW(10, 4, 8), /* $10 = mem[$8 + 4]; read count */ + MIPS32_LUI(11, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(11, 11, LOWER16(MIPS32_PRACC_PARAM_OUT)), /* loop: */ - MIPS32_BEQ(0,10,8), /* beq 0, $10, end */ + MIPS32_BEQ(0, 10, 8), /* beq 0, $10, end */ MIPS32_NOP, - MIPS32_LHU(8,0,9), /* lw $8,0($9), Load $8 with the halfword @mem[$9] */ - MIPS32_SW(8,0,11), /* sw $8,0($11) */ + MIPS32_LHU(8, 0, 9), /* lw $8,0($9), Load $8 with the halfword @mem[$9] */ + MIPS32_SW(8, 0, 11), /* sw $8,0($11) */ - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,2), /* $9 += 2 */ - MIPS32_ADDI(11,11,4), /* $11 += 4 */ + MIPS32_ADDI(10, 10, NEG16(1)), /* $10-- */ + MIPS32_ADDI(9, 9, 2), /* $9 += 2 */ + MIPS32_ADDI(11, 11, 4), /* $11 += 4 */ MIPS32_B(NEG16(8)), /* b loop */ MIPS32_NOP, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(27)), /* b start */ - MIPS32_MFC0(15,30,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 30, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -476,7 +448,7 @@ static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int blocksize; uint32_t param_in[2]; - //while (count > 0) + /*while (count > 0) */ { blocksize = count; if (count > 0x400) @@ -488,14 +460,12 @@ static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, ARRAY_SIZE(param_in), param_in, count, param_out, 1); -// count -= blocksize; -// addr += blocksize; +/* count -= blocksize; */ +/* addr += blocksize; */ } for (i = 0; i < count; i++) - { buf[i] = param_out[i]; - } free(param_out); @@ -506,39 +476,39 @@ static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* $9 = mem[$8]; read addr */ - MIPS32_LW(10,4,8), /* $10 = mem[$8 + 4]; read count */ - MIPS32_LUI(11,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(11,11,LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* $9 = mem[$8]; read addr */ + MIPS32_LW(10, 4, 8), /* $10 = mem[$8 + 4]; read count */ + MIPS32_LUI(11, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(11, 11, LOWER16(MIPS32_PRACC_PARAM_OUT)), /* loop: */ - MIPS32_BEQ(0,10,8), /* beq 0, $10, end */ + MIPS32_BEQ(0, 10, 8), /* beq 0, $10, end */ MIPS32_NOP, - MIPS32_LBU(8,0,9), /* lw $8,0($9), Load t4 with the byte @mem[t1] */ - MIPS32_SW(8,0,11), /* sw $8,0($11) */ + MIPS32_LBU(8, 0, 9), /* lw $8,0($9), Load t4 with the byte @mem[t1] */ + MIPS32_SW(8, 0, 11), /* sw $8,0($11) */ - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,1), /* $9 += 1 */ - MIPS32_ADDI(11,11,4), /* $11 += 4 */ + MIPS32_ADDI(10, 10, NEG16(1)), /* $10-- */ + MIPS32_ADDI(9, 9, 1), /* $9 += 1 */ + MIPS32_ADDI(11, 11, 4), /* $11 += 4 */ MIPS32_B(NEG16(8)), /* b loop */ MIPS32_NOP, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(27)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -549,7 +519,7 @@ static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int blocksize; uint32_t param_in[2]; -// while (count > 0) +/* while (count > 0) */ { blocksize = count; if (count > 0x400) @@ -561,14 +531,12 @@ static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, ARRAY_SIZE(param_in), param_in, count, param_out, 1); -// count -= blocksize; -// addr += blocksize; +/* count -= blocksize; */ +/* addr += blocksize; */ } for (i = 0; i < count; i++) - { buf[i] = param_out[i]; - } free(param_out); @@ -583,22 +551,22 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r */ uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ - /* 5 */ MIPS32_MFC0(8,0,0), /* move COP0 [cp0_reg select] to $8 */ + /* 5 */ MIPS32_MFC0(8, 0, 0), /* move COP0 [cp0_reg select] to $8 */ - MIPS32_LUI(9,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(9,9,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_SW(8,0,9), /* sw $8,0($9) */ + MIPS32_LUI(9, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(9, 9, LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_SW(8, 0, 9), /* sw $8,0($9) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(12)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /** @@ -627,26 +595,26 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_r } int mips32_cp0_write(struct mips_ejtag *ejtag_info, - uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel) + uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel) { uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write val to $9 */ + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* Load write val to $9 */ - /* 8 */ MIPS32_MTC0(9,0,0), /* move $9 to COP0 [cp0_reg select] */ + /* 8 */ MIPS32_MTC0(9, 0, 0), /* move $9 to COP0 [cp0_reg select] */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(12)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /** @@ -697,39 +665,39 @@ int mips32_cp0_write(struct mips_ejtag *ejtag_info, * from one of the standard “hardware registers”. */ static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, - uint32_t start_addr, uint32_t end_addr) + uint32_t start_addr, uint32_t end_addr) { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write start_addr to $9 */ - MIPS32_LW(10,4,8), /* Load write end_addr to $10 */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */ + MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */ MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */ - MIPS32_BEQ(11,0,6), /* beq $11, $0, end */ + MIPS32_BEQ(11, 0, 6), /* beq $11, $0, end */ MIPS32_NOP, /* synci_loop : */ - MIPS32_SYNCI(0,9), /* synci 0($9) */ - MIPS32_SLTU(8,10,9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */ - MIPS32_BNE(8,0,NEG16(3)), /* bne $8, $0, synci_loop */ + MIPS32_SYNCI(0, 9), /* synci 0($9) */ + MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */ + MIPS32_BNE(8, 0, NEG16(3)), /* bne $8, $0, synci_loop */ MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */ MIPS32_SYNC, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(24)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -756,39 +724,39 @@ static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write start_addr to $9 */ - MIPS32_LW(10,4,8), /* Load write end_addr to $10 */ - MIPS32_LW(11,8,8), /* Load write clsiz to $11 */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* Load write start_addr to $9 */ + MIPS32_LW(10, 4, 8), /* Load write end_addr to $10 */ + MIPS32_LW(11, 8, 8), /* Load write clsiz to $11 */ /* cache_loop: */ - MIPS32_SLTU(8,10,9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */ - MIPS32_BGTZ(8,6), /* bgtz $8, end */ + MIPS32_SLTU(8, 10, 9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */ + MIPS32_BGTZ(8, 6), /* bgtz $8, end */ MIPS32_NOP, - MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK,0,9), /* cache Hit_Writeback_D, 0($9) */ - MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE,0,9), /* cache Hit_Invalidate_I, 0($9) */ + MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK, 0, 9), /* cache Hit_Writeback_D, 0($9) */ + MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE, 0, 9), /* cache Hit_Invalidate_I, 0($9) */ - MIPS32_ADDU(9,9,11), /* $9 += $11 */ + MIPS32_ADDU(9, 9, 11), /* $9 += $11 */ MIPS32_B(NEG16(7)), /* b cache_loop */ MIPS32_NOP, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(25)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /** @@ -822,23 +790,18 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz { int retval; - switch (size) - { + switch (size) { case 1: - retval = mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); + retval = mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t *)buf); break; case 2: - retval = mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); + retval = mips32_pracc_write_mem16(ejtag_info, addr, count, (uint16_t *)buf); break; case 4: if (count == 1) - { - retval = mips32_pracc_write_u32(ejtag_info, addr, (uint32_t*)buf); - } + retval = mips32_pracc_write_u32(ejtag_info, addr, (uint32_t *)buf); else - { - retval = mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); - } + retval = mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t *)buf); break; default: retval = ERROR_FAIL; @@ -855,12 +818,11 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz mips32_cp0_read(ejtag_info, &conf, 16, 0); - switch (KSEGX(addr)) - { + switch (KSEGX(addr)) { case KUSEG: cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; break; - case KSEG0 : + case KSEG0: cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; break; case KSEG1: @@ -880,8 +842,7 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz * is the region cacheable or uncached. * If cacheable we have to synchronize the cache */ - if (cached == 0x3) - { + if (cached == 0x3) { uint32_t start_addr, end_addr; uint32_t rel; @@ -890,17 +851,16 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz /** select cache synchronisation mechanism based on Architecture Release */ rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; - switch (rel) - { - case MIPS32_ARCH_REL1 : + switch (rel) { + case MIPS32_ARCH_REL1: /* MIPS32/64 Release 1 - we must use cache instruction */ mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr); break; - case MIPS32_ARCH_REL2 : + case MIPS32_ARCH_REL2: /* MIPS32/64 Release 2 - we can use synci instruction */ mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr); break; - default : + default: /* what ? */ break; } @@ -913,34 +873,34 @@ static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_ADDI(8,15,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)), /* $8= MIPS32_PRACC_PARAM_IN */ - MIPS32_LW(9,0,8), /* Load write addr to $9 */ - MIPS32_LW(10,4,8), /* Load write count to $10 */ - MIPS32_ADDI(8,8,8), /* $8 += 8 beginning of data */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_ADDI(8, 15, NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)), /* $8= MIPS32_PRACC_PARAM_IN */ + MIPS32_LW(9, 0, 8), /* Load write addr to $9 */ + MIPS32_LW(10, 4, 8), /* Load write count to $10 */ + MIPS32_ADDI(8, 8, 8), /* $8 += 8 beginning of data */ /* loop: */ - MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ - MIPS32_SW(11,0,9), /* sw $11,0($9) */ + MIPS32_LW(11, 0, 8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ + MIPS32_SW(11, 0, 9), /* sw $11,0($9) */ - MIPS32_ADDI(9,9,4), /* $9 += 4 */ - MIPS32_BNE(10,9,NEG16(4)), /* bne $10, $9, loop */ - MIPS32_ADDI(8,8,4), /* $8 += 4 */ + MIPS32_ADDI(9, 9, 4), /* $9 += 4 */ + MIPS32_BNE(10, 9, NEG16(4)), /* bne $10, $9, loop */ + MIPS32_ADDI(8, 8, 4), /* $8 += 4 */ /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(21)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -963,21 +923,21 @@ static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ - MIPS32_LW(8,NEG16((MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)-4), 15), /* load R8 @ param_in[1] = data */ - MIPS32_LW(9,NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN), 15), /* load R9 @ param_in[0] = address */ + MIPS32_LW(8, NEG16((MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN)-4), 15), /* load R8 @ param_in[1] = data */ + MIPS32_LW(9, NEG16(MIPS32_PRACC_STACK-MIPS32_PRACC_PARAM_IN), 15), /* load R9 @ param_in[0] = address */ - MIPS32_SW(8,0,9), /* sw $8,0($9) */ + MIPS32_SW(8, 0, 9), /* sw $8,0($9) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(11)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -993,39 +953,39 @@ static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write addr to $9 */ - MIPS32_LW(10,4,8), /* Load write count to $10 */ - MIPS32_ADDI(8,8,8), /* $8 += 8 */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* Load write addr to $9 */ + MIPS32_LW(10, 4, 8), /* Load write count to $10 */ + MIPS32_ADDI(8, 8, 8), /* $8 += 8 */ /* loop: */ - MIPS32_BEQ(0,10,8), /* beq $0, $10, end */ + MIPS32_BEQ(0, 10, 8), /* beq $0, $10, end */ MIPS32_NOP, - MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ - MIPS32_SH(11,0,9), /* sh $11,0($9) */ + MIPS32_LW(11, 0, 8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ + MIPS32_SH(11, 0, 9), /* sh $11,0($9) */ - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,2), /* $9 += 2 */ - MIPS32_ADDI(8,8,4), /* $8 += 4 */ + MIPS32_ADDI(10, 10, NEG16(1)), /* $10-- */ + MIPS32_ADDI(9, 9, 2), /* $9 += 2 */ + MIPS32_ADDI(8, 8, 4), /* $8 += 4 */ MIPS32_B(NEG16(8)), /* b loop */ MIPS32_NOP, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(26)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -1035,9 +995,7 @@ static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr param_in[1] = count; for (i = 0; i < count; i++) - { param_in[i + 2] = buf[i]; - } int retval; retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, @@ -1052,39 +1010,39 @@ static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(8,0,15), /* sw $8,($15) */ - MIPS32_SW(9,0,15), /* sw $9,($15) */ - MIPS32_SW(10,0,15), /* sw $10,($15) */ - MIPS32_SW(11,0,15), /* sw $11,($15) */ - - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(9,0,8), /* Load write addr to $9 */ - MIPS32_LW(10,4,8), /* Load write count to $10 */ - MIPS32_ADDI(8,8,8), /* $8 += 8 */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8, 0, 15), /* sw $8,($15) */ + MIPS32_SW(9, 0, 15), /* sw $9,($15) */ + MIPS32_SW(10, 0, 15), /* sw $10,($15) */ + MIPS32_SW(11, 0, 15), /* sw $11,($15) */ + + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9, 0, 8), /* Load write addr to $9 */ + MIPS32_LW(10, 4, 8), /* Load write count to $10 */ + MIPS32_ADDI(8, 8, 8), /* $8 += 8 */ /* loop: */ - MIPS32_BEQ(0,10,8), /* beq $0, $10, end */ + MIPS32_BEQ(0, 10, 8), /* beq $0, $10, end */ MIPS32_NOP, - MIPS32_LW(11,0,8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ - MIPS32_SB(11,0,9), /* sb $11,0($9) */ + MIPS32_LW(11, 0, 8), /* lw $11,0($8), Load $11 with the word @mem[$8] */ + MIPS32_SB(11, 0, 9), /* sb $11,0($9) */ - MIPS32_ADDI(10,10,NEG16(1)), /* $10-- */ - MIPS32_ADDI(9,9,1), /* $9 += 1 */ - MIPS32_ADDI(8,8,4), /* $8 += 4 */ + MIPS32_ADDI(10, 10, NEG16(1)), /* $10-- */ + MIPS32_ADDI(9, 9, 1), /* $9 += 1 */ + MIPS32_ADDI(8, 8, 4), /* $8 += 4 */ MIPS32_B(NEG16(8)), /* b loop */ MIPS32_NOP, /* end: */ - MIPS32_LW(11,0,15), /* lw $11,($15) */ - MIPS32_LW(10,0,15), /* lw $10,($15) */ - MIPS32_LW(9,0,15), /* lw $9,($15) */ - MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_LW(11, 0, 15), /* lw $11,($15) */ + MIPS32_LW(10, 0, 15), /* lw $10,($15) */ + MIPS32_LW(9, 0, 15), /* lw $9,($15) */ + MIPS32_LW(8, 0, 15), /* lw $8,($15) */ MIPS32_B(NEG16(26)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; /* TODO remove array */ @@ -1095,9 +1053,7 @@ static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, param_in[1] = count; for (i = 0; i < count; i++) - { param_in[i + 2] = buf[i]; - } retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, count + 2, param_in, 0, NULL, 1); @@ -1111,62 +1067,62 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) { static const uint32_t code[] = { /* start: */ - MIPS32_LUI(2,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $2 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(2,2,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(1,1*4,2), /* lw $1,1*4($2) */ - MIPS32_LW(15,15*4,2), /* lw $15,15*4($2) */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1,0,15), /* sw $1,($15) */ - MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $1 = MIPS32_PRACC_PARAM_IN */ - MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_IN)), - MIPS32_LW(3,3*4,1), /* lw $3,3*4($1) */ - MIPS32_LW(4,4*4,1), /* lw $4,4*4($1) */ - MIPS32_LW(5,5*4,1), /* lw $5,5*4($1) */ - MIPS32_LW(6,6*4,1), /* lw $6,6*4($1) */ - MIPS32_LW(7,7*4,1), /* lw $7,7*4($1) */ - MIPS32_LW(8,8*4,1), /* lw $8,8*4($1) */ - MIPS32_LW(9,9*4,1), /* lw $9,9*4($1) */ - MIPS32_LW(10,10*4,1), /* lw $10,10*4($1) */ - MIPS32_LW(11,11*4,1), /* lw $11,11*4($1) */ - MIPS32_LW(12,12*4,1), /* lw $12,12*4($1) */ - MIPS32_LW(13,13*4,1), /* lw $13,13*4($1) */ - MIPS32_LW(14,14*4,1), /* lw $14,14*4($1) */ - MIPS32_LW(16,16*4,1), /* lw $16,16*4($1) */ - MIPS32_LW(17,17*4,1), /* lw $17,17*4($1) */ - MIPS32_LW(18,18*4,1), /* lw $18,18*4($1) */ - MIPS32_LW(19,19*4,1), /* lw $19,19*4($1) */ - MIPS32_LW(20,20*4,1), /* lw $20,20*4($1) */ - MIPS32_LW(21,21*4,1), /* lw $21,21*4($1) */ - MIPS32_LW(22,22*4,1), /* lw $22,22*4($1) */ - MIPS32_LW(23,23*4,1), /* lw $23,23*4($1) */ - MIPS32_LW(24,24*4,1), /* lw $24,24*4($1) */ - MIPS32_LW(25,25*4,1), /* lw $25,25*4($1) */ - MIPS32_LW(26,26*4,1), /* lw $26,26*4($1) */ - MIPS32_LW(27,27*4,1), /* lw $27,27*4($1) */ - MIPS32_LW(28,28*4,1), /* lw $28,28*4($1) */ - MIPS32_LW(29,29*4,1), /* lw $29,29*4($1) */ - MIPS32_LW(30,30*4,1), /* lw $30,30*4($1) */ - MIPS32_LW(31,31*4,1), /* lw $31,31*4($1) */ - - MIPS32_LW(2,32*4,1), /* lw $2,32*4($1) */ - MIPS32_MTC0(2,12,0), /* move $2 to status */ - MIPS32_LW(2,33*4,1), /* lw $2,33*4($1) */ + MIPS32_LUI(2, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $2 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(2, 2, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(1, 1*4, 2), /* lw $1,1*4($2) */ + MIPS32_LW(15, 15*4, 2), /* lw $15,15*4($2) */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(1, 0, 15), /* sw $1,($15) */ + MIPS32_LUI(1, UPPER16(MIPS32_PRACC_PARAM_IN)), /* $1 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(1, 1, LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(3, 3*4, 1), /* lw $3,3*4($1) */ + MIPS32_LW(4, 4*4, 1), /* lw $4,4*4($1) */ + MIPS32_LW(5, 5*4, 1), /* lw $5,5*4($1) */ + MIPS32_LW(6, 6*4, 1), /* lw $6,6*4($1) */ + MIPS32_LW(7, 7*4, 1), /* lw $7,7*4($1) */ + MIPS32_LW(8, 8*4, 1), /* lw $8,8*4($1) */ + MIPS32_LW(9, 9*4, 1), /* lw $9,9*4($1) */ + MIPS32_LW(10, 10*4, 1), /* lw $10,10*4($1) */ + MIPS32_LW(11, 11*4, 1), /* lw $11,11*4($1) */ + MIPS32_LW(12, 12*4, 1), /* lw $12,12*4($1) */ + MIPS32_LW(13, 13*4, 1), /* lw $13,13*4($1) */ + MIPS32_LW(14, 14*4, 1), /* lw $14,14*4($1) */ + MIPS32_LW(16, 16*4, 1), /* lw $16,16*4($1) */ + MIPS32_LW(17, 17*4, 1), /* lw $17,17*4($1) */ + MIPS32_LW(18, 18*4, 1), /* lw $18,18*4($1) */ + MIPS32_LW(19, 19*4, 1), /* lw $19,19*4($1) */ + MIPS32_LW(20, 20*4, 1), /* lw $20,20*4($1) */ + MIPS32_LW(21, 21*4, 1), /* lw $21,21*4($1) */ + MIPS32_LW(22, 22*4, 1), /* lw $22,22*4($1) */ + MIPS32_LW(23, 23*4, 1), /* lw $23,23*4($1) */ + MIPS32_LW(24, 24*4, 1), /* lw $24,24*4($1) */ + MIPS32_LW(25, 25*4, 1), /* lw $25,25*4($1) */ + MIPS32_LW(26, 26*4, 1), /* lw $26,26*4($1) */ + MIPS32_LW(27, 27*4, 1), /* lw $27,27*4($1) */ + MIPS32_LW(28, 28*4, 1), /* lw $28,28*4($1) */ + MIPS32_LW(29, 29*4, 1), /* lw $29,29*4($1) */ + MIPS32_LW(30, 30*4, 1), /* lw $30,30*4($1) */ + MIPS32_LW(31, 31*4, 1), /* lw $31,31*4($1) */ + + MIPS32_LW(2, 32*4, 1), /* lw $2,32*4($1) */ + MIPS32_MTC0(2, 12, 0), /* move $2 to status */ + MIPS32_LW(2, 33*4, 1), /* lw $2,33*4($1) */ MIPS32_MTLO(2), /* move $2 to lo */ - MIPS32_LW(2,34*4,1), /* lw $2,34*4($1) */ + MIPS32_LW(2, 34*4, 1), /* lw $2,34*4($1) */ MIPS32_MTHI(2), /* move $2 to hi */ - MIPS32_LW(2,35*4,1), /* lw $2,35*4($1) */ - MIPS32_MTC0(2,8,0), /* move $2 to badvaddr */ - MIPS32_LW(2,36*4,1), /* lw $2,36*4($1) */ - MIPS32_MTC0(2,13,0), /* move $2 to cause*/ - MIPS32_LW(2,37*4,1), /* lw $2,37*4($1) */ - MIPS32_MTC0(2,24,0), /* move $2 to depc (pc) */ - - MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */ - MIPS32_LW(1,0,15), /* lw $1,($15) */ + MIPS32_LW(2, 35*4, 1), /* lw $2,35*4($1) */ + MIPS32_MTC0(2, 8, 0), /* move $2 to badvaddr */ + MIPS32_LW(2, 36*4, 1), /* lw $2,36*4($1) */ + MIPS32_MTC0(2, 13, 0), /* move $2 to cause*/ + MIPS32_LW(2, 37*4, 1), /* lw $2,37*4($1) */ + MIPS32_MTC0(2, 24, 0), /* move $2 to depc (pc) */ + + MIPS32_LW(2, 2*4, 1), /* lw $2,2*4($1) */ + MIPS32_LW(1, 0, 15), /* lw $1,($15) */ MIPS32_B(NEG16(53)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; int retval; @@ -1181,67 +1137,67 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) { static const uint32_t code[] = { /* start: */ - MIPS32_MTC0(2,31,0), /* move $2 to COP0 DeSave */ - MIPS32_LUI(2,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $2 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(2,2,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_SW(0,0*4,2), /* sw $0,0*4($2) */ - MIPS32_SW(1,1*4,2), /* sw $1,1*4($2) */ - MIPS32_SW(15,15*4,2), /* sw $15,15*4($2) */ - MIPS32_MFC0(2,31,0), /* move COP0 DeSave to $2 */ - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1,0,15), /* sw $1,($15) */ - MIPS32_SW(2,0,15), /* sw $2,($15) */ - MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_SW(2,2*4,1), /* sw $2,2*4($1) */ - MIPS32_SW(3,3*4,1), /* sw $3,3*4($1) */ - MIPS32_SW(4,4*4,1), /* sw $4,4*4($1) */ - MIPS32_SW(5,5*4,1), /* sw $5,5*4($1) */ - MIPS32_SW(6,6*4,1), /* sw $6,6*4($1) */ - MIPS32_SW(7,7*4,1), /* sw $7,7*4($1) */ - MIPS32_SW(8,8*4,1), /* sw $8,8*4($1) */ - MIPS32_SW(9,9*4,1), /* sw $9,9*4($1) */ - MIPS32_SW(10,10*4,1), /* sw $10,10*4($1) */ - MIPS32_SW(11,11*4,1), /* sw $11,11*4($1) */ - MIPS32_SW(12,12*4,1), /* sw $12,12*4($1) */ - MIPS32_SW(13,13*4,1), /* sw $13,13*4($1) */ - MIPS32_SW(14,14*4,1), /* sw $14,14*4($1) */ - MIPS32_SW(16,16*4,1), /* sw $16,16*4($1) */ - MIPS32_SW(17,17*4,1), /* sw $17,17*4($1) */ - MIPS32_SW(18,18*4,1), /* sw $18,18*4($1) */ - MIPS32_SW(19,19*4,1), /* sw $19,19*4($1) */ - MIPS32_SW(20,20*4,1), /* sw $20,20*4($1) */ - MIPS32_SW(21,21*4,1), /* sw $21,21*4($1) */ - MIPS32_SW(22,22*4,1), /* sw $22,22*4($1) */ - MIPS32_SW(23,23*4,1), /* sw $23,23*4($1) */ - MIPS32_SW(24,24*4,1), /* sw $24,24*4($1) */ - MIPS32_SW(25,25*4,1), /* sw $25,25*4($1) */ - MIPS32_SW(26,26*4,1), /* sw $26,26*4($1) */ - MIPS32_SW(27,27*4,1), /* sw $27,27*4($1) */ - MIPS32_SW(28,28*4,1), /* sw $28,28*4($1) */ - MIPS32_SW(29,29*4,1), /* sw $29,29*4($1) */ - MIPS32_SW(30,30*4,1), /* sw $30,30*4($1) */ - MIPS32_SW(31,31*4,1), /* sw $31,31*4($1) */ - - MIPS32_MFC0(2,12,0), /* move status to $2 */ - MIPS32_SW(2,32*4,1), /* sw $2,32*4($1) */ + MIPS32_MTC0(2, 31, 0), /* move $2 to COP0 DeSave */ + MIPS32_LUI(2, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $2 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(2, 2, LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_SW(0, 0*4, 2), /* sw $0,0*4($2) */ + MIPS32_SW(1, 1*4, 2), /* sw $1,1*4($2) */ + MIPS32_SW(15, 15*4, 2), /* sw $15,15*4($2) */ + MIPS32_MFC0(2, 31, 0), /* move COP0 DeSave to $2 */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(1, 0, 15), /* sw $1,($15) */ + MIPS32_SW(2, 0, 15), /* sw $2,($15) */ + MIPS32_LUI(1, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(1, 1, LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_SW(2, 2*4, 1), /* sw $2,2*4($1) */ + MIPS32_SW(3, 3*4, 1), /* sw $3,3*4($1) */ + MIPS32_SW(4, 4*4, 1), /* sw $4,4*4($1) */ + MIPS32_SW(5, 5*4, 1), /* sw $5,5*4($1) */ + MIPS32_SW(6, 6*4, 1), /* sw $6,6*4($1) */ + MIPS32_SW(7, 7*4, 1), /* sw $7,7*4($1) */ + MIPS32_SW(8, 8*4, 1), /* sw $8,8*4($1) */ + MIPS32_SW(9, 9*4, 1), /* sw $9,9*4($1) */ + MIPS32_SW(10, 10*4, 1), /* sw $10,10*4($1) */ + MIPS32_SW(11, 11*4, 1), /* sw $11,11*4($1) */ + MIPS32_SW(12, 12*4, 1), /* sw $12,12*4($1) */ + MIPS32_SW(13, 13*4, 1), /* sw $13,13*4($1) */ + MIPS32_SW(14, 14*4, 1), /* sw $14,14*4($1) */ + MIPS32_SW(16, 16*4, 1), /* sw $16,16*4($1) */ + MIPS32_SW(17, 17*4, 1), /* sw $17,17*4($1) */ + MIPS32_SW(18, 18*4, 1), /* sw $18,18*4($1) */ + MIPS32_SW(19, 19*4, 1), /* sw $19,19*4($1) */ + MIPS32_SW(20, 20*4, 1), /* sw $20,20*4($1) */ + MIPS32_SW(21, 21*4, 1), /* sw $21,21*4($1) */ + MIPS32_SW(22, 22*4, 1), /* sw $22,22*4($1) */ + MIPS32_SW(23, 23*4, 1), /* sw $23,23*4($1) */ + MIPS32_SW(24, 24*4, 1), /* sw $24,24*4($1) */ + MIPS32_SW(25, 25*4, 1), /* sw $25,25*4($1) */ + MIPS32_SW(26, 26*4, 1), /* sw $26,26*4($1) */ + MIPS32_SW(27, 27*4, 1), /* sw $27,27*4($1) */ + MIPS32_SW(28, 28*4, 1), /* sw $28,28*4($1) */ + MIPS32_SW(29, 29*4, 1), /* sw $29,29*4($1) */ + MIPS32_SW(30, 30*4, 1), /* sw $30,30*4($1) */ + MIPS32_SW(31, 31*4, 1), /* sw $31,31*4($1) */ + + MIPS32_MFC0(2, 12, 0), /* move status to $2 */ + MIPS32_SW(2, 32*4, 1), /* sw $2,32*4($1) */ MIPS32_MFLO(2), /* move lo to $2 */ - MIPS32_SW(2,33*4,1), /* sw $2,33*4($1) */ + MIPS32_SW(2, 33*4, 1), /* sw $2,33*4($1) */ MIPS32_MFHI(2), /* move hi to $2 */ - MIPS32_SW(2,34*4,1), /* sw $2,34*4($1) */ - MIPS32_MFC0(2,8,0), /* move badvaddr to $2 */ - MIPS32_SW(2,35*4,1), /* sw $2,35*4($1) */ - MIPS32_MFC0(2,13,0), /* move cause to $2 */ - MIPS32_SW(2,36*4,1), /* sw $2,36*4($1) */ - MIPS32_MFC0(2,24,0), /* move depc (pc) to $2 */ - MIPS32_SW(2,37*4,1), /* sw $2,37*4($1) */ - - MIPS32_LW(2,0,15), /* lw $2,($15) */ - MIPS32_LW(1,0,15), /* lw $1,($15) */ + MIPS32_SW(2, 34*4, 1), /* sw $2,34*4($1) */ + MIPS32_MFC0(2, 8, 0), /* move badvaddr to $2 */ + MIPS32_SW(2, 35*4, 1), /* sw $2,35*4($1) */ + MIPS32_MFC0(2, 13, 0), /* move cause to $2 */ + MIPS32_SW(2, 36*4, 1), /* sw $2,36*4($1) */ + MIPS32_MFC0(2, 24, 0), /* move depc (pc) to $2 */ + MIPS32_SW(2, 37*4, 1), /* sw $2,37*4($1) */ + + MIPS32_LW(2, 0, 15), /* lw $2,($15) */ + MIPS32_LW(1, 0, 15), /* lw $1,($15) */ MIPS32_B(NEG16(58)), /* b start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; int retval; @@ -1260,41 +1216,41 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) * 3. data ... */ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, - int write_t, uint32_t addr, int count, uint32_t *buf) + int write_t, uint32_t addr, int count, uint32_t *buf) { uint32_t handler_code[] = { /* caution when editing, table is modified below */ /* r15 points to the start of this code */ - MIPS32_SW(8,MIPS32_FASTDATA_HANDLER_SIZE - 4,15), - MIPS32_SW(9,MIPS32_FASTDATA_HANDLER_SIZE - 8,15), - MIPS32_SW(10,MIPS32_FASTDATA_HANDLER_SIZE - 12,15), - MIPS32_SW(11,MIPS32_FASTDATA_HANDLER_SIZE - 16,15), + MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15), + MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15), + MIPS32_SW(10, MIPS32_FASTDATA_HANDLER_SIZE - 12, 15), + MIPS32_SW(11, MIPS32_FASTDATA_HANDLER_SIZE - 16, 15), /* start of fastdata area in t0 */ - MIPS32_LUI(8,UPPER16(MIPS32_PRACC_FASTDATA_AREA)), - MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_FASTDATA_AREA)), - MIPS32_LW(9,0,8), /* start addr in t1 */ - MIPS32_LW(10,0,8), /* end addr to t2 */ + MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA)), + MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA)), + MIPS32_LW(9, 0, 8), /* start addr in t1 */ + MIPS32_LW(10, 0, 8), /* end addr to t2 */ /* loop: */ - /* 8 */ MIPS32_LW(11,0,0), /* lw t3,[t8 | r9] */ - /* 9 */ MIPS32_SW(11,0,0), /* sw t3,[r9 | r8] */ - MIPS32_BNE(10,9,NEG16(3)), /* bne $t2,t1,loop */ - MIPS32_ADDI(9,9,4), /* addi t1,t1,4 */ - - MIPS32_LW(8,MIPS32_FASTDATA_HANDLER_SIZE - 4,15), - MIPS32_LW(9,MIPS32_FASTDATA_HANDLER_SIZE - 8,15), - MIPS32_LW(10,MIPS32_FASTDATA_HANDLER_SIZE - 12,15), - MIPS32_LW(11,MIPS32_FASTDATA_HANDLER_SIZE - 16,15), - - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_TEXT)), - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_TEXT)), - MIPS32_JR(15), /* jr start */ - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */ + /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */ + MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */ + MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */ + + MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE - 4, 15), + MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE - 8, 15), + MIPS32_LW(10, MIPS32_FASTDATA_HANDLER_SIZE - 12, 15), + MIPS32_LW(11, MIPS32_FASTDATA_HANDLER_SIZE - 16, 15), + + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_TEXT)), + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_TEXT)), + MIPS32_JR(15), /* jr start */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; uint32_t jmp_code[] = { - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - /* 1 */ MIPS32_LUI(15,0), /* addr of working area added below */ - /* 2 */ MIPS32_ORI(15,15,0), /* addr of working area added below */ + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + /* 1 */ MIPS32_LUI(15, 0), /* addr of working area added below */ + /* 2 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */ MIPS32_JR(15), /* jump to ram program */ MIPS32_NOP, }; @@ -1305,20 +1261,16 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - if (write_t) - { - handler_code[8] = MIPS32_LW(11,0,8); /* load data from probe at fastdata area */ - handler_code[9] = MIPS32_SW(11,0,9); /* store data to RAM @ r9 */ - } - else - { - handler_code[8] = MIPS32_LW(11,0,9); /* load data from RAM @ r9 */ - handler_code[9] = MIPS32_SW(11,0,8); /* store data to probe at fastdata area */ + if (write_t) { + handler_code[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */ + handler_code[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */ + } else { + handler_code[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */ + handler_code[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */ } /* write program into RAM */ - if (write_t != ejtag_info->fast_access_save) - { + if (write_t != ejtag_info->fast_access_save) { mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code); /* save previous operation to speed to any consecutive read/writes */ ejtag_info->fast_access_save = write_t; @@ -1329,9 +1281,9 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are jmp_code[1] |= UPPER16(source->address); jmp_code[2] |= LOWER16(source->address); - for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) - { - if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) { + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) return retval; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); @@ -1343,7 +1295,8 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl); } - if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) return retval; /* next fetch to dmseg should be in FASTDATA_AREA, check */ @@ -1357,7 +1310,8 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are return ERROR_FAIL; /* wait PrAcc pending bit for FASTDATA write */ - if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) return retval; /* Send the load start address */ @@ -1369,19 +1323,20 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are val = addr + (count - 1) * 4; mips_ejtag_fastdata_scan(ejtag_info, 1, &val); - for (i = 0; i < count; i++) - { - if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK) + for (i = 0; i < count; i++) { + retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++); + if (retval != ERROR_OK) return retval; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("fastdata load failed"); return retval; } - if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) return retval; address = 0; diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index 0c106ba..c200e93 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -22,6 +22,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef MIPS32_PRACC_H #define MIPS32_PRACC_H @@ -71,7 +72,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ * @return ERROR_OK on Sucess, ERROR_FAIL otherwise */ int mips32_cp0_read(struct mips_ejtag *ejtag_info, - uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel); + uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel); /** * \b mips32_cp0_write @@ -87,6 +88,6 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, * @return ERROR_OK on Sucess, ERROR_FAIL otherwise */ int mips32_cp0_write(struct mips_ejtag *ejtag_info, - uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel); + uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel); #endif diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index 449b6b8..9114f8c 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -21,6 +21,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -35,8 +36,7 @@ void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr) tap = ejtag_info->tap; assert(tap != NULL); - if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) - { + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) { struct scan_field field; uint8_t t[4]; @@ -63,8 +63,8 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode) jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE); int retval; - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } @@ -88,8 +88,8 @@ static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impco jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE); int retval; - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } @@ -116,8 +116,8 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data) jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } @@ -164,8 +164,8 @@ int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data) jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } @@ -193,12 +193,12 @@ void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data) static int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info) { static const uint32_t code[] = { - MIPS32_MTC0(1,31,0), /* move $1 to COP0 DeSave */ - MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */ - MIPS32_ORI(1,1,0x0100), /* set SSt bit in debug reg */ - MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */ + MIPS32_MTC0(1, 31, 0), /* move $1 to COP0 DeSave */ + MIPS32_MFC0(1, 23, 0), /* move COP0 Debug to $1 */ + MIPS32_ORI(1, 1, 0x0100), /* set SSt bit in debug reg */ + MIPS32_MTC0(1, 23, 0), /* move $1 to COP0 Debug */ MIPS32_B(NEG16(5)), - MIPS32_MFC0(1,31,0), /* move COP0 DeSave to $1 */ + MIPS32_MFC0(1, 31, 0), /* move COP0 DeSave to $1 */ }; return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, @@ -208,20 +208,20 @@ static int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info) static int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info) { static const uint32_t code[] = { - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1,0,15), /* sw $1,($15) */ - MIPS32_SW(2,0,15), /* sw $2,($15) */ - MIPS32_MFC0(1,23,0), /* move COP0 Debug to $1 */ - MIPS32_LUI(2,0xFFFF), /* $2 = 0xfffffeff */ - MIPS32_ORI(2,2,0xFEFF), - MIPS32_AND(1,1,2), - MIPS32_MTC0(1,23,0), /* move $1 to COP0 Debug */ - MIPS32_LW(2,0,15), - MIPS32_LW(1,0,15), + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(1, 0, 15), /* sw $1,($15) */ + MIPS32_SW(2, 0, 15), /* sw $2,($15) */ + MIPS32_MFC0(1, 23, 0), /* move COP0 Debug to $1 */ + MIPS32_LUI(2, 0xFFFF), /* $2 = 0xfffffeff */ + MIPS32_ORI(2, 2, 0xFEFF), + MIPS32_AND(1, 1, 2), + MIPS32_MTC0(1, 23, 0), /* move $1 to COP0 Debug */ + MIPS32_LW(2, 0, 15), + MIPS32_LW(1, 0, 15), MIPS32_B(NEG16(13)), - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, @@ -248,8 +248,7 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info) ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl); - if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) - { + if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) { LOG_ERROR("Failed to enter Debug Mode!"); return ERROR_FAIL; } @@ -270,19 +269,19 @@ int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg) { /* read ejtag ECR */ static const uint32_t code[] = { - MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ - MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ - MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), - MIPS32_SW(1,0,15), /* sw $1,($15) */ - MIPS32_SW(2,0,15), /* sw $2,($15) */ - MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ - MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)), - MIPS32_MFC0(2,23,0), /* move COP0 Debug to $2 */ - MIPS32_SW(2,0,1), - MIPS32_LW(2,0,15), - MIPS32_LW(1,0,15), + MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(1, 0, 15), /* sw $1,($15) */ + MIPS32_SW(2, 0, 15), /* sw $2,($15) */ + MIPS32_LUI(1, UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $1 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(1, 1, LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_MFC0(2, 23, 0), /* move COP0 Debug to $2 */ + MIPS32_SW(2, 0, 1), + MIPS32_LW(2, 0, 15), + MIPS32_LW(1, 0, 15), MIPS32_B(NEG16(12)), - MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */ }; return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, @@ -302,8 +301,7 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info) /* get ejtag version */ ejtag_version = ((ejtag_info->impcode >> 29) & 0x07); - switch (ejtag_version) - { + switch (ejtag_version) { case 0: LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected"); break; @@ -359,19 +357,15 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_ fields[1].num_bits = 32; fields[1].out_value = t; - if (write_t) - { + if (write_t) { fields[1].in_value = NULL; buf_set_u32(t, 0, 32, *data); - } - else - { + } else fields[1].in_value = (void *) data; - } jtag_add_dr_scan(tap, 2, fields, TAP_IDLE); - if ( (!write_t) && (data) ) + if (!write_t && data) jtag_add_callback(mips_le_to_h_u32, (jtag_callback_data_t) data); diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h index 399246c..be2af27 100644 --- a/src/target/mips_ejtag.h +++ b/src/target/mips_ejtag.h @@ -122,8 +122,7 @@ #define EJTAG_DBCn_BLM_SHIFT 4 #define EJTAG_DBCn_BE (1 << 0) -struct mips_ejtag -{ +struct mips_ejtag { struct jtag_tap *tap; uint32_t impcode; uint32_t idcode; @@ -146,7 +145,7 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info); int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step); int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg); -static __inline__ void mips_le_to_h_u32(jtag_callback_data_t arg) +static inline void mips_le_to_h_u32(jtag_callback_data_t arg) { uint8_t *in = (uint8_t *)arg; *((uint32_t *)arg) = le_to_h_u32(in); diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 83a2a7b..aa9dbe7 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -24,6 +24,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -48,26 +49,27 @@ static int mips_m4k_examine_debug_reason(struct target *target) int retval; if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { /* get info about inst breakpoint support */ - if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK) + retval = target_read_u32(target, EJTAG_IBS, &break_status); + if (retval != ERROR_OK) return retval; - if (break_status & 0x1f) - { + if (break_status & 0x1f) { /* we have halted on a breakpoint */ - if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK) + retval = target_write_u32(target, EJTAG_IBS, 0); + if (retval != ERROR_OK) return retval; target->debug_reason = DBG_REASON_BREAKPOINT; } /* get info about data breakpoint support */ - if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK) + retval = target_read_u32(target, EJTAG_DBS, &break_status); + if (retval != ERROR_OK) return retval; - if (break_status & 0x1f) - { + if (break_status & 0x1f) { /* we have halted on a breakpoint */ - if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK) + retval = target_write_u32(target, EJTAG_DBS, 0); + if (retval != ERROR_OK) return retval; target->debug_reason = DBG_REASON_WATCHPOINT; } @@ -92,8 +94,7 @@ static int mips_m4k_debug_entry(struct target *target) mips_m4k_examine_debug_reason(target); /* clear single step if active */ - if (debug_reg & EJTAG_DEBUG_DSS) - { + if (debug_reg & EJTAG_DEBUG_DSS) { /* stopped due to single step - clear step bit */ mips_ejtag_config_step(ejtag_info, 0); } @@ -103,9 +104,8 @@ static int mips_m4k_debug_entry(struct target *target) /* default to mips32 isa, it will be changed below if required */ mips32->isa_mode = MIPS32_ISA_MIPS32; - if (ejtag_info->impcode & EJTAG_IMP_MIPS16) { + if (ejtag_info->impcode & EJTAG_IMP_MIPS16) mips32->isa_mode = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1); - } LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s", buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32), @@ -129,8 +129,7 @@ static int mips_m4k_poll(struct target *target) /* clear this bit before handling polling * as after reset registers will read zero */ - if (ejtag_ctrl & EJTAG_CTRL_ROCC) - { + if (ejtag_ctrl & EJTAG_CTRL_ROCC) { /* we have detected a reset, clear flag * otherwise ejtag will not work */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; @@ -143,35 +142,30 @@ static int mips_m4k_poll(struct target *target) } /* check for processor halted */ - if (ejtag_ctrl & EJTAG_CTRL_BRKST) - { - if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) - { + if (ejtag_ctrl & EJTAG_CTRL_BRKST) { + if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); target->state = TARGET_HALTED; - if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) + retval = mips_m4k_debug_entry(target); + if (retval != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } - else if (target->state == TARGET_DEBUG_RUNNING) - { + } else if (target->state == TARGET_DEBUG_RUNNING) { target->state = TARGET_HALTED; - if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) + retval = mips_m4k_debug_entry(target); + if (retval != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } - } - else - { + } else target->state = TARGET_RUNNING; - } -// LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); +/* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */ return ERROR_OK; } @@ -181,29 +175,21 @@ static int mips_m4k_halt(struct target *target) struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - LOG_DEBUG("target->state: %s", - target_state_name(target)); + LOG_DEBUG("target->state: %s", target_state_name(target)); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } if (target->state == TARGET_UNKNOWN) - { LOG_WARNING("target was in unknown state when halt was requested"); - } - if (target->state == TARGET_RESET) - { - if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) - { + if (target->state == TARGET_RESET) { + if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) { LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST"); return ERROR_TARGET_FAILURE; - } - else - { + } else { /* we came here in a reset_halt or reset_init sequence * debug entry was already prepared in mips32_prepare_reset_halt() */ @@ -235,32 +221,20 @@ static int mips_m4k_assert_reset(struct target *target) if (!(jtag_reset_config & RESET_HAS_SRST)) assert_srst = 0; - if (target->reset_halt) - { + if (target->reset_halt) { /* use hardware to catch reset */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT); - } - else - { + } else mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT); - } - if (assert_srst) - { + if (assert_srst) { /* here we should issue a srst only, but we may have to assert trst as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { jtag_add_reset(1, 1); - } else - { jtag_add_reset(0, 1); - } - } - else - { - if (mips_m4k->is_pic32mx) - { + } else { + if (mips_m4k->is_pic32mx) { LOG_DEBUG("Using MTAP reset to reset processor..."); /* use microchip specific MTAP reset */ @@ -270,9 +244,7 @@ static int mips_m4k_assert_reset(struct target *target) mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST); mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST); mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); - } - else - { + } else { /* use ejtag reset - not supported by all cores */ uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); @@ -286,10 +258,9 @@ static int mips_m4k_assert_reset(struct target *target) register_cache_invalidate(mips_m4k->mips32.core_cache); - if (target->reset_halt) - { - int retval; - if ((retval = target_halt(target)) != ERROR_OK) + if (target->reset_halt) { + int retval = target_halt(target); + if (retval != ERROR_OK) return retval; } @@ -298,8 +269,7 @@ static int mips_m4k_assert_reset(struct target *target) static int mips_m4k_deassert_reset(struct target *target) { - LOG_DEBUG("target->state: %s", - target_state_name(target)); + LOG_DEBUG("target->state: %s", target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -340,41 +310,36 @@ static int mips_m4k_resume(struct target *target, int current, struct breakpoint *breakpoint = NULL; uint32_t resume_pc; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!debug_execution) - { + if (!debug_execution) { target_free_all_working_areas(target); mips_m4k_enable_breakpoints(target); mips_m4k_enable_watchpoints(target); } /* current = 1: continue on current pc, otherwise continue at <address> */ - if (!current) - { + if (!current) { buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; mips32->core_cache->reg_list[MIPS32_PC].valid = 1; } - if (ejtag_info->impcode & EJTAG_IMP_MIPS16) { + if (ejtag_info->impcode & EJTAG_IMP_MIPS16) buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode); - } resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); mips32_restore_context(target); /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { /* Single step past breakpoint at current address */ - if ((breakpoint = breakpoint_find(target, resume_pc))) - { + breakpoint = breakpoint_find(target, resume_pc); + if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); mips_m4k_unset_breakpoint(target, breakpoint); mips_m4k_single_step_core(target); @@ -392,14 +357,11 @@ static int mips_m4k_resume(struct target *target, int current, /* registers are now invalid */ register_cache_invalidate(mips32->core_cache); - if (!debug_execution) - { + if (!debug_execution) { target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc); @@ -416,15 +378,13 @@ static int mips_m4k_step(struct target *target, int current, struct mips_ejtag *ejtag_info = &mips32->ejtag_info; struct breakpoint *breakpoint = NULL; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } /* current = 1: continue on current pc, otherwise continue at <address> */ - if (!current) - { + if (!current) { buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; mips32->core_cache->reg_list[MIPS32_PC].valid = 1; @@ -473,8 +433,7 @@ static void mips_m4k_enable_breakpoints(struct target *target) struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ - while (breakpoint) - { + while (breakpoint) { if (breakpoint->set == 0) mips_m4k_set_breakpoint(target, breakpoint); breakpoint = breakpoint->next; @@ -485,85 +444,72 @@ static int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { struct mips32_common *mips32 = target_to_mips32(target); - struct mips32_comparator * comparator_list = mips32->inst_break_list; + struct mips32_comparator *comparator_list = mips32->inst_break_list; int retval; - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { int bp_num = 0; while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints)) bp_num++; - if (bp_num >= mips32->num_inst_bpoints) - { + if (bp_num >= mips32->num_inst_bpoints) { LOG_ERROR("Can not find free FP Comparator(bpid: %d)", - breakpoint->unique_id ); + breakpoint->unique_id); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } breakpoint->set = bp_num + 1; comparator_list[bp_num].used = 1; comparator_list[bp_num].bp_value = breakpoint->address; - target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value); + target_write_u32(target, comparator_list[bp_num].reg_address, + comparator_list[bp_num].bp_value); target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000); target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1); LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "", breakpoint->unique_id, bp_num, comparator_list[bp_num].bp_value); - } - else if (breakpoint->type == BKPT_SOFT) - { - LOG_DEBUG("bpid: %d", breakpoint->unique_id ); - if (breakpoint->length == 4) - { + } else if (breakpoint->type == BKPT_SOFT) { + LOG_DEBUG("bpid: %d", breakpoint->unique_id); + if (breakpoint->length == 4) { uint32_t verify = 0xffffffff; - if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK) - { + retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK) - { + retval = target_read_u32(target, breakpoint->address, &verify); + if (retval != ERROR_OK) return retval; - } - if (verify != MIPS32_SDBBP) - { - LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); + if (verify != MIPS32_SDBBP) { + LOG_ERROR("Unable to set 32bit breakpoint at address %08" PRIx32 + " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } - } - else - { + } else { uint16_t verify = 0xffff; - if ((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK) - { + retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP); + if (retval != ERROR_OK) return retval; - } - if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK) - { + retval = target_read_u16(target, breakpoint->address, &verify); + if (retval != ERROR_OK) return retval; - } - if (verify != MIPS16_SDBBP) - { - LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); + if (verify != MIPS16_SDBBP) { + LOG_ERROR("Unable to set 16bit breakpoint at address %08" PRIx32 + " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } } @@ -582,43 +528,36 @@ static int mips_m4k_unset_breakpoint(struct target *target, struct mips32_comparator *comparator_list = mips32->inst_break_list; int retval; - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { int bp_num = breakpoint->set - 1; - if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) - { + if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints)) { LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)", breakpoint->unique_id); return ERROR_OK; } LOG_DEBUG("bpid: %d - releasing hw: %d", - breakpoint->unique_id, - bp_num ); + breakpoint->unique_id, + bp_num); comparator_list[bp_num].used = 0; comparator_list[bp_num].bp_value = 0; target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0); - } - else - { + } else { /* restore original instruction (kept in target endianness) */ LOG_DEBUG("bpid: %d", breakpoint->unique_id); - if (breakpoint->length == 4) - { + if (breakpoint->length == 4) { uint32_t current_instr; /* check that user program has not modified breakpoint instruction */ - if ((retval = target_read_memory(target, breakpoint->address, 4, 1, - (uint8_t*)¤t_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 4, 1, + (uint8_t *)¤t_instr); + if (retval != ERROR_OK) return retval; - } /** * target_read_memory() gets us data in _target_ endianess. @@ -627,33 +566,26 @@ static int mips_m4k_unset_breakpoint(struct target *target, */ current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); - if (current_instr == MIPS32_SDBBP) - { - if ((retval = target_write_memory(target, breakpoint->address, 4, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + if (current_instr == MIPS32_SDBBP) { + retval = target_write_memory(target, breakpoint->address, 4, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } } - } - else - { + } else { uint16_t current_instr; /* check that user program has not modified breakpoint instruction */ - if ((retval = target_read_memory(target, breakpoint->address, 2, 1, - (uint8_t*)¤t_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 2, 1, + (uint8_t *)¤t_instr); + if (retval != ERROR_OK) return retval; - } current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); - if (current_instr == MIPS16_SDBBP) - { - if ((retval = target_write_memory(target, breakpoint->address, 2, 1, - breakpoint->orig_instr)) != ERROR_OK) - { + if (current_instr == MIPS16_SDBBP) { + retval = target_write_memory(target, breakpoint->address, 2, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } } } } @@ -666,10 +598,8 @@ static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *bre { struct mips32_common *mips32 = target_to_mips32(target); - if (breakpoint->type == BKPT_HARD) - { - if (mips32->num_inst_bpoints_avail < 1) - { + if (breakpoint->type == BKPT_HARD) { + if (mips32->num_inst_bpoints_avail < 1) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -686,16 +616,13 @@ static int mips_m4k_remove_breakpoint(struct target *target, /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (breakpoint->set) - { mips_m4k_unset_breakpoint(target, breakpoint); - } if (breakpoint->type == BKPT_HARD) mips32->num_inst_bpoints_avail++; @@ -715,36 +642,31 @@ static int mips_m4k_set_watchpoint(struct target *target, * condition evaluation */ int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | - (0xff << EJTAG_DBCn_BLM_SHIFT); + (0xff << EJTAG_DBCn_BLM_SHIFT); - if (watchpoint->set) - { + if (watchpoint->set) { LOG_WARNING("watchpoint already set"); return ERROR_OK; } - while(comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints)) + while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints)) wp_num++; - if (wp_num >= mips32->num_data_bpoints) - { + if (wp_num >= mips32->num_data_bpoints) { LOG_ERROR("Can not find free FP Comparator"); return ERROR_FAIL; } - if (watchpoint->length != 4) - { + if (watchpoint->length != 4) { LOG_ERROR("Only watchpoints of length 4 are supported"); return ERROR_TARGET_UNALIGNED_ACCESS; } - if (watchpoint->address % 4) - { + if (watchpoint->address % 4) { LOG_ERROR("Watchpoints address should be word aligned"); return ERROR_TARGET_UNALIGNED_ACCESS; } - switch (watchpoint->rw) - { + switch (watchpoint->rw) { case WPT_READ: enable &= ~EJTAG_DBCn_NOLB; break; @@ -778,15 +700,13 @@ static int mips_m4k_unset_watchpoint(struct target *target, struct mips32_common *mips32 = target_to_mips32(target); struct mips32_comparator *comparator_list = mips32->data_break_list; - if (!watchpoint->set) - { + if (!watchpoint->set) { LOG_WARNING("watchpoint not set"); return ERROR_OK; } int wp_num = watchpoint->set - 1; - if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) - { + if ((wp_num < 0) || (wp_num >= mips32->num_data_bpoints)) { LOG_DEBUG("Invalid FP Comparator number in watchpoint"); return ERROR_OK; } @@ -802,8 +722,7 @@ static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *wat { struct mips32_common *mips32 = target_to_mips32(target); - if (mips32->num_data_bpoints_avail < 1) - { + if (mips32->num_data_bpoints_avail < 1) { LOG_INFO("no hardware watchpoints available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -820,16 +739,13 @@ static int mips_m4k_remove_watchpoint(struct target *target, /* get pointers to arch-specific information */ struct mips32_common *mips32 = target_to_mips32(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (watchpoint->set) - { mips_m4k_unset_watchpoint(target, watchpoint); - } mips32->num_data_bpoints_avail++; @@ -841,8 +757,7 @@ static void mips_m4k_enable_watchpoints(struct target *target) struct watchpoint *watchpoint = target->watchpoints; /* set any pending watchpoints */ - while (watchpoint) - { + while (watchpoint) { if (watchpoint->set == 0) mips_m4k_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; @@ -855,10 +770,10 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, struct mips32_common *mips32 = target_to_mips32(target); struct mips_ejtag *ejtag_info = &mips32->ejtag_info; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + address, size, count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -873,19 +788,14 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */ void *t = NULL; - if (size > 1) - { + if (size > 1) { t = malloc(count * size * sizeof(uint8_t)); - if (t == NULL) - { + if (t == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - } - else - { + } else t = buffer; - } /* if noDMA off, use DMAACC mode for memory read */ int retval; @@ -896,15 +806,13 @@ static int mips_m4k_read_memory(struct target *target, uint32_t address, /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */ /* endianness, but byte array should represent target endianness */ - if (ERROR_OK == retval) - { - switch(size) - { + if (ERROR_OK == retval) { + switch (size) { case 4: - target_buffer_set_u32_array(target,buffer,count,t); + target_buffer_set_u32_array(target, buffer, count, t); break; case 2: - target_buffer_set_u16_array(target,buffer,count,t); + target_buffer_set_u16_array(target, buffer, count, t); break; } } @@ -924,8 +832,7 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -939,24 +846,21 @@ static int mips_m4k_write_memory(struct target *target, uint32_t address, /** correct endianess if we have word or hword access */ void *t = NULL; - if (size > 1) - { + if (size > 1) { /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */ /* endianness, but byte array represents target endianness */ t = malloc(count * size * sizeof(uint8_t)); - if (t == NULL) - { + if (t == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - switch(size) - { + switch (size) { case 4: - target_buffer_get_u32_array(target,buffer,count,(uint32_t*)t); + target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t); break; case 2: - target_buffer_get_u16_array(target,buffer,count,(uint16_t*)t); + target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t); break; } buffer = t; @@ -1016,15 +920,13 @@ static int mips_m4k_examine(struct target *target) struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info; uint32_t idcode = 0; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { retval = mips_ejtag_get_idcode(ejtag_info, &idcode); if (retval != ERROR_OK) return retval; ejtag_info->idcode = idcode; - if (((idcode >> 1) & 0x7FF) == 0x29) - { + if (((idcode >> 1) & 0x7FF) == 0x29) { /* we are using a pic32mx so select ejtag port * as it is not selected by default */ mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP); @@ -1034,10 +936,12 @@ static int mips_m4k_examine(struct target *target) } /* init rest of ejtag interface */ - if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK) + retval = mips_ejtag_init(ejtag_info); + if (retval != ERROR_OK) return retval; - if ((retval = mips32_examine(target)) != ERROR_OK) + retval = mips32_examine(target); + if (retval != ERROR_OK) return retval; return ERROR_OK; @@ -1053,8 +957,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, LOG_DEBUG("address: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1063,8 +966,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, if (address & 0x3u) return ERROR_TARGET_UNALIGNED_ACCESS; - if (mips32->fast_data_area == NULL) - { + if (mips32->fast_data_area == NULL) { /* Get memory for block write handler * we preserve this area between calls and gain a speed increase * of about 3kb/sec when writing flash @@ -1072,8 +974,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, retval = target_alloc_working_area(target, MIPS32_FASTDATA_HANDLER_SIZE, &mips32->fast_data_area); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_WARNING("No working area available, falling back to non-bulk write"); return mips_m4k_write_memory(target, address, 4, count, buffer); } @@ -1086,13 +987,12 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, /* but byte array represents target endianness */ uint32_t *t = NULL; t = malloc(count * sizeof(uint32_t)); - if (t == NULL) - { + if (t == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - target_buffer_get_u32_array(target,buffer,count,t); + target_buffer_get_u32_array(target, buffer, count, t); retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address, count, t); @@ -1100,8 +1000,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, if (t != NULL) free(t); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { /* FASTDATA access failed, try normal memory write */ LOG_DEBUG("Fastdata access Failed, falling back to non-bulk write"); retval = mips_m4k_write_memory(target, address, 4, count, buffer); @@ -1131,48 +1030,40 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* two or more argument, access a single register/select (write if third argument is given) */ if (CMD_ARGC < 2) - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - else - { + return ERROR_COMMAND_SYNTAX_ERROR; + else { uint32_t cp0_reg, cp0_sel; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel); - if (CMD_ARGC == 2) - { + if (CMD_ARGC == 2) { uint32_t value; - if ((retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel)) != ERROR_OK) - { + retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access reg %" PRIi32, cp0_reg); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32, cp0_reg, cp0_sel, value); - } - else if (CMD_ARGC == 3) - { + } else if (CMD_ARGC == 3) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); - if ((retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel)) != ERROR_OK) - { + retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp0 reg %" PRIi32 ", select %" PRIi32, cp0_reg, cp0_sel); @@ -1211,8 +1102,7 @@ const struct command_registration mips_m4k_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct target_type mips_m4k_target = -{ +struct target_type mips_m4k_target = { .name = "mips_m4k", .poll = mips_m4k_poll, diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h index 11a936f..5a9ed77 100644 --- a/src/target/mips_m4k.h +++ b/src/target/mips_m4k.h @@ -32,8 +32,7 @@ struct target; #define MIPSM4K_COMMON_MAGIC 0xB321B321 -struct mips_m4k_common -{ +struct mips_m4k_common { uint32_t common_magic; bool is_pic32mx; struct mips32_common mips32; diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c index 09beba9..240f867 100644 --- a/src/target/oocd_trace.c +++ b/src/target/oocd_trace.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -30,7 +31,6 @@ * https://lists.berlios.de/pipermail/openocd-development/2007-September/000336.html */ - static int oocd_trace_read_reg(struct oocd_trace *oocd_trace, int reg, uint32_t *value) { size_t bytes_written, bytes_read, bytes_to_read; @@ -40,9 +40,8 @@ static int oocd_trace_read_reg(struct oocd_trace *oocd_trace, int reg, uint32_t bytes_written = write(oocd_trace->tty_fd, &cmd, 1); bytes_to_read = 4; - while (bytes_to_read > 0) - { - bytes_read = read(oocd_trace->tty_fd, ((uint8_t*)value) + 4 - bytes_to_read, bytes_to_read); + while (bytes_to_read > 0) { + bytes_read = read(oocd_trace->tty_fd, ((uint8_t *)value) + 4 - bytes_to_read, bytes_to_read); bytes_to_read -= bytes_read; } @@ -81,13 +80,11 @@ static int oocd_trace_read_memory(struct oocd_trace *oocd_trace, uint8_t *data, bytes_written = write(oocd_trace->tty_fd, &cmd, 1); bytes_to_read = size * 16; - while (bytes_to_read > 0) - { - if ((bytes_read = read(oocd_trace->tty_fd, - ((uint8_t*)data) + (size * 16) - bytes_to_read, bytes_to_read)) < 0) - { + while (bytes_to_read > 0) { + bytes_read = read(oocd_trace->tty_fd, + ((uint8_t *)data) + (size * 16) - bytes_to_read, bytes_to_read); + if (bytes_read < 0) LOG_DEBUG("read() returned %zi (%s)", bytes_read, strerror(errno)); - } else bytes_to_read -= bytes_read; } @@ -103,8 +100,7 @@ static int oocd_trace_init(struct etm_context *etm_ctx) oocd_trace->tty_fd = open(oocd_trace->tty, O_RDWR | O_NOCTTY | O_NONBLOCK); - if (oocd_trace->tty_fd < 0) - { + if (oocd_trace->tty_fd < 0) { LOG_ERROR("can't open tty"); return ERROR_ETM_CAPTURE_INIT_FAILED; } @@ -134,10 +130,11 @@ static int oocd_trace_init(struct etm_context *etm_ctx) /* occasionally one bogus character is left in the input buffer * read up any leftover characters to ensure communication is in sync */ - while ((bytes_read = read(oocd_trace->tty_fd, trash, sizeof(trash))) > 0) - { - LOG_DEBUG("%zi bytes read", bytes_read); - }; + do { + bytes_read = read(oocd_trace->tty_fd, trash, sizeof(trash)); + if (bytes_read) + LOG_DEBUG("%zi bytes read", bytes_read); + } while (bytes_read > 0); return ERROR_OK; } @@ -151,11 +148,8 @@ static trace_status_t oocd_trace_status(struct etm_context *etm_ctx) /* if tracing is currently idle, return this information */ if (etm_ctx->capture_status == TRACE_IDLE) - { return etm_ctx->capture_status; - } - else if (etm_ctx->capture_status & TRACE_RUNNING) - { + else if (etm_ctx->capture_status & TRACE_RUNNING) { /* check Full bit to identify an overflow */ if (status & 0x4) etm_ctx->capture_status |= TRACE_OVERFLOWED; @@ -164,8 +158,7 @@ static trace_status_t oocd_trace_status(struct etm_context *etm_ctx) if (status & 0x2) etm_ctx->capture_status |= TRACE_TRIGGERED; - if (status & 0x1) - { + if (status & 0x1) { etm_ctx->capture_status &= ~TRACE_RUNNING; etm_ctx->capture_status |= TRACE_COMPLETED; } @@ -202,26 +195,20 @@ static int oocd_trace_read_trace(struct etm_context *etm_ctx) oocd_trace_read_memory(oocd_trace, trace_data, first_frame, num_frames); if (etm_ctx->trace_depth > 0) - { free(etm_ctx->trace_data); - } etm_ctx->trace_depth = num_frames * 16; etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth); - for (i = 0; i < num_frames * 16; i++) - { + for (i = 0; i < num_frames * 16; i++) { etm_ctx->trace_data[i].pipestat = (trace_data[i] & 0x7); etm_ctx->trace_data[i].packet = (trace_data[i] & 0x78) >> 3; etm_ctx->trace_data[i].flags = 0; if ((trace_data[i] & 0x80) >> 7) - { etm_ctx->trace_data[i].flags |= ETMV1_TRACESYNC_CYCLE; - } - if (etm_ctx->trace_data[i].pipestat == STAT_TR) - { + if (etm_ctx->trace_data[i].pipestat == STAT_TR) { etm_ctx->trace_data[i].pipestat = etm_ctx->trace_data[i].packet & 0x7; etm_ctx->trace_data[i].flags |= ETMV1_TRIGGER_CYCLE; } @@ -239,16 +226,13 @@ static int oocd_trace_start_capture(struct etm_context *etm_ctx) uint32_t trigger_count; if (((etm_ctx->control & ETM_PORT_MODE_MASK) != ETM_PORT_NORMAL) - || ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_4BIT)) - { + || ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_4BIT)) { LOG_DEBUG("OpenOCD + trace only supports normal 4-bit ETM mode"); return ERROR_ETM_PORTMODE_NOT_SUPPORTED; } if ((etm_ctx->control & ETM_PORT_CLOCK_MASK) == ETM_PORT_HALF_CLOCK) - { control |= 0x2; /* half rate clock, capture at twice the clock rate */ - } /* OpenOCD + trace holds up to 16 million samples, * but trigger counts is set in multiples of 16 */ @@ -283,20 +267,16 @@ COMMAND_HANDLER(handle_oocd_trace_config_command) struct arm *arm; if (CMD_ARGC != 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (arm->etm) - { + if (arm->etm) { struct oocd_trace *oocd_trace = malloc(sizeof(struct oocd_trace)); arm->etm->capture_driver_priv = oocd_trace; @@ -304,11 +284,8 @@ COMMAND_HANDLER(handle_oocd_trace_config_command) /* copy name of TTY device used to communicate with OpenOCD + trace */ oocd_trace->tty = strndup(CMD_ARGV[1], 256); - } - else - { + } else LOG_ERROR("target has no ETM defined, OpenOCD + trace left unconfigured"); - } return ERROR_OK; } @@ -323,25 +300,22 @@ COMMAND_HANDLER(handle_oocd_trace_status_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (!arm->etm) - { + if (!arm->etm) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } - if (strcmp(arm->etm->capture_driver->name, "oocd_trace") != 0) - { + if (strcmp(arm->etm->capture_driver->name, "oocd_trace") != 0) { command_print(CMD_CTX, "current target's ETM capture driver isn't 'oocd_trace'"); return ERROR_FAIL; } - oocd_trace = (struct oocd_trace*)arm->etm->capture_driver_priv; + oocd_trace = (struct oocd_trace *)arm->etm->capture_driver_priv; oocd_trace_read_reg(oocd_trace, OOCD_TRACE_STATUS, &status); @@ -364,25 +338,22 @@ COMMAND_HANDLER(handle_oocd_trace_resync_command) target = get_current_target(CMD_CTX); arm = target_to_arm(target); - if (!is_arm(arm)) - { + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (!arm->etm) - { + if (!arm->etm) { command_print(CMD_CTX, "current target doesn't have an ETM configured"); return ERROR_FAIL; } - if (strcmp(arm->etm->capture_driver->name, "oocd_trace") != 0) - { + if (strcmp(arm->etm->capture_driver->name, "oocd_trace") != 0) { command_print(CMD_CTX, "current target's ETM capture driver isn't 'oocd_trace'"); return ERROR_FAIL; } - oocd_trace = (struct oocd_trace*)arm->etm->capture_driver_priv; + oocd_trace = (struct oocd_trace *)arm->etm->capture_driver_priv; cmd_array[0] = 0xf0; @@ -428,8 +399,7 @@ static const struct command_registration oocd_trace_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct etm_capture_driver oocd_trace_capture_driver = -{ +struct etm_capture_driver oocd_trace_capture_driver = { .name = "oocd_trace", .commands = oocd_trace_command_handlers, .init = oocd_trace_init, @@ -438,5 +408,3 @@ struct etm_capture_driver oocd_trace_capture_driver = .stop_capture = oocd_trace_stop_capture, .read_trace = oocd_trace_read_trace, }; - - diff --git a/src/target/oocd_trace.h b/src/target/oocd_trace.h index 6646933..538f1b2 100644 --- a/src/target/oocd_trace.h +++ b/src/target/oocd_trace.h @@ -17,14 +17,14 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef OOCD_TRACE_H #define OOCD_TRACE_H #include <termios.h> /* registers */ -enum -{ +enum { OOCD_TRACE_ID = 0x7, OOCD_TRACE_ADDRESS = 0x0, OOCD_TRACE_TRIGGER_COUNTER = 0x01, @@ -34,8 +34,7 @@ enum }; /* commands */ -enum -{ +enum { OOCD_TRACE_NOP = 0x0, OOCD_TRACE_READ_REG = 0x10, OOCD_TRACE_WRITE_REG = 0x18, @@ -44,8 +43,7 @@ enum OOCD_TRACE_RESYNC = 0xf0, }; -struct oocd_trace -{ +struct oocd_trace { struct etm_context *etm_ctx; char *tty; int tty_fd; diff --git a/src/target/register.c b/src/target/register.c index 355c860..65dc24f 100644 --- a/src/target/register.c +++ b/src/target/register.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -38,16 +39,14 @@ * may be separate registers associated with debug or trace modules. */ -struct reg* register_get_by_name(struct reg_cache *first, +struct reg *register_get_by_name(struct reg_cache *first, const char *name, bool search_all) { unsigned i; struct reg_cache *cache = first; - while (cache) - { - for (i = 0; i < cache->num_regs; i++) - { + while (cache) { + for (i = 0; i < cache->num_regs; i++) { if (strcmp(cache->reg_list[i].name, name) == 0) return &(cache->reg_list[i]); } @@ -61,7 +60,7 @@ struct reg* register_get_by_name(struct reg_cache *first, return NULL; } -struct reg_cache** register_get_last_cache_p(struct reg_cache **first) +struct reg_cache **register_get_last_cache_p(struct reg_cache **first) { struct reg_cache **cache_p = first; diff --git a/src/target/register.h b/src/target/register.h index 4b45fd3..cf08e4a 100644 --- a/src/target/register.h +++ b/src/target/register.h @@ -20,13 +20,13 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef REGISTER_H #define REGISTER_H struct target; -struct reg -{ +struct reg { const char *name; void *value; bool dirty; @@ -36,23 +36,21 @@ struct reg const struct reg_arch_type *type; }; -struct reg_cache -{ +struct reg_cache { const char *name; struct reg_cache *next; struct reg *reg_list; unsigned num_regs; }; -struct reg_arch_type -{ +struct reg_arch_type { int (*get)(struct reg *reg); int (*set)(struct reg *reg, uint8_t *buf); }; -struct reg* register_get_by_name(struct reg_cache *first, +struct reg *register_get_by_name(struct reg_cache *first, const char *name, bool search_all); -struct reg_cache** register_get_last_cache_p(struct reg_cache **first); +struct reg_cache **register_get_last_cache_p(struct reg_cache **first); void register_cache_invalidate(struct reg_cache *cache); void register_init_dummy(struct reg *reg); diff --git a/src/target/smp.c b/src/target/smp.c index eed3d8c..c0936ff 100644 --- a/src/target/smp.c +++ b/src/target/smp.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -29,7 +30,6 @@ #include "server/gdb_server.h" #include "smp.h" - /* implementation of new packet in gdb interface for smp feature */ /* */ /* j : smp status request */ @@ -53,9 +53,8 @@ /* Another way to test this packet is the usage of maintenance packet */ /* maint packet Jc01 */ /* maint packet jc */ - -static const char DIGITS[16] = "0123456789abcdef"; +static const char DIGITS[16] = "0123456789abcdef"; /* packet j :smp status request */ int gdb_read_smp_packet(struct connection *connection, @@ -66,15 +65,12 @@ int gdb_read_smp_packet(struct connection *connection, uint8_t *buffer; char *hex_buffer; int retval = ERROR_OK; - if (target->smp) - { - if (strstr(packet, "jc")) - { + if (target->smp) { + if (strstr(packet, "jc")) { hex_buffer = malloc(len * 2 + 1); buffer = (uint8_t *)&target->gdb_service->core[0]; uint32_t i; - for (i = 0; i < 4; i++) - { + for (i = 0; i < 4; i++) { uint8_t t = buffer[i]; hex_buffer[2 * i] = DIGITS[(t >> 4) & 0xf]; hex_buffer[2 * i + 1] = DIGITS[t & 0xf]; @@ -84,9 +80,8 @@ int gdb_read_smp_packet(struct connection *connection, free(hex_buffer); } - } - else - retval = gdb_put_packet(connection,"E01",3); + } else + retval = gdb_put_packet(connection, "E01", 3); return retval; } @@ -100,20 +95,15 @@ int gdb_write_smp_packet(struct connection *connection, int retval = ERROR_OK; /* skip command character */ - if (target->smp) - { - if (strstr(packet, "Jc")) - { - packet+=2; + if (target->smp) { + if (strstr(packet, "Jc")) { + packet += 2; coreid = strtoul(packet, &separator, 16); target->gdb_service->core[1] = coreid; retval = gdb_put_packet(connection, "OK", 2); } - } - else - { - retval = gdb_put_packet(connection,"E01",3); - } + } else + retval = gdb_put_packet(connection, "E01", 3); return retval; } diff --git a/src/target/smp.h b/src/target/smp.h index b8f0ea5..d8bb673 100644 --- a/src/target/smp.h +++ b/src/target/smp.h @@ -17,7 +17,9 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #include "server/server.h" + int gdb_read_smp_packet(struct connection *connection, char *packet, int packet_size); int gdb_write_smp_packet(struct connection *connection, diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c index f6f9247..2c4824c 100644 --- a/src/target/stm32_stlink.c +++ b/src/target/stm32_stlink.c @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -42,8 +43,8 @@ static inline struct stlink_interface_s *target_to_stlink(struct target *target) } static int stm32_stlink_load_core_reg_u32(struct target *target, - enum armv7m_regtype type, - uint32_t num, uint32_t *value) + enum armv7m_regtype type, + uint32_t num, uint32_t *value) { int retval; struct stlink_interface_s *stlink_if = target_to_stlink(target); @@ -57,8 +58,7 @@ static int stm32_stlink_load_core_reg_u32(struct target *target, switch (num) { case 0 ... 18: /* read a normal core register */ - retval = - stlink_if->layout->api->read_reg(stlink_if->fd, num, value); + retval = stlink_if->layout->api->read_reg(stlink_if->fd, num, value); if (retval != ERROR_OK) { LOG_ERROR("JTAG failure %i", retval); @@ -76,8 +76,7 @@ static int stm32_stlink_load_core_reg_u32(struct target *target, * in one Debug Core register. So say r0 and r2 docs; * it was removed from r1 docs, but still works. */ - retval = - stlink_if->layout->api->read_reg(stlink_if->fd, 20, value); + retval = stlink_if->layout->api->read_reg(stlink_if->fd, 20, value); switch (num) { case ARMV7M_PRIMASK: @@ -109,8 +108,8 @@ static int stm32_stlink_load_core_reg_u32(struct target *target, } static int stm32_stlink_store_core_reg_u32(struct target *target, - enum armv7m_regtype type, - uint32_t num, uint32_t value) + enum armv7m_regtype type, + uint32_t num, uint32_t value) { int retval; uint32_t reg; @@ -231,7 +230,7 @@ static int stm32_stlink_init_target(struct command_context *cmd_ctx, } static int stm32_stlink_target_create(struct target *target, - Jim_Interp *interp) + Jim_Interp *interp) { LOG_DEBUG("%s", __func__); @@ -467,10 +466,8 @@ static int stm32_stlink_halt(struct target *target) return ERROR_OK; } - if (target->state == TARGET_UNKNOWN) { - LOG_WARNING - ("target was in unknown state when halt was requested"); - } + if (target->state == TARGET_UNKNOWN) + LOG_WARNING("target was in unknown state when halt was requested"); res = stlink_if->layout->api->halt(stlink_if->fd); @@ -483,8 +480,8 @@ static int stm32_stlink_halt(struct target *target) } static int stm32_stlink_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, - int debug_execution) + uint32_t address, int handle_breakpoints, + int debug_execution) { int res; struct stlink_interface_s *stlink_if = target_to_stlink(target); @@ -494,7 +491,7 @@ static int stm32_stlink_resume(struct target *target, int current, struct reg *pc; LOG_DEBUG("%s %d %x %d %d", __func__, current, address, - handle_breakpoints, debug_execution); + handle_breakpoints, debug_execution); if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); @@ -526,8 +523,8 @@ static int stm32_stlink_resume(struct target *target, int current, breakpoint = breakpoint_find(target, resume_pc); if (breakpoint) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", - breakpoint->address, - breakpoint->unique_id); + breakpoint->address, + breakpoint->unique_id); cortex_m3_unset_breakpoint(target, breakpoint); res = stlink_if->layout->api->step(stlink_if->fd); @@ -552,7 +549,7 @@ static int stm32_stlink_resume(struct target *target, int current, } static int stm32_stlink_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + uint32_t address, int handle_breakpoints) { int res; struct stlink_interface_s *stlink_if = target_to_stlink(target); @@ -613,8 +610,8 @@ static int stm32_stlink_step(struct target *target, int current, } static int stm32_stlink_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, - uint8_t *buffer) + uint32_t size, uint32_t count, + uint8_t *buffer) { int res; uint32_t buffer_threshold = 128; @@ -644,13 +641,11 @@ static int stm32_stlink_read_memory(struct target *target, uint32_t address, c = count; if (size != 4) - res = - stlink_if->layout->api->read_mem8(stlink_if->fd, address, - c, dst); + res = stlink_if->layout->api->read_mem8(stlink_if->fd, + address, c, dst); else - res = - stlink_if->layout->api->read_mem32(stlink_if->fd, address, - c, (uint32_t *)dst); + res = stlink_if->layout->api->read_mem32(stlink_if->fd, + address, c, (uint32_t *)dst); if (res != ERROR_OK) return res; @@ -664,8 +659,8 @@ static int stm32_stlink_read_memory(struct target *target, uint32_t address, } static int stm32_stlink_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, - const uint8_t *buffer) + uint32_t size, uint32_t count, + const uint8_t *buffer) { int res; uint32_t buffer_threshold = 128; @@ -695,13 +690,11 @@ static int stm32_stlink_write_memory(struct target *target, uint32_t address, c = count; if (size != 4) - res = - stlink_if->layout->api->write_mem8(stlink_if->fd, address, - c, dst); + res = stlink_if->layout->api->write_mem8(stlink_if->fd, + address, c, dst); else - res = - stlink_if->layout->api->write_mem32(stlink_if->fd, address, - c, (uint32_t *)dst); + res = stlink_if->layout->api->write_mem32(stlink_if->fd, + address, c, (uint32_t *)dst); if (res != ERROR_OK) return res; @@ -715,8 +708,8 @@ static int stm32_stlink_write_memory(struct target *target, uint32_t address, } static int stm32_stlink_bulk_write_memory(struct target *target, - uint32_t address, uint32_t count, - const uint8_t *buffer) + uint32_t address, uint32_t count, + const uint8_t *buffer) { return stm32_stlink_write_memory(target, address, 4, count, buffer); } diff --git a/src/target/target.c b/src/target/target.c index ab094f9..5b2117d 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -35,6 +35,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -52,15 +53,14 @@ #include "image.h" #include "rtos/rtos.h" - static int target_read_buffer_default(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer); static int target_write_buffer_default(struct target *target, uint32_t address, uint32_t size, const uint8_t *buffer); static int target_array2mem(Jim_Interp *interp, struct target *target, - int argc, Jim_Obj *const *argv); + int argc, Jim_Obj * const *argv); static int target_mem2array(Jim_Interp *interp, struct target *target, - int argc, Jim_Obj *const *argv); + int argc, Jim_Obj * const *argv); static int target_register_user_commands(struct command_context *cmd_ctx); /* targets */ @@ -86,8 +86,7 @@ extern struct target_type testee_target; extern struct target_type avr32_ap7k_target; extern struct target_type stm32_stlink_target; -static struct target_type *target_types[] = -{ +static struct target_type *target_types[] = { &arm7tdmi_target, &arm9tdmi_target, &arm920t_target, @@ -112,9 +111,9 @@ static struct target_type *target_types[] = NULL, }; -struct target *all_targets = NULL; -static struct target_event_callback *target_event_callbacks = NULL; -static struct target_timer_callback *target_timer_callbacks = NULL; +struct target *all_targets; +static struct target_event_callback *target_event_callbacks; +static struct target_timer_callback *target_timer_callbacks; static const int polling_interval = 100; static const Jim_Nvp nvp_assert[] = { @@ -147,11 +146,10 @@ static const char *target_strerror_safe(int err) const Jim_Nvp *n; n = Jim_Nvp_value2name_simple(nvp_error_target, err); - if (n->name == NULL) { + if (n->name == NULL) return "unknown"; - } else { + else return n->name; - } } static const Jim_Nvp nvp_target_event[] = { @@ -214,7 +212,7 @@ static const Jim_Nvp nvp_target_state[] = { { .name = NULL, .value = -1 }, }; -static const Jim_Nvp nvp_target_debug_reason [] = { +static const Jim_Nvp nvp_target_debug_reason[] = { { .name = "debug-request" , .value = DBG_REASON_DBGRQ }, { .name = "breakpoint" , .value = DBG_REASON_BREAKPOINT }, { .name = "watchpoint" , .value = DBG_REASON_WATCHPOINT }, @@ -254,12 +252,11 @@ const char *debug_reason_name(struct target *t) return cp; } -const char * -target_state_name( struct target *t ) +const char *target_state_name(struct target *t) { const char *cp; cp = Jim_Nvp_value2name_simple(nvp_target_state, t->state)->name; - if( !cp ){ + if (!cp) { LOG_ERROR("Invalid target state: %d", (int)(t->state)); cp = "(*BUG*unknown*BUG*)"; } @@ -276,9 +273,8 @@ static int new_target_number(void) x = -1; t = all_targets; while (t) { - if (x < t->target_number) { + if (x < t->target_number) x = t->target_number; - } t = t->next; } return x + 1; @@ -354,32 +350,32 @@ static void target_buffer_set_u8(struct target *target, uint8_t *buffer, uint8_t void target_buffer_get_u32_array(struct target *target, const uint8_t *buffer, uint32_t count, uint32_t *dstbuf) { uint32_t i; - for(i = 0; i < count; i ++) - dstbuf[i] = target_buffer_get_u32(target,&buffer[i*4]); + for (i = 0; i < count; i++) + dstbuf[i] = target_buffer_get_u32(target, &buffer[i * 4]); } /* write a uint16_t array to a buffer in target memory endianness */ void target_buffer_get_u16_array(struct target *target, const uint8_t *buffer, uint32_t count, uint16_t *dstbuf) { uint32_t i; - for(i = 0; i < count; i ++) - dstbuf[i] = target_buffer_get_u16(target,&buffer[i*2]); + for (i = 0; i < count; i++) + dstbuf[i] = target_buffer_get_u16(target, &buffer[i * 2]); } /* write a uint32_t array to a buffer in target memory endianness */ void target_buffer_set_u32_array(struct target *target, uint8_t *buffer, uint32_t count, uint32_t *srcbuf) { uint32_t i; - for(i = 0; i < count; i ++) - target_buffer_set_u32(target,&buffer[i*4],srcbuf[i]); + for (i = 0; i < count; i++) + target_buffer_set_u32(target, &buffer[i * 4], srcbuf[i]); } /* write a uint16_t array to a buffer in target memory endianness */ void target_buffer_set_u16_array(struct target *target, uint8_t *buffer, uint32_t count, uint16_t *srcbuf) { uint32_t i; - for(i = 0; i < count; i ++) - target_buffer_set_u16(target,&buffer[i*2],srcbuf[i]); + for (i = 0; i < count; i++) + target_buffer_set_u16(target, &buffer[i * 2], srcbuf[i]); } /* return a pointer to a configured target; id is name or number */ @@ -419,21 +415,19 @@ static struct target *get_target_by_num(int num) struct target *target = all_targets; while (target) { - if (target->target_number == num) { + if (target->target_number == num) return target; - } target = target->next; } return NULL; } -struct target* get_current_target(struct command_context *cmd_ctx) +struct target *get_current_target(struct command_context *cmd_ctx) { struct target *target = get_target_by_num(cmd_ctx->current_target); - if (target == NULL) - { + if (target == NULL) { LOG_ERROR("BUG: current_target out of bounds"); exit(-1); } @@ -446,8 +440,7 @@ int target_poll(struct target *target) int retval; /* We can't poll until after examine */ - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { /* Fail silently lest we pollute the log */ return ERROR_FAIL; } @@ -456,16 +449,12 @@ int target_poll(struct target *target) if (retval != ERROR_OK) return retval; - if (target->halt_issued) - { + if (target->halt_issued) { if (target->state == TARGET_HALTED) - { target->halt_issued = false; - } else - { + else { long long t = timeval_ms() - target->halt_issued_time; - if (t>1000) - { + if (t > 1000) { target->halt_issued = false; LOG_INFO("Halt timed out, wake up GDB."); target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT); @@ -480,8 +469,7 @@ int target_halt(struct target *target) { int retval; /* We can't poll until after examine */ - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -531,8 +519,7 @@ int target_resume(struct target *target, int current, uint32_t address, int hand int retval; /* We can't poll until after examine */ - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -541,7 +528,8 @@ int target_resume(struct target *target, int current, uint32_t address, int hand * we poll. The CPU can even halt at the current PC as a result of * a software breakpoint being inserted by (a bug?) the application. */ - if ((retval = target->type->resume(target, current, address, handle_breakpoints, debug_execution)) != ERROR_OK) + retval = target->type->resume(target, current, address, handle_breakpoints, debug_execution); + if (retval != ERROR_OK) return retval; return retval; @@ -573,7 +561,7 @@ static int target_process_reset(struct command_context *cmd_ctx, enum target_res if (retval != JIM_OK) { Jim_MakeErrorMessage(cmd_ctx->interp); - command_print(NULL,"%s\n", Jim_GetString(Jim_GetResult(cmd_ctx->interp), NULL)); + command_print(NULL, "%s\n", Jim_GetString(Jim_GetResult(cmd_ctx->interp), NULL)); return ERROR_FAIL; } @@ -581,9 +569,8 @@ static int target_process_reset(struct command_context *cmd_ctx, enum target_res retval = target_call_timer_callbacks_now(); struct target *target; - for (target = all_targets; target; target = target->next) { + for (target = all_targets; target; target = target->next) target->type->check_reset(target); - } return retval; } @@ -640,15 +627,15 @@ int target_examine(void) int retval = ERROR_OK; struct target *target; - for (target = all_targets; target; target = target->next) - { + for (target = all_targets; target; target = target->next) { /* defer examination, but don't skip it */ if (!target->tap->enabled) { jtag_register_event_callback(jtag_enable_callback, target); continue; } - if ((retval = target_examine_one(target)) != ERROR_OK) + retval = target_examine_one(target); + if (retval != ERROR_OK) return retval; } return retval; @@ -658,20 +645,20 @@ const char *target_type_name(struct target *target) return target->type->name; } -static int target_write_memory_imp(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) +static int target_write_memory_imp(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } return target->type->write_memory_imp(target, address, size, count, buffer); } -static int target_read_memory_imp(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int target_read_memory_imp(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -680,8 +667,7 @@ static int target_read_memory_imp(struct target *target, uint32_t address, uint3 static int target_soft_reset_halt_imp(struct target *target) { - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -712,8 +698,7 @@ int target_run_algorithm(struct target *target, { int retval = ERROR_FAIL; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); goto done; } @@ -749,8 +734,7 @@ int target_start_algorithm(struct target *target, { int retval = ERROR_FAIL; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); goto done; } @@ -843,7 +827,7 @@ int target_bulk_write_memory(struct target *target, int target_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - if ((target->state != TARGET_HALTED)&&(breakpoint->type!=BKPT_HARD)) { + if ((target->state != TARGET_HALTED) && (breakpoint->type != BKPT_HARD)) { LOG_WARNING("target %s is not halted", target->cmd_name); return ERROR_TARGET_NOT_HALTED; } @@ -902,7 +886,6 @@ int target_step(struct target *target, return target->type->step(target, current, address, handle_breakpoints); } - /** * Reset the @c examined flag for the given target. * Pure paranoia -- targets are zeroed on allocation. @@ -912,16 +895,14 @@ static void target_reset_examined(struct target *target) target->examined = false; } -static int -err_read_phys_memory(struct target *target, uint32_t address, +static int err_read_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { LOG_ERROR("Not implemented: %s", __func__); return ERROR_FAIL; } -static int -err_write_phys_memory(struct target *target, uint32_t address, +static int err_write_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { LOG_ERROR("Not implemented: %s", __func__); @@ -939,14 +920,13 @@ static int target_init_one(struct command_context *cmd_ctx, if (type->examine == NULL) type->examine = default_examine; - if (type->check_reset== NULL) + if (type->check_reset == NULL) type->check_reset = default_check_reset; assert(type->init_target != NULL); int retval = type->init_target(cmd_ctx, target); - if (ERROR_OK != retval) - { + if (ERROR_OK != retval) { LOG_ERROR("target '%s' init failed", target_name(target)); return retval; } @@ -971,37 +951,28 @@ static int target_init_one(struct command_context *cmd_ctx, /* Sanity-check MMU support ... stub in what we must, to help * implement it in stages, but warn if we need to do so. */ - if (type->mmu) - { - if (type->write_phys_memory == NULL) - { + if (type->mmu) { + if (type->write_phys_memory == NULL) { LOG_ERROR("type '%s' is missing write_phys_memory", type->name); type->write_phys_memory = err_write_phys_memory; } - if (type->read_phys_memory == NULL) - { + if (type->read_phys_memory == NULL) { LOG_ERROR("type '%s' is missing read_phys_memory", type->name); type->read_phys_memory = err_read_phys_memory; } - if (type->virt2phys == NULL) - { + if (type->virt2phys == NULL) { LOG_ERROR("type '%s' is missing virt2phys", type->name); type->virt2phys = identity_virt2phys; } - } - else - { + } else { /* Make sure no-MMU targets all behave the same: make no * distinction between physical and virtual addresses, and * ensure that virt2phys() is always an identity mapping. */ - if (type->write_phys_memory || type->read_phys_memory - || type->virt2phys) - { + if (type->write_phys_memory || type->read_phys_memory || type->virt2phys) LOG_WARNING("type '%s' has bad MMU hooks", type->name); - } type->mmu = no_mmu; type->write_phys_memory = type->write_memory; @@ -1023,8 +994,7 @@ static int target_init(struct command_context *cmd_ctx) struct target *target; int retval; - for (target = all_targets; target; target = target->next) - { + for (target = all_targets; target; target = target->next) { retval = target_init_one(cmd_ctx, target); if (ERROR_OK != retval) return retval; @@ -1052,9 +1022,8 @@ COMMAND_HANDLER(handle_target_init_command) if (CMD_ARGC != 0) return ERROR_COMMAND_SYNTAX_ERROR; - static bool target_initialized = false; - if (target_initialized) - { + static bool target_initialized; + if (target_initialized) { LOG_INFO("'target init' has already been called"); return ERROR_OK; } @@ -1068,17 +1037,15 @@ COMMAND_HANDLER(handle_target_init_command) return target_init(CMD_CTX); } -int target_register_event_callback(int (*callback)(struct target *target, enum target_event event, void *priv), void *priv) +int target_register_event_callback(int (*callback)(struct target *target, + enum target_event event, void *priv), void *priv) { struct target_event_callback **callbacks_p = &target_event_callbacks; if (callback == NULL) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - if (*callbacks_p) - { + if (*callbacks_p) { while ((*callbacks_p)->next) callbacks_p = &((*callbacks_p)->next); callbacks_p = &((*callbacks_p)->next); @@ -1098,12 +1065,9 @@ int target_register_timer_callback(int (*callback)(void *priv), int time_ms, int struct timeval now; if (callback == NULL) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - if (*callbacks_p) - { + if (*callbacks_p) { while ((*callbacks_p)->next) callbacks_p = &((*callbacks_p)->next); callbacks_p = &((*callbacks_p)->next); @@ -1118,8 +1082,7 @@ int target_register_timer_callback(int (*callback)(void *priv), int time_ms, int (*callbacks_p)->when.tv_usec = now.tv_usec + (time_ms % 1000) * 1000; time_ms -= (time_ms % 1000); (*callbacks_p)->when.tv_sec = now.tv_sec + (time_ms / 1000); - if ((*callbacks_p)->when.tv_usec > 1000000) - { + if ((*callbacks_p)->when.tv_usec > 1000000) { (*callbacks_p)->when.tv_usec = (*callbacks_p)->when.tv_usec - 1000000; (*callbacks_p)->when.tv_sec += 1; } @@ -1130,26 +1093,22 @@ int target_register_timer_callback(int (*callback)(void *priv), int time_ms, int return ERROR_OK; } -int target_unregister_event_callback(int (*callback)(struct target *target, enum target_event event, void *priv), void *priv) +int target_unregister_event_callback(int (*callback)(struct target *target, + enum target_event event, void *priv), void *priv) { struct target_event_callback **p = &target_event_callbacks; struct target_event_callback *c = target_event_callbacks; if (callback == NULL) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - while (c) - { + while (c) { struct target_event_callback *next = c->next; - if ((c->callback == callback) && (c->priv == priv)) - { + if ((c->callback == callback) && (c->priv == priv)) { *p = next; free(c); return ERROR_OK; - } - else + } else p = &(c->next); c = next; } @@ -1163,20 +1122,15 @@ static int target_unregister_timer_callback(int (*callback)(void *priv), void *p struct target_timer_callback *c = target_timer_callbacks; if (callback == NULL) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - while (c) - { + while (c) { struct target_timer_callback *next = c->next; - if ((c->callback == callback) && (c->priv == priv)) - { + if ((c->callback == callback) && (c->priv == priv)) { *p = next; free(c); return ERROR_OK; - } - else + } else p = &(c->next); c = next; } @@ -1189,20 +1143,17 @@ int target_call_event_callbacks(struct target *target, enum target_event event) struct target_event_callback *callback = target_event_callbacks; struct target_event_callback *next_callback; - if (event == TARGET_EVENT_HALTED) - { + if (event == TARGET_EVENT_HALTED) { /* execute early halted first */ target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT); } - LOG_DEBUG("target event %i (%s)", - event, - Jim_Nvp_value2name_simple(nvp_target_event, event)->name); + LOG_DEBUG("target event %i (%s)", event, + Jim_Nvp_value2name_simple(nvp_target_event, event)->name); target_handle_event(target, event); - while (callback) - { + while (callback) { next_callback = callback->next; callback->callback(target, event, callback->priv); callback = next_callback; @@ -1218,8 +1169,7 @@ static int target_timer_callback_periodic_restart( cb->when.tv_usec = now->tv_usec + (time_ms % 1000) * 1000; time_ms -= (time_ms % 1000); cb->when.tv_sec = now->tv_sec + time_ms / 1000; - if (cb->when.tv_usec > 1000000) - { + if (cb->when.tv_usec > 1000000) { cb->when.tv_usec = cb->when.tv_usec - 1000000; cb->when.tv_sec += 1; } @@ -1245,9 +1195,8 @@ static int target_call_timer_callbacks_check_time(int checktime) gettimeofday(&now, NULL); struct target_timer_callback *callback = target_timer_callbacks; - while (callback) - { - // cleaning up may unregister and free this callback + while (callback) { + /* cleaning up may unregister and free this callback */ struct target_timer_callback *next_callback = callback->next; bool call_it = callback->callback && @@ -1256,8 +1205,7 @@ static int target_call_timer_callbacks_check_time(int checktime) (now.tv_sec == callback->when.tv_sec && now.tv_usec >= callback->when.tv_usec)); - if (call_it) - { + if (call_it) { int retval = target_call_timer_callback(callback, &now); if (retval != ERROR_OK) return retval; @@ -1286,16 +1234,13 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w struct working_area *new_wa = NULL; /* Reevaluate working area address based on MMU state*/ - if (target->working_areas == NULL) - { + if (target->working_areas == NULL) { int retval; int enabled; retval = target->type->mmu(target, &enabled); if (retval != ERROR_OK) - { return retval; - } if (!enabled) { if (target->working_area_phys_spec) { @@ -1323,17 +1268,14 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w } /* only allocate multiples of 4 byte */ - if (size % 4) - { + if (size % 4) { LOG_ERROR("BUG: code tried to allocate unaligned number of bytes (0x%08x), padding", ((unsigned)(size))); size = (size + 3) & (~3); } /* see if there's already a matching working area */ - while (c) - { - if ((c->free) && (c->size == size)) - { + while (c) { + if ((c->free) && (c->size == size)) { new_wa = c; break; } @@ -1341,15 +1283,13 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w } /* if not, allocate a new one */ - if (!new_wa) - { + if (!new_wa) { struct working_area **p = &target->working_areas; uint32_t first_free = target->working_area; uint32_t free_size = target->working_area_size; c = target->working_areas; - while (c) - { + while (c) { first_free += c->size; free_size -= c->size; p = &c->next; @@ -1357,9 +1297,7 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w } if (free_size < size) - { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } LOG_DEBUG("allocated new working area at address 0x%08x", (unsigned)first_free); @@ -1368,21 +1306,18 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w new_wa->size = size; new_wa->address = first_free; - if (target->backup_working_area) - { + if (target->backup_working_area) { int retval; new_wa->backup = malloc(new_wa->size); - if ((retval = target_read_memory(target, new_wa->address, 4, new_wa->size / 4, new_wa->backup)) != ERROR_OK) - { + retval = target_read_memory(target, new_wa->address, 4, + new_wa->size / 4, new_wa->backup); + if (retval != ERROR_OK) { free(new_wa->backup); free(new_wa); return retval; } - } - else - { + } else new_wa->backup = NULL; - } /* put new entry in list */ *p = new_wa; @@ -1404,9 +1339,7 @@ int target_alloc_working_area(struct target *target, uint32_t size, struct worki retval = target_alloc_working_area_try(target, size, area); if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) - { LOG_WARNING("not enough working area available(requested %u)", (unsigned)(size)); - } return retval; } @@ -1416,10 +1349,10 @@ static int target_free_working_area_restore(struct target *target, struct workin if (area->free) return ERROR_OK; - if (restore && target->backup_working_area) - { - int retval; - if ((retval = target_write_memory(target, area->address, 4, area->size / 4, area->backup)) != ERROR_OK) + if (restore && target->backup_working_area) { + int retval = target_write_memory(target, + area->address, 4, area->size / 4, area->backup); + if (retval != ERROR_OK) return retval; } @@ -1444,8 +1377,7 @@ static void target_free_all_working_areas_restore(struct target *target, int res { struct working_area *c = target->working_areas; - while (c) - { + while (c) { struct working_area *next = c->next; target_free_working_area_restore(target, c, restore); @@ -1468,13 +1400,12 @@ void target_free_all_working_areas(struct target *target) int target_arch_state(struct target *target) { int retval; - if (target == NULL) - { + if (target == NULL) { LOG_USER("No target has been configured"); return ERROR_OK; } - LOG_USER("target state: %s", target_state_name( target )); + LOG_USER("target state: %s", target_state_name(target)); if (target->state != TARGET_HALTED) return ERROR_OK; @@ -1490,20 +1421,17 @@ int target_arch_state(struct target *target) int target_write_buffer(struct target *target, uint32_t address, uint32_t size, const uint8_t *buffer) { LOG_DEBUG("writing buffer of %i byte at 0x%8.8x", - (int)size, (unsigned)address); + (int)size, (unsigned)address); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } - if (size == 0) { + if (size == 0) return ERROR_OK; - } - if ((address + size - 1) < address) - { + if ((address + size - 1) < address) { /* GDB can request this when e.g. PC is 0xfffffffc*/ LOG_ERROR("address + size wrapped(0x%08x, 0x%08x)", (unsigned)address, @@ -1519,19 +1447,17 @@ static int target_write_buffer_default(struct target *target, uint32_t address, int retval = ERROR_OK; if (((address % 2) == 0) && (size == 2)) - { return target_write_memory(target, address, 2, 1, buffer); - } /* handle unaligned head bytes */ - if (address % 4) - { + if (address % 4) { uint32_t unaligned = 4 - (address % 4); if (unaligned > size) unaligned = size; - if ((retval = target_write_memory(target, address, 1, unaligned, buffer)) != ERROR_OK) + retval = target_write_memory(target, address, 1, unaligned, buffer); + if (retval != ERROR_OK) return retval; buffer += unaligned; @@ -1540,19 +1466,17 @@ static int target_write_buffer_default(struct target *target, uint32_t address, } /* handle aligned words */ - if (size >= 4) - { + if (size >= 4) { int aligned = size - (size % 4); /* use bulk writes above a certain limit. This may have to be changed */ - if (aligned > 128) - { - if ((retval = target->type->bulk_write_memory(target, address, aligned / 4, buffer)) != ERROR_OK) + if (aligned > 128) { + retval = target->type->bulk_write_memory(target, address, aligned / 4, buffer); + if (retval != ERROR_OK) return retval; - } - else - { - if ((retval = target_write_memory(target, address, 4, aligned / 4, buffer)) != ERROR_OK) + } else { + retval = target_write_memory(target, address, 4, aligned / 4, buffer); + if (retval != ERROR_OK) return retval; } @@ -1562,9 +1486,9 @@ static int target_write_buffer_default(struct target *target, uint32_t address, } /* handle tail writes of less than 4 bytes */ - if (size > 0) - { - if ((retval = target_write_memory(target, address, 1, size, buffer)) != ERROR_OK) + if (size > 0) { + retval = target_write_memory(target, address, 1, size, buffer); + if (retval != ERROR_OK) return retval; } @@ -1580,18 +1504,15 @@ int target_read_buffer(struct target *target, uint32_t address, uint32_t size, u LOG_DEBUG("reading buffer of %i byte at 0x%8.8x", (int)size, (unsigned)address); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } - if (size == 0) { + if (size == 0) return ERROR_OK; - } - if ((address + size - 1) < address) - { + if ((address + size - 1) < address) { /* GDB can request this when e.g. PC is 0xfffffffc*/ LOG_ERROR("address + size wrapped(0x%08" PRIx32 ", 0x%08" PRIx32 ")", address, @@ -1607,19 +1528,17 @@ static int target_read_buffer_default(struct target *target, uint32_t address, u int retval = ERROR_OK; if (((address % 2) == 0) && (size == 2)) - { return target_read_memory(target, address, 2, 1, buffer); - } /* handle unaligned head bytes */ - if (address % 4) - { + if (address % 4) { uint32_t unaligned = 4 - (address % 4); if (unaligned > size) unaligned = size; - if ((retval = target_read_memory(target, address, 1, unaligned, buffer)) != ERROR_OK) + retval = target_read_memory(target, address, 1, unaligned, buffer); + if (retval != ERROR_OK) return retval; buffer += unaligned; @@ -1628,11 +1547,11 @@ static int target_read_buffer_default(struct target *target, uint32_t address, u } /* handle aligned words */ - if (size >= 4) - { + if (size >= 4) { int aligned = size - (size % 4); - if ((retval = target_read_memory(target, address, 4, aligned / 4, buffer)) != ERROR_OK) + retval = target_read_memory(target, address, 4, aligned / 4, buffer); + if (retval != ERROR_OK) return retval; buffer += aligned; @@ -1641,9 +1560,8 @@ static int target_read_buffer_default(struct target *target, uint32_t address, u } /*prevent byte access when possible (avoid AHB access limitations in some cases)*/ - if(size >=2) - { - int aligned = size - (size%2); + if (size >= 2) { + int aligned = size - (size % 2); retval = target_read_memory(target, address, 2, aligned / 2, buffer); if (retval != ERROR_OK) return retval; @@ -1653,9 +1571,9 @@ static int target_read_buffer_default(struct target *target, uint32_t address, u size -= aligned; } /* handle tail writes of less than 4 bytes */ - if (size > 0) - { - if ((retval = target_read_memory(target, address, 1, size, buffer)) != ERROR_OK) + if (size > 0) { + retval = target_read_memory(target, address, 1, size, buffer); + if (retval != ERROR_OK) return retval; } @@ -1668,31 +1586,26 @@ int target_checksum_memory(struct target *target, uint32_t address, uint32_t siz int retval; uint32_t i; uint32_t checksum = 0; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } - if ((retval = target->type->checksum_memory(target, address, - size, &checksum)) != ERROR_OK) - { + retval = target->type->checksum_memory(target, address, size, &checksum); + if (retval != ERROR_OK) { buffer = malloc(size); - if (buffer == NULL) - { + if (buffer == NULL) { LOG_ERROR("error allocating buffer for section (%d bytes)", (int)size); return ERROR_COMMAND_SYNTAX_ERROR; } retval = target_read_buffer(target, address, size, buffer); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { free(buffer); return retval; } /* convert to target endianness */ - for (i = 0; i < (size/sizeof(uint32_t)); i++) - { + for (i = 0; i < (size/sizeof(uint32_t)); i++) { uint32_t target_data; target_data = target_buffer_get_u32(target, &buffer[i*sizeof(uint32_t)]); target_buffer_set_u32(target, &buffer[i*sizeof(uint32_t)], target_data); @@ -1710,8 +1623,7 @@ int target_checksum_memory(struct target *target, uint32_t address, uint32_t siz int target_blank_check_memory(struct target *target, uint32_t address, uint32_t size, uint32_t* blank) { int retval; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -1727,23 +1639,19 @@ int target_blank_check_memory(struct target *target, uint32_t address, uint32_t int target_read_u32(struct target *target, uint32_t address, uint32_t *value) { uint8_t value_buf[4]; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } int retval = target_read_memory(target, address, 4, 1, value_buf); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { *value = target_buffer_get_u32(target, value_buf); LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "", address, *value); - } - else - { + } else { *value = 0x0; LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", address); @@ -1755,23 +1663,19 @@ int target_read_u32(struct target *target, uint32_t address, uint32_t *value) int target_read_u16(struct target *target, uint32_t address, uint16_t *value) { uint8_t value_buf[2]; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } int retval = target_read_memory(target, address, 2, 1, value_buf); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { *value = target_buffer_get_u16(target, value_buf); LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%4.4x", address, *value); - } - else - { + } else { *value = 0x0; LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", address); @@ -1783,20 +1687,16 @@ int target_read_u16(struct target *target, uint32_t address, uint16_t *value) int target_read_u8(struct target *target, uint32_t address, uint8_t *value) { int retval = target_read_memory(target, address, 1, 1, value); - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%2.2x", address, *value); - } - else - { + } else { *value = 0x0; LOG_DEBUG("address: 0x%8.8" PRIx32 " failed", address); @@ -1809,8 +1709,7 @@ int target_write_u32(struct target *target, uint32_t address, uint32_t value) { int retval; uint8_t value_buf[4]; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -1820,10 +1719,9 @@ int target_write_u32(struct target *target, uint32_t address, uint32_t value) value); target_buffer_set_u32(target, value_buf, value); - if ((retval = target_write_memory(target, address, 4, 1, value_buf)) != ERROR_OK) - { + retval = target_write_memory(target, address, 4, 1, value_buf); + if (retval != ERROR_OK) LOG_DEBUG("failed: %i", retval); - } return retval; } @@ -1832,8 +1730,7 @@ int target_write_u16(struct target *target, uint32_t address, uint16_t value) { int retval; uint8_t value_buf[2]; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -1843,10 +1740,9 @@ int target_write_u16(struct target *target, uint32_t address, uint16_t value) value); target_buffer_set_u16(target, value_buf, value); - if ((retval = target_write_memory(target, address, 2, 1, value_buf)) != ERROR_OK) - { + retval = target_write_memory(target, address, 2, 1, value_buf); + if (retval != ERROR_OK) LOG_DEBUG("failed: %i", retval); - } return retval; } @@ -1854,8 +1750,7 @@ int target_write_u16(struct target *target, uint32_t address, uint16_t value) int target_write_u8(struct target *target, uint32_t address, uint8_t value) { int retval; - if (!target_was_examined(target)) - { + if (!target_was_examined(target)) { LOG_ERROR("Target not examined yet"); return ERROR_FAIL; } @@ -1863,10 +1758,9 @@ int target_write_u8(struct target *target, uint32_t address, uint8_t value) LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%2.2x", address, value); - if ((retval = target_write_memory(target, address, 1, 1, &value)) != ERROR_OK) - { + retval = target_write_memory(target, address, 1, 1, &value); + if (retval != ERROR_OK) LOG_DEBUG("failed: %i", retval); - } return retval; } @@ -1893,8 +1787,7 @@ static int find_target(struct command_context *cmd_ctx, const char *name) COMMAND_HANDLER(handle_targets_command) { int retval = ERROR_OK; - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { retval = find_target(CMD_CTX, CMD_ARGV[0]); if (retval == ERROR_OK) { /* we're done! */ @@ -1905,13 +1798,12 @@ COMMAND_HANDLER(handle_targets_command) struct target *target = all_targets; command_print(CMD_CTX, " TargetName Type Endian TapName State "); command_print(CMD_CTX, "-- ------------------ ---------- ------ ------------------ ------------"); - while (target) - { + while (target) { const char *state; char marker = ' '; if (target->tap->enabled) - state = target_state_name( target ); + state = target_state_name(target); else state = "tap-disabled"; @@ -1947,53 +1839,47 @@ static int runSrstDeasserted; static int sense_handler(void) { - static int prevSrstAsserted = 0; - static int prevPowerdropout = 0; + static int prevSrstAsserted; + static int prevPowerdropout; - int retval; - if ((retval = jtag_power_dropout(&powerDropout)) != ERROR_OK) + int retval = jtag_power_dropout(&powerDropout); + if (retval != ERROR_OK) return retval; int powerRestored; powerRestored = prevPowerdropout && !powerDropout; if (powerRestored) - { runPowerRestore = 1; - } long long current = timeval_ms(); - static long long lastPower = 0; + static long long lastPower; int waitMore = lastPower + 2000 > current; - if (powerDropout && !waitMore) - { + if (powerDropout && !waitMore) { runPowerDropout = 1; lastPower = current; } - if ((retval = jtag_srst_asserted(&srstAsserted)) != ERROR_OK) + retval = jtag_srst_asserted(&srstAsserted); + if (retval != ERROR_OK) return retval; int srstDeasserted; srstDeasserted = prevSrstAsserted && !srstAsserted; - static long long lastSrst = 0; + static long long lastSrst; waitMore = lastSrst + 2000 > current; - if (srstDeasserted && !waitMore) - { + if (srstDeasserted && !waitMore) { runSrstDeasserted = 1; lastSrst = current; } if (!prevSrstAsserted && srstAsserted) - { runSrstAsserted = 1; - } prevSrstAsserted = srstAsserted; prevPowerdropout = powerDropout; - if (srstDeasserted || powerRestored) - { + if (srstDeasserted || powerRestored) { /* Other than logging the event we can't do anything here. * Issuing a reset is a particularly bad idea as we might * be inside a reset already. @@ -2003,8 +1889,8 @@ static int sense_handler(void) return ERROR_OK; } -static int backoff_times = 0; -static int backoff_count = 0; +static int backoff_times; +static int backoff_count; /* process target state changes */ static int handle_target(void *priv) @@ -2012,16 +1898,14 @@ static int handle_target(void *priv) Jim_Interp *interp = (Jim_Interp *)priv; int retval = ERROR_OK; - if (!is_jtag_poll_safe()) - { + if (!is_jtag_poll_safe()) { /* polling is disabled currently */ return ERROR_OK; } /* we do not want to recurse here... */ - static int recursive = 0; - if (! recursive) - { + static int recursive; + if (!recursive) { recursive = 1; sense_handler(); /* danger! running these procedures can trigger srst assertions and power dropouts. @@ -2029,31 +1913,26 @@ static int handle_target(void *priv) * clearing the flags after running these events. */ int did_something = 0; - if (runSrstAsserted) - { + if (runSrstAsserted) { LOG_INFO("srst asserted detected, running srst_asserted proc."); Jim_Eval(interp, "srst_asserted"); did_something = 1; } - if (runSrstDeasserted) - { + if (runSrstDeasserted) { Jim_Eval(interp, "srst_deasserted"); did_something = 1; } - if (runPowerDropout) - { + if (runPowerDropout) { LOG_INFO("Power dropout detected, running power_dropout proc."); Jim_Eval(interp, "power_dropout"); did_something = 1; } - if (runPowerRestore) - { + if (runPowerRestore) { Jim_Eval(interp, "power_restore"); did_something = 1; } - if (did_something) - { + if (did_something) { /* clear detect flags */ sense_handler(); } @@ -2068,8 +1947,7 @@ static int handle_target(void *priv) recursive = 0; } - if (backoff_times > backoff_count) - { + if (backoff_times > backoff_count) { /* do not poll this time as we failed previously */ backoff_count++; return ERROR_OK; @@ -2081,24 +1959,22 @@ static int handle_target(void *priv) */ for (struct target *target = all_targets; is_jtag_poll_safe() && target; - target = target->next) - { + target = target->next) { if (!target->tap->enabled) continue; /* only poll target if we've got power and srst isn't asserted */ - if (!powerDropout && !srstAsserted) - { + if (!powerDropout && !srstAsserted) { /* polling may fail silently until the target has been examined */ - if ((retval = target_poll(target)) != ERROR_OK) - { + retval = target_poll(target); + if (retval != ERROR_OK) { /* 100ms polling interval. Increase interval between polling up to 5000ms */ - if (backoff_times * polling_interval < 5000) - { + if (backoff_times * polling_interval < 5000) { backoff_times *= 2; backoff_times++; } - LOG_USER("Polling target failed, GDB will be halted. Polling again in %dms", backoff_times * polling_interval); + LOG_USER("Polling target failed, GDB will be halted. Polling again in %dms", + backoff_times * polling_interval); /* Tell GDB to halt the debugger. This allows the user to * run monitor commands to handle the situation. @@ -2108,9 +1984,7 @@ static int handle_target(void *priv) } /* Since we succeeded, we reset backoff count */ if (backoff_times > 0) - { LOG_USER("Polling succeeded again"); - } backoff_times = 0; } } @@ -2130,21 +2004,18 @@ COMMAND_HANDLER(handle_reg_command) target = get_current_target(CMD_CTX); /* list all available registers for the current target */ - if (CMD_ARGC == 0) - { + if (CMD_ARGC == 0) { struct reg_cache *cache = target->reg_cache; count = 0; - while (cache) - { + while (cache) { unsigned i; command_print(CMD_CTX, "===== %s", cache->name); for (i = 0, reg = cache->reg_list; i < cache->num_regs; - i++, reg++, count++) - { + i++, reg++, count++) { /* only print cached values if they are valid */ if (reg->valid) { value = buf_to_str(reg->value, @@ -2170,20 +2041,16 @@ COMMAND_HANDLER(handle_reg_command) } /* access a single register by its ordinal number */ - if ((CMD_ARGV[0][0] >= '0') && (CMD_ARGV[0][0] <= '9')) - { + if ((CMD_ARGV[0][0] >= '0') && (CMD_ARGV[0][0] <= '9')) { unsigned num; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num); struct reg_cache *cache = target->reg_cache; count = 0; - while (cache) - { + while (cache) { unsigned i; - for (i = 0; i < cache->num_regs; i++) - { - if (count++ == num) - { + for (i = 0; i < cache->num_regs; i++) { + if (count++ == num) { reg = &cache->reg_list[i]; break; } @@ -2193,17 +2060,16 @@ COMMAND_HANDLER(handle_reg_command) cache = cache->next; } - if (!reg) - { - command_print(CMD_CTX, "%i is out of bounds, the current target has only %i registers (0 - %i)", num, count, count - 1); + if (!reg) { + command_print(CMD_CTX, "%i is out of bounds, the current target " + "has only %i registers (0 - %i)", num, count, count - 1); return ERROR_OK; } - } else /* access a single register by its name */ - { + } else { + /* access a single register by its name */ reg = register_get_by_name(target->reg_cache, CMD_ARGV[0], 1); - if (!reg) - { + if (!reg) { command_print(CMD_CTX, "register %s not found in current target", CMD_ARGV[0]); return ERROR_OK; } @@ -2212,15 +2078,13 @@ COMMAND_HANDLER(handle_reg_command) assert(reg != NULL); /* give clang a hint that we *know* reg is != NULL here */ /* display a register */ - if ((CMD_ARGC == 1) || ((CMD_ARGC == 2) && !((CMD_ARGV[1][0] >= '0') && (CMD_ARGV[1][0] <= '9')))) - { + if ((CMD_ARGC == 1) || ((CMD_ARGC == 2) && !((CMD_ARGV[1][0] >= '0') + && (CMD_ARGV[1][0] <= '9')))) { if ((CMD_ARGC == 2) && (strcmp(CMD_ARGV[1], "force") == 0)) reg->valid = 0; if (reg->valid == 0) - { reg->type->get(reg); - } value = buf_to_str(reg->value, reg->size, 16); command_print(CMD_CTX, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value); free(value); @@ -2228,8 +2092,7 @@ COMMAND_HANDLER(handle_reg_command) } /* set register value */ - if (CMD_ARGC == 2) - { + if (CMD_ARGC == 2) { uint8_t *buf = malloc(DIV_ROUND_UP(reg->size, 8)); if (buf == NULL) return ERROR_FAIL; @@ -2254,8 +2117,7 @@ COMMAND_HANDLER(handle_poll_command) int retval = ERROR_OK; struct target *target = get_current_target(CMD_CTX); - if (CMD_ARGC == 0) - { + if (CMD_ARGC == 0) { command_print(CMD_CTX, "background polling: %s", jtag_poll_get_enabled() ? "on" : "off"); command_print(CMD_CTX, "TAP: %s (%s)", @@ -2263,21 +2125,18 @@ COMMAND_HANDLER(handle_poll_command) target->tap->enabled ? "enabled" : "disabled"); if (!target->tap->enabled) return ERROR_OK; - if ((retval = target_poll(target)) != ERROR_OK) + retval = target_poll(target); + if (retval != ERROR_OK) return retval; - if ((retval = target_arch_state(target)) != ERROR_OK) + retval = target_arch_state(target); + if (retval != ERROR_OK) return retval; - } - else if (CMD_ARGC == 1) - { + } else if (CMD_ARGC == 1) { bool enable; COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable); jtag_poll_set_enabled(enable); - } - else - { + } else return ERROR_COMMAND_SYNTAX_ERROR; - } return retval; } @@ -2288,14 +2147,11 @@ COMMAND_HANDLER(handle_wait_halt_command) return ERROR_COMMAND_SYNTAX_ERROR; unsigned ms = 5000; - if (1 == CMD_ARGC) - { + if (1 == CMD_ARGC) { int retval = parse_uint(CMD_ARGV[0], &ms); if (ERROR_OK != retval) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - // convert seconds (given) to milliseconds (needed) + /* convert seconds (given) to milliseconds (needed) */ ms *= 1000; } @@ -2315,32 +2171,26 @@ int target_wait_state(struct target *target, enum target_state state, int ms) long long then = 0, cur; int once = 1; - for (;;) - { - if ((retval = target_poll(target)) != ERROR_OK) + for (;;) { + retval = target_poll(target); + if (retval != ERROR_OK) return retval; if (target->state == state) - { break; - } cur = timeval_ms(); - if (once) - { + if (once) { once = 0; then = timeval_ms(); LOG_DEBUG("waiting for target %s...", - Jim_Nvp_value2name_simple(nvp_target_state,state)->name); + Jim_Nvp_value2name_simple(nvp_target_state, state)->name); } if (cur-then > 500) - { keep_alive(); - } - if ((cur-then) > ms) - { + if ((cur-then) > ms) { LOG_ERROR("timed out while waiting for target %s", - Jim_Nvp_value2name_simple(nvp_target_state,state)->name); + Jim_Nvp_value2name_simple(nvp_target_state, state)->name); return ERROR_FAIL; } } @@ -2357,8 +2207,7 @@ COMMAND_HANDLER(handle_halt_command) if (ERROR_OK != retval) return retval; - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { unsigned wait_local; retval = parse_uint(CMD_ARGV[0], &wait_local); if (ERROR_OK != retval) @@ -2387,13 +2236,11 @@ COMMAND_HANDLER(handle_reset_command) return ERROR_COMMAND_SYNTAX_ERROR; enum target_reset_mode reset_mode = RESET_RUN; - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { const Jim_Nvp *n; n = Jim_Nvp_name2value_simple(nvp_reset_modes, CMD_ARGV[0]); - if ((n->name == NULL) || (n->value == RESET_UNKNOWN)) { + if ((n->name == NULL) || (n->value == RESET_UNKNOWN)) return ERROR_COMMAND_SYNTAX_ERROR; - } reset_mode = n->value; } @@ -2415,8 +2262,7 @@ COMMAND_HANDLER(handle_resume_command) * with one arguments, addr = CMD_ARGV[0], * handle breakpoints, not debugging */ uint32_t addr = 0; - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr); current = 0; } @@ -2436,8 +2282,7 @@ COMMAND_HANDLER(handle_step_command) * handle breakpoints, debugging */ uint32_t addr = 0; int current_pc = 1; - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr); current_pc = 0; } @@ -2459,19 +2304,23 @@ static void handle_md_output(struct command_context *cmd_ctx, const char *value_fmt; switch (size) { - case 4: value_fmt = "%8.8x "; break; - case 2: value_fmt = "%4.4x "; break; - case 1: value_fmt = "%2.2x "; break; + case 4: + value_fmt = "%8.8x "; + break; + case 2: + value_fmt = "%4.4x "; + break; + case 1: + value_fmt = "%2.2x "; + break; default: /* "can't happen", caller checked */ LOG_ERROR("invalid memory read size: %u", size); return; } - for (unsigned i = 0; i < count; i++) - { - if (i % line_modulo == 0) - { + for (unsigned i = 0; i < count; i++) { + if (i % line_modulo == 0) { output_len += snprintf(output + output_len, sizeof(output) - output_len, "0x%8.8x: ", @@ -2481,16 +2330,20 @@ static void handle_md_output(struct command_context *cmd_ctx, uint32_t value = 0; const uint8_t *value_ptr = buffer + i * size; switch (size) { - case 4: value = target_buffer_get_u32(target, value_ptr); break; - case 2: value = target_buffer_get_u16(target, value_ptr); break; - case 1: value = *value_ptr; + case 4: + value = target_buffer_get_u32(target, value_ptr); + break; + case 2: + value = target_buffer_get_u16(target, value_ptr); + break; + case 1: + value = *value_ptr; } output_len += snprintf(output + output_len, sizeof(output) - output_len, value_fmt, value); - if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) - { + if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) { command_print(cmd_ctx, "%s", output); output_len = 0; } @@ -2504,28 +2357,30 @@ COMMAND_HANDLER(handle_md_command) unsigned size = 0; switch (CMD_NAME[2]) { - case 'w': size = 4; break; - case 'h': size = 2; break; - case 'b': size = 1; break; - default: return ERROR_COMMAND_SYNTAX_ERROR; + case 'w': + size = 4; + break; + case 'h': + size = 2; + break; + case 'b': + size = 1; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } - bool physical=strcmp(CMD_ARGV[0], "phys")==0; + bool physical = strcmp(CMD_ARGV[0], "phys") == 0; int (*fn)(struct target *target, uint32_t address, uint32_t size_value, uint32_t count, uint8_t *buffer); - if (physical) - { + if (physical) { CMD_ARGC--; CMD_ARGV++; - fn=target_read_phys_memory; + fn = target_read_phys_memory; } else - { - fn=target_read_memory; - } + fn = target_read_memory; if ((CMD_ARGC < 1) || (CMD_ARGC > 2)) - { return ERROR_COMMAND_SYNTAX_ERROR; - } uint32_t address; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); @@ -2568,24 +2423,21 @@ static int target_fill_mem(struct target *target, * to fill large memory areas with any sane speed */ const unsigned chunk_size = 16384; uint8_t *target_buf = malloc(chunk_size * data_size); - if (target_buf == NULL) - { + if (target_buf == NULL) { LOG_ERROR("Out of memory"); return ERROR_FAIL; } - for (unsigned i = 0; i < chunk_size; i ++) - { - switch (data_size) - { + for (unsigned i = 0; i < chunk_size; i++) { + switch (data_size) { case 4: - target_buffer_set_u32(target, target_buf + i*data_size, b); + target_buffer_set_u32(target, target_buf + i * data_size, b); break; case 2: - target_buffer_set_u16(target, target_buf + i*data_size, b); + target_buffer_set_u16(target, target_buf + i * data_size, b); break; case 1: - target_buffer_set_u8(target, target_buf + i*data_size, b); + target_buffer_set_u8(target, target_buf + i * data_size, b); break; default: exit(-1); @@ -2594,19 +2446,14 @@ static int target_fill_mem(struct target *target, int retval = ERROR_OK; - for (unsigned x = 0; x < c; x += chunk_size) - { + for (unsigned x = 0; x < c; x += chunk_size) { unsigned current; current = c - x; if (current > chunk_size) - { current = chunk_size; - } retval = fn(target, address + x * data_size, data_size, current, target_buf); if (retval != ERROR_OK) - { break; - } /* avoid GDB timeouts */ keep_alive(); } @@ -2619,20 +2466,15 @@ static int target_fill_mem(struct target *target, COMMAND_HANDLER(handle_mw_command) { if (CMD_ARGC < 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - bool physical=strcmp(CMD_ARGV[0], "phys")==0; + bool physical = strcmp(CMD_ARGV[0], "phys") == 0; target_write_fn fn; - if (physical) - { + if (physical) { CMD_ARGC--; CMD_ARGV++; - fn=target_write_phys_memory; + fn = target_write_phys_memory; } else - { fn = target_write_memory_fast; - } if ((CMD_ARGC < 2) || (CMD_ARGC > 3)) return ERROR_COMMAND_SYNTAX_ERROR; @@ -2648,8 +2490,7 @@ COMMAND_HANDLER(handle_mw_command) struct target *target = get_current_target(CMD_CTX); unsigned wordsize; - switch (CMD_NAME[2]) - { + switch (CMD_NAME[2]) { case 'w': wordsize = 4; break; @@ -2674,26 +2515,21 @@ static COMMAND_HELPER(parse_load_image_command_CMD_ARGV, struct image *image, /* a base address isn't always necessary, * default to 0x0 (i.e. don't relocate) */ - if (CMD_ARGC >= 2) - { + if (CMD_ARGC >= 2) { uint32_t addr; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], addr); image->base_address = addr; image->base_address_set = 1; - } - else + } else image->base_address_set = 0; image->start_address_set = 0; if (CMD_ARGC >= 4) - { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], *min_address); - } - if (CMD_ARGC == 5) - { + if (CMD_ARGC == 5) { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], *max_address); - // use size (given) to find max (required) + /* use size (given) to find max (required) */ *max_address += *min_address; } @@ -2724,25 +2560,21 @@ COMMAND_HANDLER(handle_load_image_command) duration_start(&bench); if (image_open(&image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) - { return ERROR_OK; - } image_size = 0x0; retval = ERROR_OK; - for (i = 0; i < image.num_sections; i++) - { + for (i = 0; i < image.num_sections; i++) { buffer = malloc(image.sections[i].size); - if (buffer == NULL) - { + if (buffer == NULL) { command_print(CMD_CTX, "error allocating buffer for section (%d bytes)", (int)(image.sections[i].size)); break; } - if ((retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt)) != ERROR_OK) - { + retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt); + if (retval != ERROR_OK) { free(buffer); break; } @@ -2752,37 +2584,34 @@ COMMAND_HANDLER(handle_load_image_command) /* DANGER!!! beware of unsigned comparision here!!! */ - if ((image.sections[i].base_address + buf_cnt >= min_address)&& - (image.sections[i].base_address < max_address)) - { - if (image.sections[i].base_address < min_address) - { + if ((image.sections[i].base_address + buf_cnt >= min_address) && + (image.sections[i].base_address < max_address)) { + + if (image.sections[i].base_address < min_address) { /* clip addresses below */ offset += min_address-image.sections[i].base_address; length -= offset; } if (image.sections[i].base_address + buf_cnt > max_address) - { length -= (image.sections[i].base_address + buf_cnt)-max_address; - } - if ((retval = target_write_buffer(target, image.sections[i].base_address + offset, length, buffer + offset)) != ERROR_OK) - { + retval = target_write_buffer(target, + image.sections[i].base_address + offset, length, buffer + offset); + if (retval != ERROR_OK) { free(buffer); break; } image_size += length; command_print(CMD_CTX, "%u bytes written at address 0x%8.8" PRIx32 "", - (unsigned int)length, - image.sections[i].base_address + offset); + (unsigned int)length, + image.sections[i].base_address + offset); } free(buffer); } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) - { + if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD_CTX, "downloaded %" PRIu32 " bytes " "in %fs (%0.3f KiB/s)", image_size, duration_elapsed(&bench), duration_kbps(&bench, image_size)); @@ -2822,21 +2651,16 @@ COMMAND_HANDLER(handle_dump_image_command) duration_start(&bench); - while (size > 0) - { + while (size > 0) { size_t size_written; uint32_t this_run_size = (size > buf_size) ? buf_size : size; retval = target_read_buffer(target, address, this_run_size, buffer); if (retval != ERROR_OK) - { break; - } retval = fileio_write(&fileio, this_run_size, buffer, &size_written); if (retval != ERROR_OK) - { break; - } size -= this_run_size; address += this_run_size; @@ -2844,8 +2668,7 @@ COMMAND_HANDLER(handle_dump_image_command) free(buffer); - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) - { + if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { int filesize; retval = fileio_size(&fileio, &filesize); if (retval != ERROR_OK) @@ -2855,7 +2678,8 @@ COMMAND_HANDLER(handle_dump_image_command) duration_elapsed(&bench), duration_kbps(&bench, filesize)); } - if ((retvaltemp = fileio_close(&fileio)) != ERROR_OK) + retvaltemp = fileio_close(&fileio); + if (retvaltemp != ERROR_OK) return retvaltemp; return retval; @@ -2876,12 +2700,9 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify) struct target *target = get_current_target(CMD_CTX); if (CMD_ARGC < 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - if (!target) - { + if (!target) { LOG_ERROR("no target selected"); return ERROR_FAIL; } @@ -2889,98 +2710,81 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify) struct duration bench; duration_start(&bench); - if (CMD_ARGC >= 2) - { + if (CMD_ARGC >= 2) { uint32_t addr; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], addr); image.base_address = addr; image.base_address_set = 1; - } - else - { + } else { image.base_address_set = 0; image.base_address = 0x0; } image.start_address_set = 0; - if ((retval = image_open(&image, CMD_ARGV[0], (CMD_ARGC == 3) ? CMD_ARGV[2] : NULL)) != ERROR_OK) - { + retval = image_open(&image, CMD_ARGV[0], (CMD_ARGC == 3) ? CMD_ARGV[2] : NULL); + if (retval != ERROR_OK) return retval; - } image_size = 0x0; int diffs = 0; retval = ERROR_OK; - for (i = 0; i < image.num_sections; i++) - { + for (i = 0; i < image.num_sections; i++) { buffer = malloc(image.sections[i].size); - if (buffer == NULL) - { + if (buffer == NULL) { command_print(CMD_CTX, - "error allocating buffer for section (%d bytes)", - (int)(image.sections[i].size)); + "error allocating buffer for section (%d bytes)", + (int)(image.sections[i].size)); break; } - if ((retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt)) != ERROR_OK) - { + retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt); + if (retval != ERROR_OK) { free(buffer); break; } - if (verify) - { + if (verify) { /* calculate checksum of image */ retval = image_calculate_checksum(buffer, buf_cnt, &checksum); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { free(buffer); break; } retval = target_checksum_memory(target, image.sections[i].base_address, buf_cnt, &mem_checksum); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { free(buffer); break; } - if (checksum != mem_checksum) - { + if (checksum != mem_checksum) { /* failed crc checksum, fall back to a binary compare */ uint8_t *data; if (diffs == 0) - { LOG_ERROR("checksum mismatch - attempting binary compare"); - } - data = (uint8_t*)malloc(buf_cnt); + data = (uint8_t *)malloc(buf_cnt); /* Can we use 32bit word accesses? */ int size = 1; int count = buf_cnt; - if ((count % 4) == 0) - { + if ((count % 4) == 0) { size *= 4; count /= 4; } retval = target_read_memory(target, image.sections[i].base_address, size, count, data); - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { uint32_t t; - for (t = 0; t < buf_cnt; t++) - { - if (data[t] != buffer[t]) - { + for (t = 0; t < buf_cnt; t++) { + if (data[t] != buffer[t]) { command_print(CMD_CTX, "diff %d address 0x%08x. Was 0x%02x instead of 0x%02x", diffs, (unsigned)(t + image.sections[i].base_address), data[t], buffer[t]); - if (diffs++ >= 127) - { + if (diffs++ >= 127) { command_print(CMD_CTX, "More than 128 errors, the rest are not printed."); free(data); free(buffer); @@ -2992,8 +2796,7 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify) } free(data); } - } else - { + } else { command_print(CMD_CTX, "address 0x%08" PRIx32 " length 0x%08zx", image.sections[i].base_address, buf_cnt); @@ -3003,16 +2806,11 @@ static COMMAND_HELPER(handle_verify_image_command_internal, int verify) image_size += buf_cnt; } if (diffs > 0) - { command_print(CMD_CTX, "No more differences found."); - } done: if (diffs > 0) - { retval = ERROR_FAIL; - } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) - { + if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD_CTX, "verified %" PRIu32 " bytes " "in %fs (%0.3f KiB/s)", image_size, duration_elapsed(&bench), duration_kbps(&bench, image_size)); @@ -3037,33 +2835,27 @@ static int handle_bp_command_list(struct command_context *cmd_ctx) { struct target *target = get_current_target(cmd_ctx); struct breakpoint *breakpoint = target->breakpoints; - while (breakpoint) - { - if (breakpoint->type == BKPT_SOFT) - { - char* buf = buf_to_str(breakpoint->orig_instr, + while (breakpoint) { + if (breakpoint->type == BKPT_SOFT) { + char *buf = buf_to_str(breakpoint->orig_instr, breakpoint->length, 16); command_print(cmd_ctx, "IVA breakpoint: 0x%8.8" PRIx32 ", 0x%x, %i, 0x%s", breakpoint->address, breakpoint->length, breakpoint->set, buf); free(buf); - } - else - { + } else { if ((breakpoint->address == 0) && (breakpoint->asid != 0)) command_print(cmd_ctx, "Context breakpoint: 0x%8.8" PRIx32 ", 0x%x, %i", breakpoint->asid, breakpoint->length, breakpoint->set); - else if ((breakpoint->address != 0) && (breakpoint->asid != 0)) - { + else if ((breakpoint->address != 0) && (breakpoint->asid != 0)) { command_print(cmd_ctx, "Hybrid breakpoint(IVA): 0x%8.8" PRIx32 ", 0x%x, %i", breakpoint->address, breakpoint->length, breakpoint->set); command_print(cmd_ctx, "\t|--->linked with ContextID: 0x%8.8" PRIx32, breakpoint->asid); - } - else + } else command_print(cmd_ctx, "Breakpoint(IVA): 0x%8.8" PRIx32 ", 0x%x, %i", breakpoint->address, breakpoint->length, breakpoint->set); @@ -3079,35 +2871,27 @@ static int handle_bp_command_set(struct command_context *cmd_ctx, { struct target *target = get_current_target(cmd_ctx); - if (asid == 0) - { + if (asid == 0) { int retval = breakpoint_add(target, addr, length, hw); if (ERROR_OK == retval) command_print(cmd_ctx, "breakpoint set at 0x%8.8" PRIx32 "", addr); - else - { + else { LOG_ERROR("Failure setting breakpoint, the same address(IVA) is already used"); return retval; } - } - else if (addr == 0) - { + } else if (addr == 0) { int retval = context_breakpoint_add(target, asid, length, hw); if (ERROR_OK == retval) command_print(cmd_ctx, "Context breakpoint set at 0x%8.8" PRIx32 "", asid); - else - { + else { LOG_ERROR("Failure setting breakpoint, the same address(CONTEXTID) is already used"); return retval; } - } - else - { + } else { int retval = hybrid_breakpoint_add(target, addr, asid, length, hw); - if(ERROR_OK == retval) + if (ERROR_OK == retval) command_print(cmd_ctx, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid); - else - { + else { LOG_ERROR("Failure setting breakpoint, the same address is already used"); return retval; } @@ -3121,8 +2905,8 @@ COMMAND_HANDLER(handle_bp_command) uint32_t asid; uint32_t length; int hw = BKPT_SOFT; - switch(CMD_ARGC) - { + + switch (CMD_ARGC) { case 0: return handle_bp_command_list(CMD_CTX); @@ -3133,8 +2917,7 @@ COMMAND_HANDLER(handle_bp_command) return handle_bp_command_set(CMD_CTX, addr, asid, length, hw); case 3: - if(strcmp(CMD_ARGV[2], "hw") == 0) - { + if (strcmp(CMD_ARGV[2], "hw") == 0) { hw = BKPT_HARD; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr); @@ -3142,9 +2925,7 @@ COMMAND_HANDLER(handle_bp_command) asid = 0; return handle_bp_command_set(CMD_CTX, addr, asid, length, hw); - } - else if(strcmp(CMD_ARGV[2], "hw_ctx") == 0) - { + } else if (strcmp(CMD_ARGV[2], "hw_ctx") == 0) { hw = BKPT_HARD; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], asid); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); @@ -3182,12 +2963,10 @@ COMMAND_HANDLER(handle_wp_command) { struct target *target = get_current_target(CMD_CTX); - if (CMD_ARGC == 0) - { + if (CMD_ARGC == 0) { struct watchpoint *watchpoint = target->watchpoints; - while (watchpoint) - { + while (watchpoint) { command_print(CMD_CTX, "address: 0x%8.8" PRIx32 ", len: 0x%8.8" PRIx32 ", r/w/a: %i, value: 0x%8.8" PRIx32 @@ -3208,17 +2987,15 @@ COMMAND_HANDLER(handle_wp_command) uint32_t data_value = 0x0; uint32_t data_mask = 0xffffffff; - switch (CMD_ARGC) - { + switch (CMD_ARGC) { case 5: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], data_mask); - // fall through + /* fall through */ case 4: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], data_value); - // fall through + /* fall through */ case 3: - switch (CMD_ARGV[2][0]) - { + switch (CMD_ARGV[2][0]) { case 'r': type = WPT_READ; break; @@ -3232,7 +3009,7 @@ COMMAND_HANDLER(handle_wp_command) LOG_ERROR("invalid watchpoint mode ('%c')", CMD_ARGV[2][0]); return ERROR_COMMAND_SYNTAX_ERROR; } - // fall through + /* fall through */ case 2: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr); @@ -3264,7 +3041,6 @@ COMMAND_HANDLER(handle_rwp_command) return ERROR_OK; } - /** * Translate a virtual address to a physical address. * @@ -3298,8 +3074,7 @@ static void writeData(FILE *f, const void *data, size_t len) static void writeLong(FILE *f, int l) { int i; - for (i = 0; i < 4; i++) - { + for (i = 0; i < 4; i++) { char c = (l >> (i*8))&0xff; writeData(f, &c, 1); } @@ -3330,16 +3105,11 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, const char *filenam /* figure out bucket size */ uint32_t min = samples[0]; uint32_t max = samples[0]; - for (i = 0; i < sampleNum; i++) - { + for (i = 0; i < sampleNum; i++) { if (min > samples[i]) - { min = samples[i]; - } if (max < samples[i]) - { max = samples[i]; - } } int addressSpace = (max - min + 1); @@ -3348,31 +3118,27 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, const char *filenam static const uint32_t maxBuckets = 16 * 1024; /* maximum buckets. */ uint32_t length = addressSpace; if (length > maxBuckets) - { length = maxBuckets; - } int *buckets = malloc(sizeof(int)*length); - if (buckets == NULL) - { + if (buckets == NULL) { fclose(f); return; } - memset(buckets, 0, sizeof(int)*length); - for (i = 0; i < sampleNum;i++) - { + memset(buckets, 0, sizeof(int) * length); + for (i = 0; i < sampleNum; i++) { uint32_t address = samples[i]; - long long a = address-min; - long long b = length-1; - long long c = addressSpace-1; - int index_t = (a*b)/c; /* danger!!!! int32 overflows */ + long long a = address - min; + long long b = length - 1; + long long c = addressSpace - 1; + int index_t = (a * b) / c; /* danger!!!! int32 overflows */ buckets[index_t]++; } /* append binary memory gmon.out &profile_hist_hdr ((char*)&profile_hist_hdr + sizeof(struct gmon_hist_hdr)) */ - writeLong(f, min); /* low_pc */ + writeLong(f, min); /* low_pc */ writeLong(f, max); /* high_pc */ writeLong(f, length); /* # of samples */ - writeLong(f, 100); /* KLUDGE! We lie, ca. 100Hz best case. */ + writeLong(f, 100); /* KLUDGE! We lie, ca. 100Hz best case. */ writeString(f, "seconds"); for (i = 0; i < (15-strlen("seconds")); i++) writeData(f, &zero, 1); @@ -3380,27 +3146,21 @@ static void writeGmon(uint32_t *samples, uint32_t sampleNum, const char *filenam /*append binary memory gmon.out profile_hist_data (profile_hist_data + profile_hist_hdr.hist_size) */ - char *data = malloc(2*length); - if (data != NULL) - { - for (i = 0; i < length;i++) - { + char *data = malloc(2 * length); + if (data != NULL) { + for (i = 0; i < length; i++) { int val; val = buckets[i]; if (val > 65535) - { val = 65535; - } - data[i*2]=val&0xff; - data[i*2 + 1]=(val >> 8)&0xff; + data[i * 2] = val&0xff; + data[i * 2 + 1] = (val >> 8) & 0xff; } free(buckets); writeData(f, data, length * 2); free(data); } else - { free(buckets); - } fclose(f); } @@ -3414,9 +3174,7 @@ COMMAND_HANDLER(handle_profile_command) gettimeofday(&timeout, NULL); if (CMD_ARGC != 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } unsigned offset; COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], offset); @@ -3440,50 +3198,46 @@ COMMAND_HANDLER(handle_profile_command) struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1); int retval = ERROR_OK; - for (;;) - { + for (;;) { target_poll(target); - if (target->state == TARGET_HALTED) - { - uint32_t t=*((uint32_t *)reg->value); - samples[numSamples++]=t; - retval = target_resume(target, 1, 0, 0, 0); /* current pc, addr = 0, do not handle breakpoints, not debugging */ + if (target->state == TARGET_HALTED) { + uint32_t t = *((uint32_t *)reg->value); + samples[numSamples++] = t; + /* current pc, addr = 0, do not handle breakpoints, not debugging */ + retval = target_resume(target, 1, 0, 0, 0); target_poll(target); alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */ - } else if (target->state == TARGET_RUNNING) - { + } else if (target->state == TARGET_RUNNING) { /* We want to quickly sample the PC. */ - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) { free(samples); return retval; } - } else - { + } else { command_print(CMD_CTX, "Target not halted or running"); retval = ERROR_OK; break; } if (retval != ERROR_OK) - { break; - } gettimeofday(&now, NULL); - if ((numSamples >= maxSample) || ((now.tv_sec >= timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec))) - { + if ((numSamples >= maxSample) || ((now.tv_sec >= timeout.tv_sec) + && (now.tv_usec >= timeout.tv_usec))) { command_print(CMD_CTX, "Profiling completed. %d samples.", numSamples); - if ((retval = target_poll(target)) != ERROR_OK) - { + retval = target_poll(target); + if (retval != ERROR_OK) { free(samples); return retval; } - if (target->state == TARGET_HALTED) - { - target_resume(target, 1, 0, 0, 0); /* current pc, addr = 0, do not handle breakpoints, not debugging */ + if (target->state == TARGET_HALTED) { + /* current pc, addr = 0, do not handle + * breakpoints, not debugging */ + target_resume(target, 1, 0, 0, 0); } - if ((retval = target_poll(target)) != ERROR_OK) - { + retval = target_poll(target); + if (retval != ERROR_OK) { free(samples); return retval; } @@ -3497,7 +3251,7 @@ COMMAND_HANDLER(handle_profile_command) return retval; } -static int new_int_array_element(Jim_Interp * interp, const char *varname, int idx, uint32_t val) +static int new_int_array_element(Jim_Interp *interp, const char *varname, int idx, uint32_t val) { char *namebuf; Jim_Obj *nameObjPtr, *valObjPtr; @@ -3509,8 +3263,7 @@ static int new_int_array_element(Jim_Interp * interp, const char *varname, int i nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); valObjPtr = Jim_NewIntObj(interp, val); - if (!nameObjPtr || !valObjPtr) - { + if (!nameObjPtr || !valObjPtr) { free(namebuf); return JIM_ERR; } @@ -3531,16 +3284,15 @@ static int jim_mem2array(Jim_Interp *interp, int argc, Jim_Obj *const *argv) struct target *target; context = current_command_context(interp); - assert (context != NULL); + assert(context != NULL); target = get_current_target(context); - if (target == NULL) - { + if (target == NULL) { LOG_ERROR("mem2array: no current target"); return JIM_ERR; } - return target_mem2array(interp, target, argc-1, argv + 1); + return target_mem2array(interp, target, argc - 1, argv + 1); } static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv) @@ -3569,20 +3321,17 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, e = Jim_GetLong(interp, argv[1], &l); width = l; - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } e = Jim_GetLong(interp, argv[2], &l); addr = l; - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } e = Jim_GetLong(interp, argv[3], &l); len = l; - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } switch (width) { case 8: width = 1; @@ -3645,9 +3394,8 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, /* Slurp... in buffer size chunks */ count = len; /* in objects.. */ - if (count > (buffersize/width)) { - count = (buffersize/width); - } + if (count > (buffersize / width)) + count = (buffersize / width); retval = target_read_memory(target, addr, width, count, buffer); if (retval != ERROR_OK) { @@ -3662,7 +3410,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, break; } else { v = 0; /* shut up gcc */ - for (i = 0 ;i < count ;i++, n++) { + for (i = 0; i < count ; i++, n++) { switch (width) { case 4: v = target_buffer_get_u32(target, &buffer[i*width]); @@ -3687,7 +3435,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, return e; } -static int get_int_array_element(Jim_Interp * interp, const char *varname, int idx, uint32_t *val) +static int get_int_array_element(Jim_Interp *interp, const char *varname, int idx, uint32_t *val) { char *namebuf; Jim_Obj *nameObjPtr, *valObjPtr; @@ -3699,8 +3447,7 @@ static int get_int_array_element(Jim_Interp * interp, const char *varname, int i return JIM_ERR; nameObjPtr = Jim_NewStringObj(interp, namebuf, -1); - if (!nameObjPtr) - { + if (!nameObjPtr) { free(namebuf); return JIM_ERR; } @@ -3724,7 +3471,7 @@ static int jim_array2mem(Jim_Interp *interp, int argc, Jim_Obj *const *argv) struct target *target; context = current_command_context(interp); - assert (context != NULL); + assert(context != NULL); target = get_current_target(context); if (target == NULL) { @@ -3732,7 +3479,7 @@ static int jim_array2mem(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return JIM_ERR; } - return target_array2mem(interp,target, argc-1, argv + 1); + return target_array2mem(interp, target, argc-1, argv + 1); } static int target_array2mem(Jim_Interp *interp, struct target *target, @@ -3762,20 +3509,17 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, e = Jim_GetLong(interp, argv[1], &l); width = l; - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } e = Jim_GetLong(interp, argv[2], &l); addr = l; - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } e = Jim_GetLong(interp, argv[3], &l); len = l; - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } switch (width) { case 8: width = 1; @@ -3788,23 +3532,27 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, break; default: Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "Invalid width param, must be 8/16/32", NULL); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "Invalid width param, must be 8/16/32", NULL); return JIM_ERR; } if (len == 0) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: zero width read?", NULL); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "array2mem: zero width read?", NULL); return JIM_ERR; } if ((addr + (len * width)) < addr) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: addr + len - wraps to zero?", NULL); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "array2mem: addr + len - wraps to zero?", NULL); return JIM_ERR; } /* absurd transfer size? */ if (len > 65536) { Jim_SetResult(interp, Jim_NewEmptyStringObj(interp)); - Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: absurd > 64K item request", NULL); + Jim_AppendStrings(interp, Jim_GetResult(interp), + "array2mem: absurd > 64K item request", NULL); return JIM_ERR; } @@ -3838,19 +3586,18 @@ static int target_array2mem(Jim_Interp *interp, struct target *target, /* Slurp... in buffer size chunks */ count = len; /* in objects.. */ - if (count > (buffersize/width)) { - count = (buffersize/width); - } + if (count > (buffersize / width)) + count = (buffersize / width); v = 0; /* shut up gcc */ - for (i = 0 ;i < count ;i++, n++) { + for (i = 0; i < count; i++, n++) { get_int_array_element(interp, varname, n, &v); switch (width) { case 4: - target_buffer_set_u32(target, &buffer[i*width], v); + target_buffer_set_u32(target, &buffer[i * width], v); break; case 2: - target_buffer_set_u16(target, &buffer[i*width], v); + target_buffer_set_u16(target, &buffer[i * width], v); break; case 1: buffer[i] = v & 0x0ff; @@ -3896,10 +3643,9 @@ void target_handle_event(struct target *target, enum target_event e) e, Jim_Nvp_value2name_simple(nvp_target_event, e)->name, Jim_GetString(teap->body, NULL)); - if (Jim_EvalObj(teap->interp, teap->body) != JIM_OK) - { + if (Jim_EvalObj(teap->interp, teap->body) != JIM_OK) { Jim_MakeErrorMessage(teap->interp); - command_print(NULL,"%s\n", Jim_GetString(Jim_GetResult(teap->interp), NULL)); + command_print(NULL, "%s\n", Jim_GetString(Jim_GetResult(teap->interp), NULL)); } } } @@ -3990,7 +3736,7 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) "not settable: %s", n->name); return JIM_ERR; } else { - no_params: +no_params: if (goi->argc != 0) { Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, @@ -4032,9 +3778,8 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) teap = target->event_action; /* replace existing? */ while (teap) { - if (teap->event == (enum target_event)n->value) { + if (teap->event == (enum target_event)n->value) break; - } teap = teap->next; } @@ -4048,9 +3793,8 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) teap->event = n->value; teap->interp = goi->interp; Jim_GetOpt_Obj(goi, &o); - if (teap->body) { + if (teap->body) Jim_DecrRefCount(teap->interp, teap->body); - } teap->body = Jim_DuplicateObj(goi->interp, o); /* * FIXME: @@ -4064,8 +3808,7 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) */ Jim_IncrRefCount(teap->body); - if (!replace) - { + if (!replace) { /* add to head of event list */ teap->next = target->event_action; target->event_action = teap; @@ -4073,11 +3816,10 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) Jim_SetEmptyResult(goi->interp); } else { /* get */ - if (teap == NULL) { + if (teap == NULL) Jim_SetEmptyResult(goi->interp); - } else { + else Jim_SetResult(goi->interp, Jim_DuplicateObj(goi->interp, teap->body)); - } } } /* loop for more */ @@ -4087,15 +3829,13 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) if (goi->isconfigure) { target_free_all_working_areas(target); e = Jim_GetOpt_Wide(goi, &w); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } target->working_area_virt = w; target->working_area_virt_spec = true; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_virt)); /* loop for more */ @@ -4105,15 +3845,13 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) if (goi->isconfigure) { target_free_all_working_areas(target); e = Jim_GetOpt_Wide(goi, &w); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } target->working_area_phys = w; target->working_area_phys_spec = true; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_phys)); /* loop for more */ @@ -4123,14 +3861,12 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) if (goi->isconfigure) { target_free_all_working_areas(target); e = Jim_GetOpt_Wide(goi, &w); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } target->working_area_size = w; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_size)); /* loop for more */ @@ -4140,15 +3876,13 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) if (goi->isconfigure) { target_free_all_working_areas(target); e = Jim_GetOpt_Wide(goi, &w); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } /* make this exactly 1 or 0 */ target->backup_working_area = (!!w); } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->backup_working_area)); /* loop for more e*/ @@ -4164,9 +3898,8 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) } target->endianness = n->value; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } n = Jim_Nvp_value2name_simple(nvp_target_endian, target->endianness); if (n->name == NULL) { @@ -4185,33 +3918,29 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) n->name); return JIM_ERR; } - if (target->variant) { + if (target->variant) free((void *)(target->variant)); - } e = Jim_GetOpt_String(goi, &cp, NULL); if (e != JIM_OK) return e; target->variant = strdup(cp); } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } - Jim_SetResultString(goi->interp, target->variant,-1); + Jim_SetResultString(goi->interp, target->variant, -1); /* loop for more */ break; case TCFG_COREID: if (goi->isconfigure) { e = Jim_GetOpt_Wide(goi, &w); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } target->coreid = (int32_t)w; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_size)); /* loop for more */ @@ -4223,19 +3952,16 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) struct jtag_tap *tap; target_free_all_working_areas(target); e = Jim_GetOpt_Obj(goi, &o_t); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } tap = jtag_tap_by_jim_obj(goi->interp, o_t); - if (tap == NULL) { + if (tap == NULL) return JIM_ERR; - } /* make this exactly 1 or 0 */ target->tap = tap; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResultString(goi->interp, target->tap->dotted_name, -1); /* loop for more e*/ @@ -4243,15 +3969,13 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) case TCFG_DBGBASE: if (goi->isconfigure) { e = Jim_GetOpt_Wide(goi, &w); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } target->dbgbase = (uint32_t)w; target->dbgbase_set = true; } else { - if (goi->argc != 0) { + if (goi->argc != 0) goto no_params; - } } Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->dbgbase)); /* loop for more */ @@ -4260,11 +3984,9 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) case TCFG_RTOS: /* RTOS */ { - int result = rtos_create( goi, target ); - if ( result != JIM_OK ) - { + int result = rtos_create(goi, target); + if (result != JIM_OK) return result; - } } /* loop for more */ break; @@ -4276,16 +3998,14 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target) return JIM_OK; } -static int -jim_target_configure(Jim_Interp *interp, int argc, Jim_Obj *const *argv) +static int jim_target_configure(Jim_Interp *interp, int argc, Jim_Obj * const *argv) { Jim_GetOptInfo goi; Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); goi.isconfigure = !strcmp(Jim_GetString(argv[0], NULL), "configure"); int need_args = 1 + goi.isconfigure; - if (goi.argc < need_args) - { + if (goi.argc < need_args) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, goi.isconfigure ? "missing: -option VALUE ..." @@ -4303,8 +4023,7 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv) Jim_GetOptInfo goi; Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc < 2 || goi.argc > 4) - { + if (goi.argc < 2 || goi.argc > 4) { Jim_SetResultFormatted(goi.interp, "usage: %s [phys] <address> <data> [<count>]", cmd_name); return JIM_ERR; @@ -4314,8 +4033,7 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv) fn = target_write_memory_fast; int e; - if (strcmp(Jim_GetString(argv[1], NULL), "phys") == 0) - { + if (strcmp(Jim_GetString(argv[1], NULL), "phys") == 0) { /* consume it */ struct Jim_Obj *obj; e = Jim_GetOpt_Obj(&goi, &obj); @@ -4336,8 +4054,7 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return e; jim_wide c = 1; - if (goi.argc == 1) - { + if (goi.argc == 1) { e = Jim_GetOpt_Wide(&goi, &c); if (e != JIM_OK) return e; @@ -4345,21 +4062,17 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv) /* all args must be consumed */ if (goi.argc != 0) - { return JIM_ERR; - } struct target *target = Jim_CmdPrivData(goi.interp); unsigned data_size; - if (strcasecmp(cmd_name, "mww") == 0) { + if (strcasecmp(cmd_name, "mww") == 0) data_size = 4; - } - else if (strcasecmp(cmd_name, "mwh") == 0) { + else if (strcasecmp(cmd_name, "mwh") == 0) data_size = 2; - } - else if (strcasecmp(cmd_name, "mwb") == 0) { + else if (strcasecmp(cmd_name, "mwb") == 0) data_size = 1; - } else { + else { LOG_ERROR("command '%s' unknown: ", cmd_name); return JIM_ERR; } @@ -4374,8 +4087,7 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv) Jim_GetOptInfo goi; Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); - if ((goi.argc < 1) || (goi.argc > 3)) - { + if ((goi.argc < 1) || (goi.argc > 3)) { Jim_SetResultFormatted(goi.interp, "usage: %s [phys] <address> [<count>]", cmd_name); return JIM_ERR; @@ -4383,40 +4095,34 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv) int (*fn)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - fn=target_read_memory; + fn = target_read_memory; int e; - if (strcmp(Jim_GetString(argv[1], NULL), "phys") == 0) - { + if (strcmp(Jim_GetString(argv[1], NULL), "phys") == 0) { /* consume it */ struct Jim_Obj *obj; e = Jim_GetOpt_Obj(&goi, &obj); if (e != JIM_OK) return e; - fn=target_read_phys_memory; + fn = target_read_phys_memory; } jim_wide a; e = Jim_GetOpt_Wide(&goi, &a); - if (e != JIM_OK) { + if (e != JIM_OK) return JIM_ERR; - } jim_wide c; if (goi.argc == 1) { e = Jim_GetOpt_Wide(&goi, &c); - if (e != JIM_OK) { + if (e != JIM_OK) return JIM_ERR; - } - } else { + } else c = 1; - } /* all args must be consumed */ if (goi.argc != 0) - { return JIM_ERR; - } jim_wide b = 1; /* shut up gcc */ if (strcasecmp(cmd_name, "mdw") == 0) @@ -4438,9 +4144,8 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv) jim_wide x, y, z; while (c > 0) { y = c; - if (y > 16) { + if (y > 16) y = 16; - } e = fn(target, a, b, y / b, target_buf); if (e != ERROR_OK) { char tmp[10]; @@ -4452,34 +4157,29 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv) command_print(NULL, "0x%08x ", (int)(a)); switch (b) { case 4: - for (x = 0; x < 16 && x < y; x += 4) - { - z = target_buffer_get_u32(target, &(target_buf[ x ])); + for (x = 0; x < 16 && x < y; x += 4) { + z = target_buffer_get_u32(target, &(target_buf[x])); command_print(NULL, "%08x ", (int)(z)); } - for (; (x < 16) ; x += 4) { + for (; (x < 16) ; x += 4) command_print(NULL, " "); - } break; case 2: - for (x = 0; x < 16 && x < y; x += 2) - { - z = target_buffer_get_u16(target, &(target_buf[ x ])); + for (x = 0; x < 16 && x < y; x += 2) { + z = target_buffer_get_u16(target, &(target_buf[x])); command_print(NULL, "%04x ", (int)(z)); } - for (; (x < 16) ; x += 2) { + for (; (x < 16) ; x += 2) command_print(NULL, " "); - } break; case 1: default: for (x = 0 ; (x < 16) && (x < y) ; x += 1) { - z = target_buffer_get_u8(target, &(target_buf[ x ])); + z = target_buffer_get_u8(target, &(target_buf[x])); command_print(NULL, "%02x ", (int)(z)); } - for (; (x < 16) ; x += 1) { + for (; (x < 16) ; x += 1) command_print(NULL, " "); - } break; } /* ascii-ify the bytes */ @@ -4530,8 +4230,7 @@ static int jim_target_tap_disabled(Jim_Interp *interp) static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); return JIM_ERR; } @@ -4541,16 +4240,13 @@ static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv int e = target->type->examine(target); if (e != ERROR_OK) - { return JIM_ERR; - } return JIM_OK; } static int jim_target_halt_gdb(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); return JIM_ERR; } @@ -4564,8 +4260,7 @@ static int jim_target_halt_gdb(Jim_Interp *interp, int argc, Jim_Obj *const *arg static int jim_target_poll(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); return JIM_ERR; } @@ -4574,15 +4269,12 @@ static int jim_target_poll(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return jim_target_tap_disabled(interp); int e; - if (!(target_was_examined(target))) { + if (!(target_was_examined(target))) e = ERROR_TARGET_NOT_EXAMINED; - } else { + else e = target->type->poll(target); - } if (e != ERROR_OK) - { return JIM_ERR; - } return JIM_OK; } @@ -4591,8 +4283,7 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) Jim_GetOptInfo goi; Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc != 2) - { + if (goi.argc != 2) { Jim_WrongNumArgs(interp, 0, argv, "([tT]|[fF]|assert|deassert) BOOL"); return JIM_ERR; @@ -4600,8 +4291,7 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) Jim_Nvp *n; int e = Jim_GetOpt_Nvp(&goi, nvp_assert, &n); - if (e != JIM_OK) - { + if (e != JIM_OK) { Jim_GetOpt_NvpUnknown(&goi, nvp_assert, 1); return e; } @@ -4614,13 +4304,11 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) struct target *target = Jim_CmdPrivData(goi.interp); if (!target->tap->enabled) return jim_target_tap_disabled(interp); - if (!(target_was_examined(target))) - { + if (!(target_was_examined(target))) { LOG_ERROR("Target not examined yet"); return ERROR_TARGET_NOT_EXAMINED; } - if (!target->type->assert_reset || !target->type->deassert_reset) - { + if (!target->type->assert_reset || !target->type->deassert_reset) { Jim_SetResultFormatted(interp, "No target-specific reset for %s", target_name(target)); @@ -4632,11 +4320,10 @@ static int jim_target_reset(Jim_Interp *interp, int argc, Jim_Obj *const *argv) target_free_all_working_areas_restore(target, 0); /* do the assert */ - if (n->value == NVP_ASSERT) { + if (n->value == NVP_ASSERT) e = target->type->assert_reset(target); - } else { + else e = target->type->deassert_reset(target); - } return (e == ERROR_OK) ? JIM_OK : JIM_ERR; } @@ -4659,8 +4346,7 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); /* params: <name> statename timeoutmsecs */ - if (goi.argc != 2) - { + if (goi.argc != 2) { const char *cmd_name = Jim_GetString(argv[0], NULL); Jim_SetResultFormatted(goi.interp, "%s <state_name> <timeout_in_msec>", cmd_name); @@ -4670,21 +4356,19 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a Jim_Nvp *n; int e = Jim_GetOpt_Nvp(&goi, nvp_target_state, &n); if (e != JIM_OK) { - Jim_GetOpt_NvpUnknown(&goi, nvp_target_state,1); + Jim_GetOpt_NvpUnknown(&goi, nvp_target_state, 1); return e; } jim_wide a; e = Jim_GetOpt_Wide(&goi, &a); - if (e != JIM_OK) { + if (e != JIM_OK) return e; - } struct target *target = Jim_CmdPrivData(interp); if (!target->tap->enabled) return jim_target_tap_disabled(interp); e = target_wait_state(target, n->value, a); - if (e != ERROR_OK) - { + if (e != ERROR_OK) { Jim_Obj *eObj = Jim_NewIntObj(interp, e); Jim_SetResultFormatted(goi.interp, "target: %s wait %s fails (%#s) %s", @@ -4701,7 +4385,7 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a static int jim_target_event_list(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { struct command_context *cmd_ctx = current_command_context(interp); - assert (cmd_ctx != NULL); + assert(cmd_ctx != NULL); struct target *target = Jim_CmdPrivData(interp); struct target_event_action *teap = target->event_action; @@ -4711,8 +4395,7 @@ static int jim_target_event_list(Jim_Interp *interp, int argc, Jim_Obj *const *a command_print(cmd_ctx, "%-25s | Body", "Event"); command_print(cmd_ctx, "------------------------- | " "----------------------------------------"); - while (teap) - { + while (teap) { Jim_Nvp *opt = Jim_Nvp_value2name_simple(nvp_target_event, teap->event); command_print(cmd_ctx, "%-25s | %s", opt->name, Jim_GetString(teap->body, NULL)); @@ -4723,8 +4406,7 @@ static int jim_target_event_list(Jim_Interp *interp, int argc, Jim_Obj *const *a } static int jim_target_current_state(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "[no parameters]"); return JIM_ERR; } @@ -4736,16 +4418,14 @@ static int jim_target_invoke_event(Jim_Interp *interp, int argc, Jim_Obj *const { Jim_GetOptInfo goi; Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc != 1) - { + if (goi.argc != 1) { const char *cmd_name = Jim_GetString(argv[0], NULL); Jim_SetResultFormatted(goi.interp, "%s <eventname>", cmd_name); return JIM_ERR; } Jim_Nvp *n; int e = Jim_GetOpt_Nvp(&goi, nvp_target_event, &n); - if (e != JIM_OK) - { + if (e != JIM_OK) { Jim_GetOpt_NvpUnknown(&goi, nvp_target_event, 1); return e; } @@ -4897,7 +4577,7 @@ static int target_create(Jim_GetOptInfo *goi) struct command_context *cmd_ctx; cmd_ctx = current_command_context(goi->interp); - assert (cmd_ctx != NULL); + assert(cmd_ctx != NULL); if (goi->argc < 3) { Jim_WrongNumArgs(goi->interp, 1, goi->argv, "?name? ?type? ..options..."); @@ -4938,19 +4618,19 @@ static int target_create(Jim_GetOptInfo *goi) Jim_AppendStrings(goi->interp, Jim_GetResult(goi->interp), " or ", - target_types[x]->name,NULL); + target_types[x]->name, NULL); } } return JIM_ERR; } /* Create it */ - target = calloc(1,sizeof(struct target)); + target = calloc(1, sizeof(struct target)); /* set target number */ target->target_number = new_target_number(); /* allocate memory for each unique target type */ - target->type = (struct target_type*)calloc(1,sizeof(struct target_type)); + target->type = (struct target_type *)calloc(1, sizeof(struct target_type)); memcpy(target->type, target_types[x], sizeof(struct target_type)); @@ -4999,8 +4679,7 @@ static int target_create(Jim_GetOptInfo *goi) goi->isconfigure = 1; e = target_configure(goi, target); - if (target->tap == NULL) - { + if (target->tap == NULL) { Jim_SetResultString(goi->interp, "-chain-position required when creating target", -1); e = JIM_ERR; } @@ -5029,17 +4708,15 @@ static int target_create(Jim_GetOptInfo *goi) if (ERROR_OK != e) LOG_ERROR("unable to register '%s' commands", cp); } - if (target->type->target_create) { + if (target->type->target_create) (*(target->type->target_create))(target, goi->interp); - } /* append to end of list */ { struct target **tpp; tpp = &(all_targets); - while (*tpp) { + while (*tpp) tpp = &((*tpp)->next); - } *tpp = target; } @@ -5076,13 +4753,12 @@ static int target_create(Jim_GetOptInfo *goi) static int jim_target_current(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); return JIM_ERR; } struct command_context *cmd_ctx = current_command_context(interp); - assert (cmd_ctx != NULL); + assert(cmd_ctx != NULL); Jim_SetResultString(interp, get_current_target(cmd_ctx)->cmd_name, -1); return JIM_OK; @@ -5090,14 +4766,12 @@ static int jim_target_current(Jim_Interp *interp, int argc, Jim_Obj *const *argv static int jim_target_types(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); return JIM_ERR; } Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); - for (unsigned x = 0; NULL != target_types[x]; x++) - { + for (unsigned x = 0; NULL != target_types[x]; x++) { Jim_ListAppendElement(interp, Jim_GetResult(interp), Jim_NewStringObj(interp, target_types[x]->name, -1)); } @@ -5106,15 +4780,13 @@ static int jim_target_types(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_target_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "Too many parameters"); return JIM_ERR; } Jim_SetResult(interp, Jim_NewListObj(interp, NULL, 0)); struct target *target = all_targets; - while (target) - { + while (target) { Jim_ListAppendElement(interp, Jim_GetResult(interp), Jim_NewStringObj(interp, target_name(target), -1)); target = target->next; @@ -5126,7 +4798,7 @@ static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { int i; const char *targetname; - int retval,len; + int retval, len; struct target *target = (struct target *) NULL; struct target_list *head, *curr, *new; curr = (struct target_list *) NULL; @@ -5134,40 +4806,34 @@ static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv) new = (struct target_list *) NULL; retval = 0; - LOG_DEBUG("%d",argc); + LOG_DEBUG("%d", argc); /* argv[1] = target to associate in smp * argv[2] = target to assoicate in smp * argv[3] ... */ - for(i=1;i<argc;i++) - { + for (i = 1; i < argc; i++) { targetname = Jim_GetString(argv[i], &len); target = get_target(targetname); - LOG_DEBUG("%s ",targetname); - if (target) - { - new=malloc(sizeof(struct target_list)); + LOG_DEBUG("%s ", targetname); + if (target) { + new = malloc(sizeof(struct target_list)); new->target = target; - new->next = (struct target_list*)NULL; - if (head == (struct target_list*)NULL) - { + new->next = (struct target_list *)NULL; + if (head == (struct target_list *)NULL) { head = new; curr = head; - } - else - { + } else { curr->next = new; curr = new; } } } - /* now parse the list of cpu and put the target in smp mode*/ - curr=head; + /* now parse the list of cpu and put the target in smp mode*/ + curr = head; - while(curr!=(struct target_list *)NULL) - { + while (curr != (struct target_list *)NULL) { target = curr->target; target->smp = 1; target->head = head; @@ -5183,8 +4849,7 @@ static int jim_target_create(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { Jim_GetOptInfo goi; Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1); - if (goi.argc < 3) - { + if (goi.argc < 3) { Jim_WrongNumArgs(goi.interp, goi.argc, goi.argv, "<name> <target_type> [<target_options> ...]"); return JIM_ERR; @@ -5199,8 +4864,7 @@ static int jim_target_number(Jim_Interp *interp, int argc, Jim_Obj *const *argv) /* It's OK to remove this mechanism sometime after August 2010 or so */ LOG_WARNING("don't use numbers as target identifiers; use names"); - if (goi.argc != 1) - { + if (goi.argc != 1) { Jim_SetResultFormatted(goi.interp, "usage: target number <number>"); return JIM_ERR; } @@ -5210,8 +4874,7 @@ static int jim_target_number(Jim_Interp *interp, int argc, Jim_Obj *const *argv) return JIM_ERR; struct target *target; - for (target = all_targets; NULL != target; target = target->next) - { + for (target = all_targets; NULL != target; target = target->next) { if (target->target_number != w) continue; @@ -5229,15 +4892,13 @@ static int jim_target_number(Jim_Interp *interp, int argc, Jim_Obj *const *argv) static int jim_target_count(Jim_Interp *interp, int argc, Jim_Obj *const *argv) { - if (argc != 1) - { + if (argc != 1) { Jim_WrongNumArgs(interp, 1, argv, "<no parameters>"); return JIM_ERR; } unsigned count = 0; struct target *target = all_targets; - while (NULL != target) - { + while (NULL != target) { target = target->next; count++; } @@ -5305,8 +4966,7 @@ static const struct command_registration target_subcommand_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct FastLoad -{ +struct FastLoad { uint32_t address; uint8_t *data; int length; @@ -5318,11 +4978,9 @@ static struct FastLoad *fastload; static void free_fastload(void) { - if (fastload != NULL) - { + if (fastload != NULL) { int i; - for (i = 0; i < fastload_num; i++) - { + for (i = 0; i < fastload_num; i++) { if (fastload[i].data) free(fastload[i].data); } @@ -5331,9 +4989,6 @@ static void free_fastload(void) } } - - - COMMAND_HANDLER(handle_fast_load_image_command) { uint8_t *buffer; @@ -5355,34 +5010,29 @@ COMMAND_HANDLER(handle_fast_load_image_command) retval = image_open(&image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL); if (retval != ERROR_OK) - { return retval; - } image_size = 0x0; retval = ERROR_OK; fastload_num = image.num_sections; fastload = (struct FastLoad *)malloc(sizeof(struct FastLoad)*image.num_sections); - if (fastload == NULL) - { + if (fastload == NULL) { command_print(CMD_CTX, "out of memory"); image_close(&image); return ERROR_FAIL; } memset(fastload, 0, sizeof(struct FastLoad)*image.num_sections); - for (i = 0; i < image.num_sections; i++) - { + for (i = 0; i < image.num_sections; i++) { buffer = malloc(image.sections[i].size); - if (buffer == NULL) - { + if (buffer == NULL) { command_print(CMD_CTX, "error allocating buffer for section (%d bytes)", (int)(image.sections[i].size)); retval = ERROR_FAIL; break; } - if ((retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt)) != ERROR_OK) - { + retval = image_read_section(&image, i, 0x0, image.sections[i].size, buffer, &buf_cnt); + if (retval != ERROR_OK) { free(buffer); break; } @@ -5390,28 +5040,22 @@ COMMAND_HANDLER(handle_fast_load_image_command) uint32_t offset = 0; uint32_t length = buf_cnt; - /* DANGER!!! beware of unsigned comparision here!!! */ - if ((image.sections[i].base_address + buf_cnt >= min_address)&& - (image.sections[i].base_address < max_address)) - { - if (image.sections[i].base_address < min_address) - { + if ((image.sections[i].base_address + buf_cnt >= min_address) && + (image.sections[i].base_address < max_address)) { + if (image.sections[i].base_address < min_address) { /* clip addresses below */ offset += min_address-image.sections[i].base_address; length -= offset; } if (image.sections[i].base_address + buf_cnt > max_address) - { length -= (image.sections[i].base_address + buf_cnt)-max_address; - } fastload[i].address = image.sections[i].base_address + offset; fastload[i].data = malloc(length); - if (fastload[i].data == NULL) - { + if (fastload[i].data == NULL) { free(buffer); command_print(CMD_CTX, "error allocating buffer for section (%d bytes)", length); @@ -5430,8 +5074,7 @@ COMMAND_HANDLER(handle_fast_load_image_command) free(buffer); } - if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) - { + if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) { command_print(CMD_CTX, "Loaded %" PRIu32 " bytes " "in %fs (%0.3f KiB/s)", image_size, duration_elapsed(&bench), duration_kbps(&bench, image_size)); @@ -5444,9 +5087,7 @@ COMMAND_HANDLER(handle_fast_load_image_command) image_close(&image); if (retval != ERROR_OK) - { free_fastload(); - } return retval; } @@ -5455,8 +5096,7 @@ COMMAND_HANDLER(handle_fast_load_command) { if (CMD_ARGC > 0) return ERROR_COMMAND_SYNTAX_ERROR; - if (fastload == NULL) - { + if (fastload == NULL) { LOG_ERROR("No image in memory"); return ERROR_FAIL; } @@ -5464,21 +5104,17 @@ COMMAND_HANDLER(handle_fast_load_command) int ms = timeval_ms(); int size = 0; int retval = ERROR_OK; - for (i = 0; i < fastload_num;i++) - { + for (i = 0; i < fastload_num; i++) { struct target *target = get_current_target(CMD_CTX); command_print(CMD_CTX, "Write to 0x%08x, length 0x%08x", (unsigned int)(fastload[i].address), (unsigned int)(fastload[i].length)); retval = target_write_buffer(target, fastload[i].address, fastload[i].length, fastload[i].data); if (retval != ERROR_OK) - { break; - } size += fastload[i].length; } - if (retval == ERROR_OK) - { + if (retval == ERROR_OK) { int after = timeval_ms(); command_print(CMD_CTX, "Loaded image %f kBytes/s", (float)(size/1024.0)/((float)(after-ms)/1000.0)); } @@ -5769,10 +5405,12 @@ static const struct command_registration target_exec_command_handlers[] = { static int target_register_user_commands(struct command_context *cmd_ctx) { int retval = ERROR_OK; - if ((retval = target_request_register_commands(cmd_ctx)) != ERROR_OK) + retval = target_request_register_commands(cmd_ctx); + if (retval != ERROR_OK) return retval; - if ((retval = trace_register_commands(cmd_ctx)) != ERROR_OK) + retval = trace_register_commands(cmd_ctx); + if (retval != ERROR_OK) return retval; diff --git a/src/target/target.h b/src/target/target.h index 12726bd..680f8c3 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -29,6 +29,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef TARGET_H #define TARGET_H @@ -57,8 +58,7 @@ struct target_list; */ -enum target_state -{ +enum target_state { TARGET_UNKNOWN = 0, TARGET_RUNNING = 1, TARGET_HALTED = 2, @@ -71,16 +71,14 @@ enum nvp_assert { NVP_ASSERT, }; -enum target_reset_mode -{ +enum target_reset_mode { RESET_UNKNOWN = 0, RESET_RUN = 1, /* reset and let target run */ RESET_HALT = 2, /* reset and halt target out of reset */ RESET_INIT = 3, /* reset and halt target out of reset, then run init script */ }; -enum target_debug_reason -{ +enum target_debug_reason { DBG_REASON_DBGRQ = 0, DBG_REASON_BREAKPOINT = 1, DBG_REASON_WATCHPOINT = 2, @@ -90,14 +88,12 @@ enum target_debug_reason DBG_REASON_UNDEFINED = 6 }; -enum target_endianness -{ +enum target_endianness { TARGET_ENDIAN_UNKNOWN = 0, TARGET_BIG_ENDIAN = 1, TARGET_LITTLE_ENDIAN = 2 }; -struct working_area -{ +struct working_area { uint32_t address; uint32_t size; bool free; @@ -105,26 +101,23 @@ struct working_area struct working_area **user; struct working_area *next; }; - -struct gdb_service -{ + +struct gdb_service { struct target *target; /* field for smp display */ /* element 0 coreid currently displayed ( 1 till n) */ - /* element 1 coreid to be displayed at next resume 1 till n 0 means resume - * all cores - core displayed */ + /* element 1 coreid to be displayed at next resume 1 till n 0 means resume + * all cores core displayed */ int32_t core[2]; }; -// target_type.h contains the full definitionof struct targe_type -struct target -{ - struct target_type *type; /* target type definition (name, access functions) */ +/* target_type.h contains the full definitionof struct targe_type */ +struct target { + struct target_type *type; /* target type definition (name, access functions) */ const char *cmd_name; /* tcl Name of target */ int target_number; /* DO NOT USE! field to be removed in 2010 */ - struct jtag_tap *tap; /* where on the jtag chain is this */ - int32_t coreid; /* which device on the TAP? */ + struct jtag_tap *tap; /* where on the jtag chain is this */ + int32_t coreid; /* which device on the TAP? */ const char *variant; /* what variant of this chip is it? */ /** @@ -146,25 +139,25 @@ struct target struct target_event_action *event_action; int reset_halt; /* attempt resetting the CPU into the halted mode? */ - uint32_t working_area; /* working area (initialized RAM). Evaluated + uint32_t working_area; /* working area (initialized RAM). Evaluated * upon first allocation from virtual/physical address. */ bool working_area_virt_spec; /* virtual address specified? */ uint32_t working_area_virt; /* virtual address */ bool working_area_phys_spec; /* virtual address specified? */ uint32_t working_area_phys; /* physical address */ uint32_t working_area_size; /* size in bytes */ - uint32_t backup_working_area; /* whether the content of the working area has to be preserved */ + uint32_t backup_working_area; /* whether the content of the working area has to be preserved */ struct working_area *working_areas;/* list of allocated working areas */ enum target_debug_reason debug_reason;/* reason why the target entered debug state */ enum target_endianness endianness; /* target endianness */ - // also see: target_state_name() + /* also see: target_state_name() */ enum target_state state; /* the current backend-state (running, halted, ...) */ struct reg_cache *reg_cache; /* the first register cache of the target (core regs) */ - struct breakpoint *breakpoints; /* list of breakpoints */ - struct watchpoint *watchpoints; /* list of watchpoints */ + struct breakpoint *breakpoints; /* list of breakpoints */ + struct watchpoint *watchpoints; /* list of watchpoints */ struct trace *trace_info; /* generic trace information */ - struct debug_msg_receiver *dbgmsg;/* list of debug message receivers */ - uint32_t dbg_msg_enabled; /* debug message status */ + struct debug_msg_receiver *dbgmsg; /* list of debug message receivers */ + uint32_t dbg_msg_enabled; /* debug message status */ void *arch_info; /* architecture specific information */ struct target *next; /* next target in list */ @@ -175,13 +168,13 @@ struct target bool dbgbase_set; /* By default the debug base is not set */ uint32_t dbgbase; /* Really a Cortex-A specific option, but there is no - system in place to support target specific options - currently. */ + system in place to support target specific options + currently. */ struct rtos *rtos; /* Instance of Real Time Operating System support */ - bool rtos_auto_detect; /* A flag that indicates that the RTOS has been specified as "auto" - * and must be detected when symbols are offered */ + bool rtos_auto_detect; /* A flag that indicates that the RTOS has been specified as "auto" + * and must be detected when symbols are offered */ - int smp; /* add some target attributes for smp support */ + int smp; /* add some target attributes for smp support */ struct target_list *head; /* the gdb service is there in case of smp , we have only one gdb server * for all smp target @@ -190,7 +183,6 @@ struct target struct gdb_service *gdb_service; }; - struct target_list { struct target *target; struct target_list *next; @@ -204,8 +196,7 @@ static inline const char *target_name(struct target *target) const char *debug_reason_name(struct target *t); -enum target_event -{ +enum target_event { /* LD historical names * - Prior to the great TCL change * - June/July/Aug 2008 @@ -269,15 +260,13 @@ struct target_event_action { bool target_has_event_action(struct target *target, enum target_event event); -struct target_event_callback -{ +struct target_event_callback { int (*callback)(struct target *target, enum target_event event, void *priv); void *priv; struct target_event_callback *next; }; -struct target_timer_callback -{ +struct target_timer_callback { int (*callback)(void *priv); int time_ms; int periodic; @@ -291,11 +280,11 @@ int target_examine(void); int target_register_event_callback( int (*callback)(struct target *target, - enum target_event event, void *priv), + enum target_event event, void *priv), void *priv); int target_unregister_event_callback( int (*callback)(struct target *target, - enum target_event event, void *priv), + enum target_event event, void *priv), void *priv); /* Poll the status of the target, detect any error conditions and report them. * @@ -329,7 +318,7 @@ int target_call_timer_callbacks(void); */ int target_call_timer_callbacks_now(void); -struct target* get_current_target(struct command_context *cmd_ctx); +struct target *get_current_target(struct command_context *cmd_ctx); struct target *get_target(const char *id); /** @@ -348,14 +337,14 @@ const char *target_type_name(struct target *target); */ int target_examine_one(struct target *target); -/// @returns @c true if target_set_examined() has been called. +/** @returns @c true if target_set_examined() has been called. */ static inline bool target_was_examined(struct target *target) { return target->examined; } -/// Sets the @c examined flag for the given target. -/// Use in target->type->examine() after one-time setup is done. +/** Sets the @c examined flag for the given target. */ +/** Use in target->type->examine() after one-time setup is done. */ static inline void target_set_examined(struct target *target) { target->examined = true; @@ -520,13 +509,13 @@ int target_write_buffer(struct target *target, int target_read_buffer(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer); int target_checksum_memory(struct target *target, - uint32_t address, uint32_t size, uint32_t* crc); + uint32_t address, uint32_t size, uint32_t *crc); int target_blank_check_memory(struct target *target, - uint32_t address, uint32_t size, uint32_t* blank); + uint32_t address, uint32_t size, uint32_t *blank); int target_wait_state(struct target *target, enum target_state state, int ms); /** Return the *name* of this targets current state */ -const char *target_state_name( struct target *target ); +const char *target_state_name(struct target *target); /* DANGER!!!!! * diff --git a/src/target/target_request.c b/src/target/target_request.c index 090de9f..c1f987e 100644 --- a/src/target/target_request.c +++ b/src/target/target_request.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -35,8 +36,7 @@ #include "target_type.h" #include "trace.h" - -static bool got_message = false; +static bool got_message; bool target_got_message(void) { @@ -45,20 +45,19 @@ bool target_got_message(void) return t; } -static int charmsg_mode = 0; +static int charmsg_mode; static int target_asciimsg(struct target *target, uint32_t length) { char *msg = malloc(DIV_ROUND_UP(length + 1, 4) * 4); struct debug_msg_receiver *c = target->dbgmsg; - target->type->target_request_data(target, DIV_ROUND_UP(length, 4), (uint8_t*)msg); + target->type->target_request_data(target, DIV_ROUND_UP(length, 4), (uint8_t *)msg); msg[length] = 0; LOG_DEBUG("%s", msg); - while (c) - { + while (c) { command_print(c->cmd_ctx, "%s", msg); c = c->next; } @@ -83,13 +82,11 @@ static int target_hexmsg(struct target *target, int size, uint32_t length) LOG_DEBUG("size: %i, length: %i", (int)size, (int)length); - target->type->target_request_data(target, DIV_ROUND_UP(length * size, 4), (uint8_t*)data); + target->type->target_request_data(target, DIV_ROUND_UP(length * size, 4), (uint8_t *)data); line_len = 0; - for (i = 0; i < length; i++) - { - switch (size) - { + for (i = 0; i < length; i++) { + switch (size) { case 4: line_len += snprintf(line + line_len, 128 - line_len, "%8.8" PRIx32 " ", le_to_h_u32(data + (4*i))); break; @@ -101,12 +98,10 @@ static int target_hexmsg(struct target *target, int size, uint32_t length) break; } - if ((i%8 == 7) || (i == length - 1)) - { + if ((i%8 == 7) || (i == length - 1)) { LOG_DEBUG("%s", line); - while (c) - { + while (c) { command_print(c->cmd_ctx, "%s", line); c = c->next; } @@ -134,20 +129,16 @@ int target_request(struct target *target, uint32_t request) target_charmsg(target, target_req_cmd); return ERROR_OK; } - switch (target_req_cmd) - { + + switch (target_req_cmd) { case TARGET_REQ_TRACEMSG: trace_point(target, (request & 0xffffff00) >> 8); break; case TARGET_REQ_DEBUGMSG: if (((request & 0xff00) >> 8) == 0) - { target_asciimsg(target, (request & 0xffff0000) >> 16); - } else - { target_hexmsg(target, (request & 0xff00) >> 8, (request & 0xffff0000) >> 16); - } break; case TARGET_REQ_DEBUGCHAR: target_charmsg(target, (request & 0x00ff0000) >> 16); @@ -155,9 +146,9 @@ int target_request(struct target *target, uint32_t request) /* case TARGET_REQ_SEMIHOSTING: * break; */ - default: - LOG_ERROR("unknown target request: %2.2x", target_req_cmd); - break; + default: + LOG_ERROR("unknown target request: %2.2x", target_req_cmd); + break; } return ERROR_OK; @@ -171,8 +162,7 @@ static int add_debug_msg_receiver(struct command_context *cmd_ctx, struct target return ERROR_COMMAND_SYNTAX_ERROR; /* see if there's already a list */ - if (*p) - { + if (*p) { /* find end of linked list */ p = &target->dbgmsg; while ((*p)->next) @@ -191,7 +181,8 @@ static int add_debug_msg_receiver(struct command_context *cmd_ctx, struct target return ERROR_OK; } -static struct debug_msg_receiver* find_debug_msg_receiver(struct command_context *cmd_ctx, struct target *target) +static struct debug_msg_receiver *find_debug_msg_receiver(struct command_context *cmd_ctx, + struct target *target) { int do_all_targets = 0; @@ -208,12 +199,9 @@ static struct debug_msg_receiver* find_debug_msg_receiver(struct command_context /* so we target != null */ struct debug_msg_receiver **p = &target->dbgmsg; do { - while (*p) - { + while (*p) { if ((*p)->cmd_ctx == cmd_ctx) - { return *p; - } p = &((*p)->next); } @@ -230,8 +218,7 @@ int delete_debug_msg_receiver(struct command_context *cmd_ctx, struct target *ta int do_all_targets = 0; /* if no target has been specified search all of them */ - if (target == NULL) - { + if (target == NULL) { /* if no targets haven been specified */ if (all_targets == NULL) return ERROR_OK; @@ -240,25 +227,20 @@ int delete_debug_msg_receiver(struct command_context *cmd_ctx, struct target *ta do_all_targets = 1; } - do - { + do { p = &target->dbgmsg; c = *p; - while (c) - { + while (c) { struct debug_msg_receiver *next = c->next; - if (c->cmd_ctx == cmd_ctx) - { + if (c->cmd_ctx == cmd_ctx) { *p = next; free(c); - if (*p == NULL) - { + if (*p == NULL) { /* disable callback */ target->dbg_msg_enabled = 0; } return ERROR_OK; - } - else + } else p = &(c->next); c = next; } @@ -279,35 +261,26 @@ COMMAND_HANDLER(handle_target_request_debugmsgs_command) if (find_debug_msg_receiver(CMD_CTX, target) != NULL) receiving = 1; - if (CMD_ARGC > 0) - { - if (!strcmp(CMD_ARGV[0], "enable") || !strcmp(CMD_ARGV[0], "charmsg")) - { + if (CMD_ARGC > 0) { + if (!strcmp(CMD_ARGV[0], "enable") || !strcmp(CMD_ARGV[0], "charmsg")) { /* don't register if this command context is already receiving */ - if (!receiving) - { + if (!receiving) { receiving = 1; add_debug_msg_receiver(CMD_CTX, target); } charmsg_mode = !strcmp(CMD_ARGV[0], "charmsg"); - } - else if (!strcmp(CMD_ARGV[0], "disable")) - { + } else if (!strcmp(CMD_ARGV[0], "disable")) { /* no need to delete a receiver if none is registered */ - if (receiving) - { + if (receiving) { receiving = 0; delete_debug_msg_receiver(CMD_CTX, target); } - } - else - { - return ERROR_COMMAND_SYNTAX_ERROR; - } + } else + return ERROR_COMMAND_SYNTAX_ERROR; } command_print(CMD_CTX, "receiving debug messages from current target %s", - (receiving) ? (charmsg_mode?"charmsg":"enabled") : "disabled"); + (receiving) ? (charmsg_mode ? "charmsg" : "enabled") : "disabled"); return ERROR_OK; } diff --git a/src/target/target_request.h b/src/target/target_request.h index 740645e..301390b 100644 --- a/src/target/target_request.h +++ b/src/target/target_request.h @@ -23,22 +23,21 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef TARGET_REQUEST_H #define TARGET_REQUEST_H struct target; struct command_context; -typedef enum target_req_cmd -{ +typedef enum target_req_cmd { TARGET_REQ_TRACEMSG, TARGET_REQ_DEBUGMSG, TARGET_REQ_DEBUGCHAR, /* TARGET_REQ_SEMIHOSTING, */ } target_req_cmd_t; -struct debug_msg_receiver -{ +struct debug_msg_receiver { struct command_context *cmd_ctx; struct debug_msg_receiver *next; }; diff --git a/src/target/target_type.h b/src/target/target_type.h index 10b6f33..f6f0ea7 100644 --- a/src/target/target_type.h +++ b/src/target/target_type.h @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef TARGET_TYPE_H #define TARGET_TYPE_H @@ -36,8 +37,7 @@ struct target; * type. For example, all Cortex-M3 targets on a scan chain share * the same method table. */ -struct target_type -{ +struct target_type { /** * Name of this type of target. Do @b not access this * field directly, use target_type_name() instead. @@ -55,8 +55,10 @@ struct target_type /* halt will log a warning, but return ERROR_OK if the target is already halted. */ int (*halt)(struct target *target); - int (*resume)(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); - int (*step)(struct target *target, int current, uint32_t address, int handle_breakpoints); + int (*resume)(struct target *target, int current, uint32_t address, + int handle_breakpoints, int debug_execution); + int (*step)(struct target *target, int current, uint32_t address, + int handle_breakpoints); /* target reset control. assert reset can be invoked when OpenOCD and * the target is out of sync. @@ -106,34 +108,43 @@ struct target_type * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * count: number of items of <size> */ - int (*read_memory_imp)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); + int (*read_memory_imp)(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer); /** * Target memory read callback. Do @b not call this function * directly, use target_read_memory() instead. */ - int (*read_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - int (*write_memory_imp)(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer); + int (*read_memory)(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer); + int (*write_memory_imp)(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); /** * Target memory write callback. Do @b not call this function * directly, use target_write_memory() instead. */ - int (*write_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer); + int (*write_memory)(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); /* Default implementation will do some fancy alignment to improve performance, target can override */ - int (*read_buffer)(struct target *target, uint32_t address, uint32_t size, uint8_t *buffer); + int (*read_buffer)(struct target *target, uint32_t address, + uint32_t size, uint8_t *buffer); /* Default implementation will do some fancy alignment to improve performance, target can override */ - int (*write_buffer)(struct target *target, uint32_t address, uint32_t size, const uint8_t *buffer); + int (*write_buffer)(struct target *target, uint32_t address, + uint32_t size, const uint8_t *buffer); /** * Write target memory in multiples of 4 bytes, optimized for * writing large quantities of data. Do @b not call this * function directly, use target_bulk_write_memory() instead. */ - int (*bulk_write_memory)(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer); + int (*bulk_write_memory)(struct target *target, uint32_t address, + uint32_t count, const uint8_t *buffer); - int (*checksum_memory)(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum); - int (*blank_check_memory)(struct target *target, uint32_t address, uint32_t count, uint32_t* blank); + int (*checksum_memory)(struct target *target, uint32_t address, + uint32_t count, uint32_t *checksum); + int (*blank_check_memory)(struct target *target, uint32_t address, + uint32_t count, uint32_t *blank); /* * target break-/watchpoint control @@ -170,9 +181,18 @@ struct target_type * Target algorithm support. Do @b not call this method directly, * use target_run_algorithm() instead. */ - int (*run_algorithm)(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info); - int (*start_algorithm)(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, uint32_t entry_point, uint32_t exit_point, void *arch_info); - int (*wait_algorithm)(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_param, uint32_t exit_point, int timeout_ms, void *arch_info); + int (*run_algorithm)(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_param, uint32_t entry_point, + uint32_t exit_point, int timeout_ms, void *arch_info); + int (*start_algorithm)(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_param, uint32_t entry_point, + uint32_t exit_point, void *arch_info); + int (*wait_algorithm)(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_params, + struct reg_param *reg_param, uint32_t exit_point, + int timeout_ms, void *arch_info); const struct command_registration *commands; @@ -224,12 +244,14 @@ struct target_type * * Default implementation is to call read_memory. */ - int (*read_phys_memory)(struct target *target, uint32_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer); + int (*read_phys_memory)(struct target *target, uint32_t phys_address, + uint32_t size, uint32_t count, uint8_t *buffer); /* * same as read_phys_memory, except that it writes... */ - int (*write_phys_memory)(struct target *target, uint32_t phys_address, uint32_t size, uint32_t count, const uint8_t *buffer); + int (*write_phys_memory)(struct target *target, uint32_t phys_address, + uint32_t size, uint32_t count, const uint8_t *buffer); int (*mmu)(struct target *target, int *enabled); @@ -242,4 +264,4 @@ struct target_type int (*check_reset)(struct target *target); }; -#endif // TARGET_TYPE_H +#endif /* TARGET_TYPE_H */ diff --git a/src/target/trace.c b/src/target/trace.c index 7604db8..660e3cb 100644 --- a/src/target/trace.c +++ b/src/target/trace.c @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -34,11 +35,9 @@ int trace_point(struct target *target, uint32_t number) if (number < trace->num_trace_points) trace->trace_points[number].hit_counter++; - if (trace->trace_history_size) - { + if (trace->trace_history_size) { trace->trace_history[trace->trace_history_pos++] = number; - if (trace->trace_history_pos == trace->trace_history_size) - { + if (trace->trace_history_pos == trace->trace_history_size) { trace->trace_history_pos = 0; trace->trace_history_overflowed = 1; } @@ -52,12 +51,10 @@ COMMAND_HANDLER(handle_trace_point_command) struct target *target = get_current_target(CMD_CTX); struct trace *trace = target->trace_info; - if (CMD_ARGC == 0) - { + if (CMD_ARGC == 0) { uint32_t i; - for (i = 0; i < trace->num_trace_points; i++) - { + for (i = 0; i < trace->num_trace_points; i++) { command_print(CMD_CTX, "trace point 0x%8.8" PRIx32 " (%lld times hit)", trace->trace_points[i].address, (long long)trace->trace_points[i].hit_counter); @@ -66,10 +63,8 @@ COMMAND_HANDLER(handle_trace_point_command) return ERROR_OK; } - if (!strcmp(CMD_ARGV[0], "clear")) - { - if (trace->trace_points) - { + if (!strcmp(CMD_ARGV[0], "clear")) { + if (trace->trace_points) { free(trace->trace_points); trace->trace_points = NULL; } @@ -80,9 +75,9 @@ COMMAND_HANDLER(handle_trace_point_command) } /* resize array if necessary */ - if (!trace->trace_points || (trace->trace_points_size == trace->num_trace_points)) - { - trace->trace_points = realloc(trace->trace_points, sizeof(struct trace_point) * (trace->trace_points_size + 32)); + if (!trace->trace_points || (trace->trace_points_size == trace->num_trace_points)) { + trace->trace_points = realloc(trace->trace_points, + sizeof(struct trace_point) * (trace->trace_points_size + 32)); trace->trace_points_size += 32; } @@ -100,13 +95,11 @@ COMMAND_HANDLER(handle_trace_history_command) struct target *target = get_current_target(CMD_CTX); struct trace *trace = target->trace_info; - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { trace->trace_history_pos = 0; trace->trace_history_overflowed = 0; - if (!strcmp(CMD_ARGV[0], "clear")) - { + if (!strcmp(CMD_ARGV[0], "clear")) { /* clearing is implicit, we've just reset position anyway */ return ERROR_OK; } @@ -118,9 +111,7 @@ COMMAND_HANDLER(handle_trace_history_command) trace->trace_history = malloc(sizeof(uint32_t) * trace->trace_history_size); command_print(CMD_CTX, "new trace history size: %i", (int)(trace->trace_history_size)); - } - else - { + } else { uint32_t i; uint32_t first = 0; uint32_t last = trace->trace_history_pos; @@ -129,27 +120,22 @@ COMMAND_HANDLER(handle_trace_history_command) command_print(CMD_CTX, "trace history buffer is not allocated"); return ERROR_OK; } - if (trace->trace_history_overflowed) - { + + if (trace->trace_history_overflowed) { first = trace->trace_history_pos; last = trace->trace_history_pos - 1; } - for (i = first; (i % trace->trace_history_size) != last; i++) - { - if (trace->trace_history[i % trace->trace_history_size] < trace->num_trace_points) - { + for (i = first; (i % trace->trace_history_size) != last; i++) { + if (trace->trace_history[i % trace->trace_history_size] < trace->num_trace_points) { uint32_t address; address = trace->trace_points[trace->trace_history[i % trace->trace_history_size]].address; command_print(CMD_CTX, "trace point %i: 0x%8.8" PRIx32 "", - (int)(trace->trace_history[i % trace->trace_history_size]), - address); - } - - else - { - command_print(CMD_CTX, "trace point %i: -not defined-", (int)(trace->trace_history[i % trace->trace_history_size])); - } + (int)(trace->trace_history[i % trace->trace_history_size]), + address); + } else + command_print(CMD_CTX, "trace point %i: -not defined-", + (int)(trace->trace_history[i % trace->trace_history_size])); } } diff --git a/src/target/trace.h b/src/target/trace.h index 53502d4..5eaf8c8 100644 --- a/src/target/trace.h +++ b/src/target/trace.h @@ -17,6 +17,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef TRACE_H #define TRACE_H @@ -25,14 +26,12 @@ struct target; struct command_context; -struct trace_point -{ +struct trace_point { uint32_t address; uint64_t hit_counter; }; -struct trace -{ +struct trace { uint32_t num_trace_points; uint32_t trace_points_size; struct trace_point *trace_points; @@ -47,8 +46,7 @@ struct trace * to *hardware* tracing ... split such "real" tracing out from * the contrib/libdcc support. */ -typedef enum trace_status -{ +typedef enum trace_status { TRACE_IDLE = 0x0, TRACE_RUNNING = 0x1, TRACE_TRIGGERED = 0x2, diff --git a/src/target/xscale.c b/src/target/xscale.c index 6f00aea..bec7165 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -23,6 +23,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -39,7 +40,6 @@ #include "arm_opcodes.h" #include "armv4_5.h" - /* * Important XScale documents available as of October 2009 include: * @@ -59,7 +59,6 @@ * Chip-specific microarchitecture documents may also be useful. */ - /* forward declarations */ static int xscale_resume(struct target *, int current, uint32_t address, int handle_breakpoints, int debug_execution); @@ -72,7 +71,6 @@ static int xscale_set_watchpoint(struct target *, struct watchpoint *); static int xscale_unset_breakpoint(struct target *, struct breakpoint *); static int xscale_read_trace(struct target *); - /* This XScale "debug handler" is loaded into the processor's * mini-ICache, which is 2K of code writable only via JTAG. * @@ -81,11 +79,10 @@ static int xscale_read_trace(struct target *); * with a NUL character. Better would be to generate the constants * and let other code decide names, scoping, and other housekeeping. */ -static /* unsigned const char xscale_debug_handler[] = ... */ +static /* unsigned const char xscale_debug_handler[] = ... */ #include "xscale_debug.h" -static char *const xscale_reg_list[] = -{ +static char *const xscale_reg_list[] = { "XSCALE_MAINID", /* 0 */ "XSCALE_CACHETYPE", "XSCALE_CTRL", @@ -110,8 +107,7 @@ static char *const xscale_reg_list[] = "XSCALE_TXRXCTRL", }; -static const struct xscale_reg xscale_reg_arch_info[] = -{ +static const struct xscale_reg xscale_reg_arch_info[] = { {XSCALE_MAINID, NULL}, {XSCALE_CACHETYPE, NULL}, {XSCALE_CTRL, NULL}, @@ -130,10 +126,10 @@ static const struct xscale_reg xscale_reg_arch_info[] = {XSCALE_TBREG, NULL}, {XSCALE_CHKPT0, NULL}, {XSCALE_CHKPT1, NULL}, - {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */ - {-1, NULL}, /* TX accessed via JTAG */ - {-1, NULL}, /* RX accessed via JTAG */ - {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ + {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */ + {-1, NULL}, /* TX accessed via JTAG */ + {-1, NULL}, /* RX accessed via JTAG */ + {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ }; /* convenience wrapper to access XScale specific registers */ @@ -149,7 +145,7 @@ static int xscale_set_reg_u32(struct reg *reg, uint32_t value) static const char xscale_not[] = "target is not an XScale"; static int xscale_verify_pointer(struct command_context *cmd_ctx, - struct xscale_common *xscale) + struct xscale_common *xscale) { if (xscale->common_magic != XSCALE_COMMON_MAGIC) { command_print(cmd_ctx, xscale_not); @@ -160,10 +156,9 @@ static int xscale_verify_pointer(struct command_context *cmd_ctx, static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state) { - assert (tap != NULL); + assert(tap != NULL); - if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) - { + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { struct scan_field field; uint8_t scratch[4]; @@ -217,8 +212,8 @@ static int xscale_read_dcsr(struct target *target) jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while reading DCSR"); return retval; } @@ -289,16 +284,15 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words xscale_jtag_set_instr(target->tap, XSCALE_DBGTX << xscale->xscale_variant, TAP_IDLE); - jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ + jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above + *could be a no-op */ /* repeat until all words have been collected */ int attempts = 0; - while (words_done < num_words) - { + while (words_done < num_words) { /* schedule reads */ words_scheduled = 0; - for (i = words_done; i < num_words; i++) - { + for (i = words_done; i < num_words; i++) { fields[0].in_value = &field0[i]; jtag_add_pathmove(3, path); @@ -312,32 +306,28 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words words_scheduled++; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while receiving data from debug handler"); break; } /* examine results */ - for (i = words_done; i < num_words; i++) - { - if (!(field0[i] & 1)) - { + for (i = words_done; i < num_words; i++) { + if (!(field0[i] & 1)) { /* move backwards if necessary */ int j; - for (j = i; j < num_words - 1; j++) - { + for (j = i; j < num_words - 1; j++) { field0[j] = field0[j + 1]; field1[j] = field1[j + 1]; } words_scheduled--; } } - if (words_scheduled == 0) - { - if (attempts++==1000) - { - LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts"); + if (words_scheduled == 0) { + if (attempts++ == 1000) { + LOG_ERROR( + "Failed to receiving data from debug handler after 1000 attempts"); retval = ERROR_TARGET_TIMEOUT; break; } @@ -347,7 +337,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words } for (i = 0; i < num_words; i++) - *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32); + *(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32); free(field1); @@ -398,8 +388,7 @@ static int xscale_read_tx(struct target *target, int consume) gettimeofday(&timeout, NULL); timeval_add_time(&timeout, 1, 0); - for (;;) - { + for (;; ) { /* if we want to consume the register content (i.e. clear TX_READY), * we have to go straight from Capture-DR to Shift-DR * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR @@ -407,41 +396,34 @@ static int xscale_read_tx(struct target *target, int consume) if (consume) jtag_add_pathmove(3, path); else - { jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path); - } jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while reading TX"); return ERROR_TARGET_TIMEOUT; } gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) - { + if ((now.tv_sec > timeout.tv_sec) || + ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) { LOG_ERROR("time out reading TX register"); return ERROR_TARGET_TIMEOUT; } if (!((!(field0_in & 1)) && consume)) - { goto done; - } - if (debug_level >= 3) - { + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); - alive_sleep(100); /* avoid flooding the logs */ + alive_sleep(100); /* avoid flooding the logs */ } else - { keep_alive(); - } } - done: +done: if (!(field0_in & 1)) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -486,44 +468,40 @@ static int xscale_write_rx(struct target *target) /* poll until rx_read is low */ LOG_DEBUG("polling RX"); - for (;;) - { + for (;;) { jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while writing RX"); return retval; } gettimeofday(&now, NULL); - if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec))) - { + if ((now.tv_sec > timeout.tv_sec) || + ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) { LOG_ERROR("time out writing RX register"); return ERROR_TARGET_TIMEOUT; } if (!(field0_in & 1)) goto done; - if (debug_level >= 3) - { + if (debug_level >= 3) { LOG_DEBUG("waiting 100ms"); - alive_sleep(100); /* avoid flooding the logs */ + alive_sleep(100); /* avoid flooding the logs */ } else - { keep_alive(); - } } - done: +done: /* set rx_valid */ field2 = 0x1; jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while writing RX"); return retval; } @@ -544,51 +522,43 @@ static int xscale_send(struct target *target, const uint8_t *buffer, int count, XSCALE_DBGRX << xscale->xscale_variant, TAP_IDLE); - bits[0]=3; - t[0]=0; - bits[1]=32; - t[2]=1; - bits[2]=1; + bits[0] = 3; + t[0] = 0; + bits[1] = 32; + t[2] = 1; + bits[2] = 1; int endianness = target->endianness; - while (done_count++ < count) - { - switch (size) - { - case 4: - if (endianness == TARGET_LITTLE_ENDIAN) - { - t[1]=le_to_h_u32(buffer); - } else - { - t[1]=be_to_h_u32(buffer); - } - break; - case 2: - if (endianness == TARGET_LITTLE_ENDIAN) - { - t[1]=le_to_h_u16(buffer); - } else - { - t[1]=be_to_h_u16(buffer); - } - break; - case 1: - t[1]=buffer[0]; - break; - default: - LOG_ERROR("BUG: size neither 4, 2 nor 1"); - return ERROR_COMMAND_SYNTAX_ERROR; + while (done_count++ < count) { + switch (size) { + case 4: + if (endianness == TARGET_LITTLE_ENDIAN) + t[1] = le_to_h_u32(buffer); + else + t[1] = be_to_h_u32(buffer); + break; + case 2: + if (endianness == TARGET_LITTLE_ENDIAN) + t[1] = le_to_h_u16(buffer); + else + t[1] = be_to_h_u16(buffer); + break; + case 1: + t[1] = buffer[0]; + break; + default: + LOG_ERROR("BUG: size neither 4, 2 nor 1"); + return ERROR_COMMAND_SYNTAX_ERROR; } jtag_add_dr_out(target->tap, - 3, - bits, - t, - TAP_IDLE); + 3, + bits, + t, + TAP_IDLE); buffer += size; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while sending data to debug handler"); return retval; } @@ -649,8 +619,8 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask); jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { LOG_ERROR("JTAG error while writing DCSR"); return retval; } @@ -662,14 +632,14 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br } /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */ -static unsigned int parity (unsigned int v) +static unsigned int parity(unsigned int v) { - // unsigned int ov = v; + /* unsigned int ov = v; */ v ^= v >> 16; v ^= v >> 8; v ^= v >> 4; v &= 0xf; - // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); + /* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */ return (0x6996 >> v) & 1; } @@ -714,8 +684,7 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8] fields[1].num_bits = 1; fields[1].out_value = &cmd; - for (word = 0; word < 8; word++) - { + for (word = 0; word < 8; word++) { buf_set_u32(packet, 0, 32, buffer[word]); uint32_t value; @@ -766,39 +735,29 @@ static int xscale_update_vectors(struct target *target) uint32_t low_reset_branch, high_reset_branch; - for (i = 1; i < 8; i++) - { + for (i = 1; i < 8; i++) { /* if there's a static vector specified for this exception, override */ if (xscale->static_high_vectors_set & (1 << i)) - { xscale->high_vectors[i] = xscale->static_high_vectors[i]; - } - else - { + else { retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { /* Some of these reads will fail as part of normal execution */ xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0); } } } - for (i = 1; i < 8; i++) - { + for (i = 1; i < 8; i++) { if (xscale->static_low_vectors_set & (1 << i)) - { xscale->low_vectors[i] = xscale->static_low_vectors[i]; - } - else - { + else { retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]); if (retval == ERROR_TARGET_TIMEOUT) return retval; - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { /* Some of these reads will fail as part of normal execution */ xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0); } @@ -827,28 +786,25 @@ static int xscale_arch_state(struct target *target) struct xscale_common *xscale = target_to_xscale(target); struct arm *arm = &xscale->arm; - static const char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; - static const char *arch_dbg_reason[] = - { + static const char *arch_dbg_reason[] = { "", "\n(processor reset)", "\n(trace buffer full)" }; - if (arm->common_magic != ARM_COMMON_MAGIC) - { + if (arm->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); return ERROR_COMMAND_SYNTAX_ERROR; } arm_arch_state(target); LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s", - state[xscale->armv4_5_mmu.mmu_enabled], - state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], - state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled], - arch_dbg_reason[xscale->arch_debug_reason]); + state[xscale->armv4_5_mmu.mmu_enabled], + state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], + state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled], + arch_dbg_reason[xscale->arch_debug_reason]); return ERROR_OK; } @@ -857,20 +813,17 @@ static int xscale_poll(struct target *target) { int retval = ERROR_OK; - if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) - { + if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) { enum target_state previous_state = target->state; - if ((retval = xscale_read_tx(target, 0)) == ERROR_OK) - { + retval = xscale_read_tx(target, 0); + if (retval == ERROR_OK) { /* there's data to read from the tx register, we entered debug state */ target->state = TARGET_HALTED; /* process debug entry, fetching current mode regs */ retval = xscale_debug_entry(target); - } - else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) - { + } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { LOG_USER("error while polling TX register, reset CPU"); /* here we "lie" so GDB won't get stuck and a reset can be perfomed */ target->state = TARGET_HALTED; @@ -905,11 +858,13 @@ static int xscale_debug_entry(struct target *target) /* clear external dbg break (will be written on next DCSR read) */ xscale->external_debug_break = 0; - if ((retval = xscale_read_dcsr(target)) != ERROR_OK) + retval = xscale_read_dcsr(target); + if (retval != ERROR_OK) return retval; /* get r0, pc, r1 to r7 and cpsr */ - if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK) + retval = xscale_receive(target, buffer, 10); + if (retval != ERROR_OK) return retval; /* move r0 from buffer to register cache */ @@ -925,8 +880,7 @@ static int xscale_debug_entry(struct target *target) LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]); /* move data from buffer to register cache */ - for (i = 1; i <= 7; i++) - { + for (i = 1; i <= 7; i++) { buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); arm->core_cache->reg_list[i].dirty = 1; arm->core_cache->reg_list[i].valid = 1; @@ -936,14 +890,13 @@ static int xscale_debug_entry(struct target *target) arm_set_cpsr(arm, buffer[9]); LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); - if (!is_arm_mode(arm->core_mode)) - { + if (!is_arm_mode(arm->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } LOG_DEBUG("target entered debug state in %s mode", - arm_mode_name(arm->core_mode)); + arm_mode_name(arm->core_mode)); /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ if (arm->spsr) { @@ -951,16 +904,13 @@ static int xscale_debug_entry(struct target *target) buf_set_u32(arm->spsr->value, 0, 32, buffer[7]); arm->spsr->dirty = false; arm->spsr->valid = true; - } - else - { + } else { /* r8 to r14, but no spsr */ xscale_receive(target, buffer, 7); } /* move data from buffer to right banked register in cache */ - for (i = 8; i <= 14; i++) - { + for (i = 8; i <= 14; i++) { struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, buffer[i - 8]); @@ -971,7 +921,7 @@ static int xscale_debug_entry(struct target *target) /* mark xscale regs invalid to ensure they are retrieved from the * debug handler if requested */ for (i = 0; i < xscale->reg_cache->num_regs; i++) - xscale->reg_cache->reg_list[i].valid = 0; + xscale->reg_cache->reg_list[i].valid = 0; /* examine debug reason */ xscale_read_dcsr(target); @@ -980,44 +930,43 @@ static int xscale_debug_entry(struct target *target) /* stored PC (for calculating fixup) */ pc = buf_get_u32(arm->pc->value, 0, 32); - switch (moe) - { - case 0x0: /* Processor reset */ + switch (moe) { + case 0x0: /* Processor reset */ target->debug_reason = DBG_REASON_DBGRQ; xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET; pc -= 4; break; - case 0x1: /* Instruction breakpoint hit */ + case 0x1: /* Instruction breakpoint hit */ target->debug_reason = DBG_REASON_BREAKPOINT; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; pc -= 4; break; - case 0x2: /* Data breakpoint hit */ + case 0x2: /* Data breakpoint hit */ target->debug_reason = DBG_REASON_WATCHPOINT; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; pc -= 4; break; - case 0x3: /* BKPT instruction executed */ + case 0x3: /* BKPT instruction executed */ target->debug_reason = DBG_REASON_BREAKPOINT; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; pc -= 4; break; - case 0x4: /* Ext. debug event */ + case 0x4: /* Ext. debug event */ target->debug_reason = DBG_REASON_DBGRQ; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; pc -= 4; break; - case 0x5: /* Vector trap occured */ + case 0x5: /* Vector trap occured */ target->debug_reason = DBG_REASON_BREAKPOINT; xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; pc -= 4; break; - case 0x6: /* Trace buffer full break */ + case 0x6: /* Trace buffer full break */ target->debug_reason = DBG_REASON_DBGRQ; xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; pc -= 4; break; - case 0x7: /* Reserved (may flag Hot-Debug support) */ + case 0x7: /* Reserved (may flag Hot-Debug support) */ default: LOG_ERROR("Method of Entry is 'Reserved'"); exit(-1); @@ -1028,40 +977,41 @@ static int xscale_debug_entry(struct target *target) buf_set_u32(arm->pc->value, 0, 32, pc); /* on the first debug entry, identify cache type */ - if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) - { + if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) { uint32_t cache_type_reg; /* read cp15 cache type register */ xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]); - cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32); + cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, + 0, + 32); armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache); } - /* examine MMU and Cache settings */ - /* read cp15 control register */ + /* examine MMU and Cache settings + * read cp15 control register */ xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); - xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); + xscale->cp15_control_reg = + buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0; - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0; - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0; + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = + (xscale->cp15_control_reg & 0x4U) ? 1 : 0; + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = + (xscale->cp15_control_reg & 0x1000U) ? 1 : 0; /* tracing enabled, read collected trace data */ - if (xscale->trace.mode != XSCALE_TRACE_DISABLED) - { + if (xscale->trace.mode != XSCALE_TRACE_DISABLED) { xscale_read_trace(target); /* Resume if entered debug due to buffer fill and we're still collecting * trace data. Note that a debug exception due to trace buffer full * can only happen in fill mode. */ - if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) - { - if (--xscale->trace.fill_counter > 0) - xscale_resume(target, 1, 0x0, 1, 0); - } - else /* entered debug for other reason; reset counter */ - xscale->trace.fill_counter = 0; + if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) { + if (--xscale->trace.fill_counter > 0) + xscale_resume(target, 1, 0x0, 1, 0); + } else /* entered debug for other reason; reset counter */ + xscale->trace.fill_counter = 0; } return ERROR_OK; @@ -1072,25 +1022,18 @@ static int xscale_halt(struct target *target) struct xscale_common *xscale = target_to_xscale(target); LOG_DEBUG("target->state: %s", - target_state_name(target)); + target_state_name(target)); - if (target->state == TARGET_HALTED) - { + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; - } - else if (target->state == TARGET_UNKNOWN) - { + } else if (target->state == TARGET_UNKNOWN) { /* this must not happen for a xscale target */ LOG_ERROR("target was in unknown state when halt was requested"); return ERROR_TARGET_INVALID; - } - else if (target->state == TARGET_RESET) - { + } else if (target->state == TARGET_RESET) LOG_DEBUG("target->state == TARGET_RESET"); - } - else - { + else { /* assert external dbg break */ xscale->external_debug_break = 1; xscale_read_dcsr(target); @@ -1107,22 +1050,21 @@ static int xscale_enable_single_step(struct target *target, uint32_t next_pc) struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; - if (xscale->ibcr0_used) - { - struct breakpoint *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe); + if (xscale->ibcr0_used) { + struct breakpoint *ibcr0_bp = + breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe); if (ibcr0_bp) - { xscale_unset_breakpoint(target, ibcr0_bp); - } - else - { - LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); + else { + LOG_ERROR( + "BUG: xscale->ibcr0_used is set, but no breakpoint with that address found"); exit(-1); } } - if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK) + retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1); + if (retval != ERROR_OK) return retval; return ERROR_OK; @@ -1134,7 +1076,8 @@ static int xscale_disable_single_step(struct target *target) struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0]; int retval; - if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK) + retval = xscale_set_reg_u32(ibcr0, 0x0); + if (retval != ERROR_OK) return retval; return ERROR_OK; @@ -1144,8 +1087,7 @@ static void xscale_enable_watchpoints(struct target *target) { struct watchpoint *watchpoint = target->watchpoints; - while (watchpoint) - { + while (watchpoint) { if (watchpoint->set == 0) xscale_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; @@ -1157,8 +1099,7 @@ static void xscale_enable_breakpoints(struct target *target) struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ - while (breakpoint) - { + while (breakpoint) { if (breakpoint->set == 0) xscale_set_breakpoint(target, breakpoint); breakpoint = breakpoint->next; @@ -1167,20 +1108,19 @@ static void xscale_enable_breakpoints(struct target *target) static void xscale_free_trace_data(struct xscale_common *xscale) { - struct xscale_trace_data *td = xscale->trace.data; - while (td) - { - struct xscale_trace_data *next_td = td->next; - if (td->entries) - free(td->entries); - free(td); - td = next_td; - } - xscale->trace.data = NULL; + struct xscale_trace_data *td = xscale->trace.data; + while (td) { + struct xscale_trace_data *next_td = td->next; + if (td->entries) + free(td->entries); + free(td); + td = next_td; + } + xscale->trace.data = NULL; } static int xscale_resume(struct target *target, int current, - uint32_t address, int handle_breakpoints, int debug_execution) + uint32_t address, int handle_breakpoints, int debug_execution) { struct xscale_common *xscale = target_to_xscale(target); struct arm *arm = &xscale->arm; @@ -1190,19 +1130,17 @@ static int xscale_resume(struct target *target, int current, LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (!debug_execution) - { target_free_all_working_areas(target); - } /* update vector tables */ - if ((retval = xscale_update_vectors(target)) != ERROR_OK) + retval = xscale_update_vectors(target); + if (retval != ERROR_OK) return retval; /* current = 1: continue on current pc, otherwise continue at <address> */ @@ -1212,20 +1150,17 @@ static int xscale_resume(struct target *target, int current, current_pc = buf_get_u32(arm->pc->value, 0, 32); /* if we're at the reset vector, we have to simulate the branch */ - if (current_pc == 0x0) - { + if (current_pc == 0x0) { arm_simulate_step(target, NULL); current_pc = buf_get_u32(arm->pc->value, 0, 32); } /* the front-end may request us not to handle breakpoints */ - if (handle_breakpoints) - { + if (handle_breakpoints) { struct breakpoint *breakpoint; breakpoint = breakpoint_find(target, buf_get_u32(arm->pc->value, 0, 32)); - if (breakpoint != NULL) - { + if (breakpoint != NULL) { uint32_t next_pc; enum trace_mode saved_trace_mode; @@ -1234,11 +1169,13 @@ static int xscale_resume(struct target *target, int current, xscale_unset_breakpoint(target, breakpoint); /* calculate PC of next instruction */ - if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) - { + retval = arm_simulate_step(target, &next_pc); + if (retval != ERROR_OK) { uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); + LOG_ERROR( + "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", + current_opcode); } LOG_DEBUG("enable single-step"); @@ -1258,19 +1195,19 @@ static int xscale_resume(struct target *target, int current, LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, buf_get_u32(arm->cpsr->value, 0, 32)); - for (i = 7; i >= 0; i--) - { + for (i = 7; i >= 0; i--) { /* send register */ - xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + xscale_send_u32(target, + buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", - i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, - buf_get_u32(arm->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, - buf_get_u32(arm->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); /* disable trace data collection in xscale_debug_entry() */ saved_trace_mode = xscale->trace.mode; @@ -1301,56 +1238,47 @@ static int xscale_resume(struct target *target, int current, /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ - if (xscale->trace.mode != XSCALE_TRACE_DISABLED) - { - if (xscale->trace.mode == XSCALE_TRACE_FILL) - { - /* If trace enabled in fill mode and starting collection of new set - * of buffers, initialize buffer counter and free previous buffers */ - if (xscale->trace.fill_counter == 0) - { - xscale->trace.fill_counter = xscale->trace.buffer_fill; - xscale_free_trace_data(xscale); - } - } - else /* wrap mode; free previous buffer */ - xscale_free_trace_data(xscale); + if (xscale->trace.mode != XSCALE_TRACE_DISABLED) { + if (xscale->trace.mode == XSCALE_TRACE_FILL) { + /* If trace enabled in fill mode and starting collection of new set + * of buffers, initialize buffer counter and free previous buffers */ + if (xscale->trace.fill_counter == 0) { + xscale->trace.fill_counter = xscale->trace.buffer_fill; + xscale_free_trace_data(xscale); + } + } else /* wrap mode; free previous buffer */ + xscale_free_trace_data(xscale); xscale_send_u32(target, 0x62); xscale_send_u32(target, 0x31); - } - else + } else xscale_send_u32(target, 0x30); /* send CPSR */ xscale_send_u32(target, buf_get_u32(arm->cpsr->value, 0, 32)); LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(arm->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); - for (i = 7; i >= 0; i--) - { + for (i = 7; i >= 0; i--) { /* send register */ xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", - i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32, - buf_get_u32(arm->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; - if (!debug_execution) - { + if (!debug_execution) { /* registers are now invalid */ register_cache_invalidate(arm->core_cache); target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - } - else - { + } else { target->state = TARGET_DEBUG_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); } @@ -1361,7 +1289,7 @@ static int xscale_resume(struct target *target, int current, } static int xscale_step_inner(struct target *target, int current, - uint32_t address, int handle_breakpoints) + uint32_t address, int handle_breakpoints) { struct xscale_common *xscale = target_to_xscale(target); struct arm *arm = &xscale->arm; @@ -1372,36 +1300,42 @@ static int xscale_step_inner(struct target *target, int current, target->debug_reason = DBG_REASON_SINGLESTEP; /* calculate PC of next instruction */ - if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) - { + retval = arm_simulate_step(target, &next_pc); + if (retval != ERROR_OK) { uint32_t current_opcode, current_pc; current_pc = buf_get_u32(arm->pc->value, 0, 32); target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); + LOG_ERROR( + "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", + current_opcode); return retval; } LOG_DEBUG("enable single-step"); - if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK) + retval = xscale_enable_single_step(target, next_pc); + if (retval != ERROR_OK) return retval; /* restore banked registers */ - if ((retval = xscale_restore_banked(target)) != ERROR_OK) + retval = xscale_restore_banked(target); + if (retval != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ - if (xscale->trace.mode != XSCALE_TRACE_DISABLED) - { - if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK) + if (xscale->trace.mode != XSCALE_TRACE_DISABLED) { + retval = xscale_send_u32(target, 0x62); + if (retval != ERROR_OK) return retval; - if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK) + retval = xscale_send_u32(target, 0x31); + if (retval != ERROR_OK) return retval; - } - else - if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK) + } else { + retval = xscale_send_u32(target, 0x30); + if (retval != ERROR_OK) return retval; + } /* send CPSR */ retval = xscale_send_u32(target, @@ -1409,7 +1343,7 @@ static int xscale_step_inner(struct target *target, int current, if (retval != ERROR_OK) return retval; LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(arm->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ @@ -1418,7 +1352,7 @@ static int xscale_step_inner(struct target *target, int current, if (retval != ERROR_OK) return retval; LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, - buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ @@ -1427,7 +1361,7 @@ static int xscale_step_inner(struct target *target, int current, if (retval != ERROR_OK) return retval; LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32, - buf_get_u32(arm->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); @@ -1435,11 +1369,13 @@ static int xscale_step_inner(struct target *target, int current, register_cache_invalidate(arm->core_cache); /* wait for and process debug entry */ - if ((retval = xscale_debug_entry(target)) != ERROR_OK) + retval = xscale_debug_entry(target); + if (retval != ERROR_OK) return retval; LOG_DEBUG("disable single-step"); - if ((retval = xscale_disable_single_step(target)) != ERROR_OK) + retval = xscale_disable_single_step(target); + if (retval != ERROR_OK) return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1448,7 +1384,7 @@ static int xscale_step_inner(struct target *target, int current, } static int xscale_step(struct target *target, int current, - uint32_t address, int handle_breakpoints) + uint32_t address, int handle_breakpoints) { struct arm *arm = target_to_arm(target); struct breakpoint *breakpoint = NULL; @@ -1456,8 +1392,7 @@ static int xscale_step(struct target *target, int current, uint32_t current_pc; int retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1469,9 +1404,9 @@ static int xscale_step(struct target *target, int current, current_pc = buf_get_u32(arm->pc->value, 0, 32); /* if we're at the reset vector, we have to simulate the step */ - if (current_pc == 0x0) - { - if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) + if (current_pc == 0x0) { + retval = arm_simulate_step(target, NULL); + if (retval != ERROR_OK) return retval; current_pc = buf_get_u32(arm->pc->value, 0, 32); LOG_DEBUG("current pc %" PRIx32, current_pc); @@ -1497,9 +1432,7 @@ static int xscale_step(struct target *target, int current, return retval; if (breakpoint) - { xscale_set_breakpoint(target, breakpoint); - } LOG_DEBUG("target stepped"); @@ -1512,7 +1445,7 @@ static int xscale_assert_reset(struct target *target) struct xscale_common *xscale = target_to_xscale(target); LOG_DEBUG("target->state: %s", - target_state_name(target)); + target_state_name(target)); /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG @@ -1539,12 +1472,11 @@ static int xscale_assert_reset(struct target *target) target->state = TARGET_RESET; - if (target->reset_halt) - { - int retval; - if ((retval = target_halt(target)) != ERROR_OK) + if (target->reset_halt) { + int retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } + } return ERROR_OK; } @@ -1565,12 +1497,9 @@ static int xscale_deassert_reset(struct target *target) xscale->dbr1_used = 0; /* mark all hardware breakpoints as unset */ - while (breakpoint) - { + while (breakpoint) { if (breakpoint->type == BKPT_HARD) - { breakpoint->set = 0; - } breakpoint = breakpoint->next; } @@ -1615,9 +1544,8 @@ static int xscale_deassert_reset(struct target *target) */ address = xscale->handler_address; for (unsigned binary_size = sizeof xscale_debug_handler - 1; - binary_size > 0; - binary_size -= buf_cnt, buffer += buf_cnt) - { + binary_size > 0; + binary_size -= buf_cnt, buffer += buf_cnt) { uint32_t cache_line[8]; unsigned i; @@ -1625,20 +1553,16 @@ static int xscale_deassert_reset(struct target *target) if (buf_cnt > 32) buf_cnt = 32; - for (i = 0; i < buf_cnt; i += 4) - { + for (i = 0; i < buf_cnt; i += 4) { /* convert LE buffer to host-endian uint32_t */ cache_line[i / 4] = le_to_h_u32(&buffer[i]); } for (; i < 32; i += 4) - { cache_line[i / 4] = 0xe1a08008; - } /* only load addresses other than the reset vectors */ - if ((address % 0x400) != 0x0) - { + if ((address % 0x400) != 0x0) { retval = xscale_load_ic(target, address, cache_line); if (retval != ERROR_OK) @@ -1646,14 +1570,15 @@ static int xscale_deassert_reset(struct target *target) } address += buf_cnt; - }; + } + ; retval = xscale_load_ic(target, 0x0, - xscale->low_vectors); + xscale->low_vectors); if (retval != ERROR_OK) return retval; retval = xscale_load_ic(target, 0xffff0000, - xscale->high_vectors); + xscale->high_vectors); if (retval != ERROR_OK) return retval; @@ -1670,8 +1595,7 @@ static int xscale_deassert_reset(struct target *target) xscale_write_dcsr(target, 0, 1); target->state = TARGET_RUNNING; - if (!target->reset_halt) - { + if (!target->reset_halt) { jtag_add_sleep(10000); /* we should have entered debug now */ @@ -1687,7 +1611,7 @@ static int xscale_deassert_reset(struct target *target) } static int xscale_read_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode) + int num, enum arm_mode mode) { /** \todo add debug handler support for core register reads */ LOG_ERROR("not implemented"); @@ -1695,7 +1619,7 @@ static int xscale_read_core_reg(struct target *target, struct reg *r, } static int xscale_write_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode, uint32_t value) + int num, enum arm_mode mode, uint32_t value) { /** \todo add debug handler support for core register writes */ LOG_ERROR("not implemented"); @@ -1712,8 +1636,7 @@ static int xscale_full_context(struct target *target) LOG_DEBUG("-"); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1724,8 +1647,7 @@ static int xscale_full_context(struct target *target) * we can't enter User mode on an XScale (unpredictable), * but User shares registers with SYS */ - for (i = 1; i < 7; i++) - { + for (i = 1; i < 7; i++) { enum arm_mode mode = armv4_5_number_to_mode(i); bool valid = true; struct reg *r; @@ -1735,10 +1657,9 @@ static int xscale_full_context(struct target *target) /* check if there are invalid registers in the current mode */ - for (j = 0; valid && j <= 16; j++) - { + for (j = 0; valid && j <= 16; j++) { if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, - mode, j).valid) + mode, j).valid) valid = false; } if (valid) @@ -1763,13 +1684,11 @@ static int xscale_full_context(struct target *target) buf_set_u32(r->value, 0, 32, buffer[7]); r->dirty = false; r->valid = true; - } else { + } else xscale_receive(target, buffer, 7); - } /* move data from buffer to register cache */ - for (j = 8; j <= 14; j++) - { + for (j = 8; j <= 14; j++) { r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, j); @@ -1790,8 +1709,7 @@ static int xscale_restore_banked(struct target *target) int i, j; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1801,8 +1719,7 @@ static int xscale_restore_banked(struct target *target) * USR mode (number 0) in favor of SYS; we can't enter User mode on * an XScale (unpredictable), but they share all registers. */ - for (i = 1; i < 7; i++) - { + for (i = 1; i < 7; i++) { enum arm_mode mode = armv4_5_number_to_mode(i); struct reg *r; @@ -1810,18 +1727,16 @@ static int xscale_restore_banked(struct target *target) continue; /* check if there are dirty registers in this mode */ - for (j = 8; j <= 14; j++) - { + for (j = 8; j <= 14; j++) { if (ARMV4_5_CORE_REG_MODE(arm->core_cache, - mode, j).dirty) + mode, j).dirty) goto dirty; } /* if not USR/SYS, check if the SPSR needs to be written */ - if (mode != ARM_MODE_SYS) - { + if (mode != ARM_MODE_SYS) { if (ARMV4_5_CORE_REG_MODE(arm->core_cache, - mode, 16).dirty) + mode, 16).dirty) goto dirty; } @@ -1858,17 +1773,19 @@ dirty: } static int xscale_read_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { struct xscale_common *xscale = target_to_xscale(target); uint32_t *buf32; uint32_t i; int retval; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, + address, + size, + count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1881,27 +1798,29 @@ static int xscale_read_memory(struct target *target, uint32_t address, return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory read request (command 0x1n, n: access size) */ - if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK) + retval = xscale_send_u32(target, 0x10 | size); + if (retval != ERROR_OK) return retval; /* send base address for read request */ - if ((retval = xscale_send_u32(target, address)) != ERROR_OK) + retval = xscale_send_u32(target, address); + if (retval != ERROR_OK) return retval; /* send number of requested data words */ - if ((retval = xscale_send_u32(target, count)) != ERROR_OK) + retval = xscale_send_u32(target, count); + if (retval != ERROR_OK) return retval; /* receive data from target (count times 32-bit words in host endianness) */ buf32 = malloc(4 * count); - if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK) + retval = xscale_receive(target, buf32, count); + if (retval != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ - for (i = 0; i < count; i++) - { - switch (size) - { + for (i = 0; i < count; i++) { + switch (size) { case 4: target_buffer_set_u32(target, buffer, buf32[i]); buffer += 4; @@ -1922,12 +1841,13 @@ static int xscale_read_memory(struct target *target, uint32_t address, free(buf32); /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval = xscale_read_dcsr(target)) != ERROR_OK) + retval = xscale_read_dcsr(target); + if (retval != ERROR_OK) return retval; - if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) - { + if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) + retval = xscale_send_u32(target, 0x60); + if (retval != ERROR_OK) return retval; return ERROR_TARGET_DATA_ABORT; @@ -1937,7 +1857,7 @@ static int xscale_read_memory(struct target *target, uint32_t address, } static int xscale_read_phys_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t size, uint32_t count, uint8_t *buffer) { struct xscale_common *xscale = target_to_xscale(target); @@ -1947,20 +1867,22 @@ static int xscale_read_phys_memory(struct target *target, uint32_t address, /** \todo: provide a non-stub implementation of this routine. */ LOG_ERROR("%s: %s is not implemented. Disable MMU?", - target_name(target), __func__); + target_name(target), __func__); return ERROR_FAIL; } static int xscale_write_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { struct xscale_common *xscale = target_to_xscale(target); int retval; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, + address, + size, + count); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1973,23 +1895,24 @@ static int xscale_write_memory(struct target *target, uint32_t address, return ERROR_TARGET_UNALIGNED_ACCESS; /* send memory write request (command 0x2n, n: access size) */ - if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK) + retval = xscale_send_u32(target, 0x20 | size); + if (retval != ERROR_OK) return retval; /* send base address for read request */ - if ((retval = xscale_send_u32(target, address)) != ERROR_OK) + retval = xscale_send_u32(target, address); + if (retval != ERROR_OK) return retval; /* send number of requested data words to be written*/ - if ((retval = xscale_send_u32(target, count)) != ERROR_OK) + retval = xscale_send_u32(target, count); + if (retval != ERROR_OK) return retval; /* extract data from host-endian buffer into byte stream */ #if 0 - for (i = 0; i < count; i++) - { - switch (size) - { + for (i = 0; i < count; i++) { + switch (size) { case 4: value = target_buffer_get_u32(target, buffer); xscale_send_u32(target, value); @@ -2011,16 +1934,18 @@ static int xscale_write_memory(struct target *target, uint32_t address, } } #endif - if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK) + retval = xscale_send(target, buffer, count, size); + if (retval != ERROR_OK) return retval; /* examine DCSR, to see if Sticky Abort (SA) got set */ - if ((retval = xscale_read_dcsr(target)) != ERROR_OK) + retval = xscale_read_dcsr(target); + if (retval != ERROR_OK) return retval; - if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) - { + if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) { /* clear SA bit */ - if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK) + retval = xscale_send_u32(target, 0x60); + if (retval != ERROR_OK) return retval; LOG_ERROR("data abort writing memory"); @@ -2031,7 +1956,7 @@ static int xscale_write_memory(struct target *target, uint32_t address, } static int xscale_write_phys_memory(struct target *target, uint32_t address, - uint32_t size, uint32_t count, const uint8_t *buffer) + uint32_t size, uint32_t count, const uint8_t *buffer) { struct xscale_common *xscale = target_to_xscale(target); @@ -2041,12 +1966,12 @@ static int xscale_write_phys_memory(struct target *target, uint32_t address, /** \todo: provide a non-stub implementation of this routine. */ LOG_ERROR("%s: %s is not implemented. Disable MMU?", - target_name(target), __func__); + target_name(target), __func__); return ERROR_FAIL; } static int xscale_bulk_write_memory(struct target *target, uint32_t address, - uint32_t count, const uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { return xscale_write_memory(target, address, 4, count, buffer); } @@ -2068,7 +1993,7 @@ static int xscale_get_ttb(struct target *target, uint32_t *result) } static int xscale_disable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) + int d_u_cache, int i_cache) { struct xscale_common *xscale = target_to_xscale(target); uint32_t cp15_control; @@ -2076,43 +2001,41 @@ static int xscale_disable_mmu_caches(struct target *target, int mmu, /* read cp15 control register */ retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); if (mmu) cp15_control &= ~0x1U; - if (d_u_cache) - { + if (d_u_cache) { /* clean DCache */ retval = xscale_send_u32(target, 0x50); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; retval = xscale_send_u32(target, xscale->cache_clean_address); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* invalidate DCache */ retval = xscale_send_u32(target, 0x51); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; cp15_control &= ~0x4U; } - if (i_cache) - { + if (i_cache) { /* invalidate ICache */ retval = xscale_send_u32(target, 0x52); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; cp15_control &= ~0x1000U; } /* write new cp15 control register */ retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* execute cpwait to ensure outstanding operations complete */ @@ -2121,7 +2044,7 @@ static int xscale_disable_mmu_caches(struct target *target, int mmu, } static int xscale_enable_mmu_caches(struct target *target, int mmu, - int d_u_cache, int i_cache) + int d_u_cache, int i_cache) { struct xscale_common *xscale = target_to_xscale(target); uint32_t cp15_control; @@ -2129,7 +2052,7 @@ static int xscale_enable_mmu_caches(struct target *target, int mmu, /* read cp15 control register */ retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32); @@ -2144,7 +2067,7 @@ static int xscale_enable_mmu_caches(struct target *target, int mmu, /* write new cp15 control register */ retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control); - if (retval !=ERROR_OK) + if (retval != ERROR_OK) return retval; /* execute cpwait to ensure outstanding operations complete */ @@ -2153,163 +2076,137 @@ static int xscale_enable_mmu_caches(struct target *target, int mmu, } static int xscale_set_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { int retval; struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (breakpoint->set) - { + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { + if (breakpoint->type == BKPT_HARD) { uint32_t value = breakpoint->address | 1; - if (!xscale->ibcr0_used) - { + if (!xscale->ibcr0_used) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value); xscale->ibcr0_used = 1; breakpoint->set = 1; /* breakpoint set on first breakpoint register */ - } - else if (!xscale->ibcr1_used) - { + } else if (!xscale->ibcr1_used) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value); xscale->ibcr1_used = 1; breakpoint->set = 2; /* breakpoint set on second breakpoint register */ - } - else - { /* bug: availability previously verified in xscale_add_breakpoint() */ + } else {/* bug: availability previously verified in xscale_add_breakpoint() */ LOG_ERROR("BUG: no hardware comparator available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - } - else if (breakpoint->type == BKPT_SOFT) - { - if (breakpoint->length == 4) - { + } else if (breakpoint->type == BKPT_SOFT) { + if (breakpoint->length == 4) { /* keep the original instruction in target endianness */ - if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 4, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK) - { + /* write the bkpt instruction in target endianness + *(arm7_9->arm_bkpt is host endian) */ + retval = target_write_u32(target, breakpoint->address, + xscale->arm_bkpt); + if (retval != ERROR_OK) return retval; - } - } - else - { + } else { /* keep the original instruction in target endianness */ - if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) - { + retval = target_read_memory(target, breakpoint->address, 2, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - /* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - if ((retval = target_write_u16(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK) - { + /* write the bkpt instruction in target endianness + *(arm7_9->arm_bkpt is host endian) */ + retval = target_write_u16(target, breakpoint->address, + xscale->thumb_bkpt); + if (retval != ERROR_OK) return retval; - } } breakpoint->set = 1; - xscale_send_u32(target, 0x50); /* clean dcache */ + xscale_send_u32(target, 0x50); /* clean dcache */ xscale_send_u32(target, xscale->cache_clean_address); - xscale_send_u32(target, 0x51); /* invalidate dcache */ - xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */ + xscale_send_u32(target, 0x51); /* invalidate dcache */ + xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */ } return ERROR_OK; } static int xscale_add_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { struct xscale_common *xscale = target_to_xscale(target); - if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) - { + if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) { LOG_ERROR("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - if ((breakpoint->length != 2) && (breakpoint->length != 4)) - { + if ((breakpoint->length != 2) && (breakpoint->length != 4)) { LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if (breakpoint->type == BKPT_HARD) - { xscale->ibcr_available--; - } return xscale_set_breakpoint(target, breakpoint); } static int xscale_unset_breakpoint(struct target *target, - struct breakpoint *breakpoint) + struct breakpoint *breakpoint) { int retval; struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!breakpoint->set) - { + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (breakpoint->type == BKPT_HARD) - { - if (breakpoint->set == 1) - { + if (breakpoint->type == BKPT_HARD) { + if (breakpoint->set == 1) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0); xscale->ibcr0_used = 0; - } - else if (breakpoint->set == 2) - { + } else if (breakpoint->set == 2) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0); xscale->ibcr1_used = 0; } breakpoint->set = 0; - } - else - { + } else { /* restore original instruction (kept in target endianness) */ - if (breakpoint->length == 4) - { - if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) - { + if (breakpoint->length == 4) { + retval = target_write_memory(target, breakpoint->address, 4, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } - } - else - { - if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) - { + } else { + retval = target_write_memory(target, breakpoint->address, 2, 1, + breakpoint->orig_instr); + if (retval != ERROR_OK) return retval; - } } breakpoint->set = 0; - xscale_send_u32(target, 0x50); /* clean dcache */ + xscale_send_u32(target, 0x50); /* clean dcache */ xscale_send_u32(target, xscale->cache_clean_address); - xscale_send_u32(target, 0x51); /* invalidate dcache */ - xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */ + xscale_send_u32(target, 0x51); /* invalidate dcache */ + xscale_send_u32(target, 0x52); /* invalidate icache and flush fetch buffers */ } return ERROR_OK; @@ -2319,16 +2216,13 @@ static int xscale_remove_breakpoint(struct target *target, struct breakpoint *br { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (breakpoint->set) - { xscale_unset_breakpoint(target, breakpoint); - } if (breakpoint->type == BKPT_HARD) xscale->ibcr_available++; @@ -2337,21 +2231,19 @@ static int xscale_remove_breakpoint(struct target *target, struct breakpoint *br } static int xscale_set_watchpoint(struct target *target, - struct watchpoint *watchpoint) + struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); uint32_t enable = 0; struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("target not halted"); return ERROR_TARGET_NOT_HALTED; } - switch (watchpoint->rw) - { + switch (watchpoint->rw) { case WPT_READ: enable = 0x3; break; @@ -2367,40 +2259,33 @@ static int xscale_set_watchpoint(struct target *target, /* For watchpoint across more than one word, both DBR registers must be enlisted, with the second used as a mask. */ - if (watchpoint->length > 4) - { - if (xscale->dbr0_used || xscale->dbr1_used) - { - LOG_ERROR("BUG: sufficient hardware comparators unavailable"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } + if (watchpoint->length > 4) { + if (xscale->dbr0_used || xscale->dbr1_used) { + LOG_ERROR("BUG: sufficient hardware comparators unavailable"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } - /* Write mask value to DBR1, based on the length argument. - * Address bits ignored by the comparator are those set in mask. */ - xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], - watchpoint->length - 1); - xscale->dbr1_used = 1; - enable |= 0x100; /* DBCON[M] */ + /* Write mask value to DBR1, based on the length argument. + * Address bits ignored by the comparator are those set in mask. */ + xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], + watchpoint->length - 1); + xscale->dbr1_used = 1; + enable |= 0x100; /* DBCON[M] */ } - if (!xscale->dbr0_used) - { + if (!xscale->dbr0_used) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address); dbcon_value |= enable; xscale_set_reg_u32(dbcon, dbcon_value); watchpoint->set = 1; xscale->dbr0_used = 1; - } - else if (!xscale->dbr1_used) - { + } else if (!xscale->dbr1_used) { xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address); dbcon_value |= enable << 2; xscale_set_reg_u32(dbcon, dbcon_value); watchpoint->set = 2; xscale->dbr1_used = 1; - } - else - { + } else { LOG_ERROR("BUG: no hardware comparator available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -2409,87 +2294,74 @@ static int xscale_set_watchpoint(struct target *target, } static int xscale_add_watchpoint(struct target *target, - struct watchpoint *watchpoint) + struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); - if (xscale->dbr_available < 1) - { - LOG_ERROR("no more watchpoint registers available"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + if (xscale->dbr_available < 1) { + LOG_ERROR("no more watchpoint registers available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if (watchpoint->value) - LOG_WARNING("xscale does not support value, mask arguments; ignoring"); + LOG_WARNING("xscale does not support value, mask arguments; ignoring"); /* check that length is a power of two */ - for (uint32_t len = watchpoint->length; len != 1; len /= 2) - { - if (len % 2) - { - LOG_ERROR("xscale requires that watchpoint length is a power of two"); - return ERROR_COMMAND_ARGUMENT_INVALID; - } + for (uint32_t len = watchpoint->length; len != 1; len /= 2) { + if (len % 2) { + LOG_ERROR("xscale requires that watchpoint length is a power of two"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } } - if (watchpoint->length == 4) /* single word watchpoint */ - { - xscale->dbr_available--; /* one DBR reg used */ - return ERROR_OK; + if (watchpoint->length == 4) { /* single word watchpoint */ + xscale->dbr_available--;/* one DBR reg used */ + return ERROR_OK; } /* watchpoints across multiple words require both DBR registers */ - if (xscale->dbr_available < 2) - { - LOG_ERROR("insufficient watchpoint registers available"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + if (xscale->dbr_available < 2) { + LOG_ERROR("insufficient watchpoint registers available"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - - if (watchpoint->length > watchpoint->address) - { - LOG_ERROR("xscale does not support watchpoints with length " - "greater than address"); - return ERROR_COMMAND_ARGUMENT_INVALID; + + if (watchpoint->length > watchpoint->address) { + LOG_ERROR("xscale does not support watchpoints with length " + "greater than address"); + return ERROR_COMMAND_ARGUMENT_INVALID; } - + xscale->dbr_available = 0; return ERROR_OK; } static int xscale_unset_watchpoint(struct target *target, - struct watchpoint *watchpoint) + struct watchpoint *watchpoint) { struct xscale_common *xscale = target_to_xscale(target); struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON]; uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!watchpoint->set) - { + if (!watchpoint->set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (watchpoint->set == 1) - { - if (watchpoint->length > 4) - { - dbcon_value &= ~0x103; /* clear DBCON[M] as well */ - xscale->dbr1_used = 0; /* DBR1 was used for mask */ - } - else - dbcon_value &= ~0x3; + if (watchpoint->set == 1) { + if (watchpoint->length > 4) { + dbcon_value &= ~0x103; /* clear DBCON[M] as well */ + xscale->dbr1_used = 0; /* DBR1 was used for mask */ + } else + dbcon_value &= ~0x3; xscale_set_reg_u32(dbcon, dbcon_value); xscale->dbr0_used = 0; - } - else if (watchpoint->set == 2) - { + } else if (watchpoint->set == 2) { dbcon_value &= ~0xc; xscale_set_reg_u32(dbcon, dbcon_value); xscale->dbr1_used = 0; @@ -2503,20 +2375,17 @@ static int xscale_remove_watchpoint(struct target *target, struct watchpoint *wa { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("target not halted"); return ERROR_TARGET_NOT_HALTED; } if (watchpoint->set) - { xscale_unset_watchpoint(target, watchpoint); - } if (watchpoint->length > 4) - xscale->dbr_available++; /* both DBR regs now available */ - + xscale->dbr_available++;/* both DBR regs now available */ + xscale->dbr_available++; return ERROR_OK; @@ -2530,27 +2399,18 @@ static int xscale_get_reg(struct reg *reg) /* DCSR, TX and RX are accessible via JTAG */ if (strcmp(reg->name, "XSCALE_DCSR") == 0) - { return xscale_read_dcsr(arch_info->target); - } - else if (strcmp(reg->name, "XSCALE_TX") == 0) - { + else if (strcmp(reg->name, "XSCALE_TX") == 0) { /* 1 = consume register content */ return xscale_read_tx(arch_info->target, 1); - } - else if (strcmp(reg->name, "XSCALE_RX") == 0) - { + } else if (strcmp(reg->name, "XSCALE_RX") == 0) { /* can't read from RX register (host -> debug handler) */ return ERROR_OK; - } - else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) - { + } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) { /* can't (explicitly) read from TXRXCTRL register */ return ERROR_OK; - } - else /* Other DBG registers have to be transfered by the debug handler */ - { - /* send CP read request (command 0x40) */ + } else {/* Other DBG registers have to be transfered by the debug handler + * send CP read request (command 0x40) */ xscale_send_u32(target, 0x40); /* send CP register number */ @@ -2567,7 +2427,7 @@ static int xscale_get_reg(struct reg *reg) return ERROR_OK; } -static int xscale_set_reg(struct reg *reg, uint8_t* buf) +static int xscale_set_reg(struct reg *reg, uint8_t *buf) { struct xscale_reg *arch_info = reg->arch_info; struct target *target = arch_info->target; @@ -2575,29 +2435,20 @@ static int xscale_set_reg(struct reg *reg, uint8_t* buf) uint32_t value = buf_get_u32(buf, 0, 32); /* DCSR, TX and RX are accessible via JTAG */ - if (strcmp(reg->name, "XSCALE_DCSR") == 0) - { + if (strcmp(reg->name, "XSCALE_DCSR") == 0) { buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value); return xscale_write_dcsr(arch_info->target, -1, -1); - } - else if (strcmp(reg->name, "XSCALE_RX") == 0) - { + } else if (strcmp(reg->name, "XSCALE_RX") == 0) { buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value); return xscale_write_rx(arch_info->target); - } - else if (strcmp(reg->name, "XSCALE_TX") == 0) - { + } else if (strcmp(reg->name, "XSCALE_TX") == 0) { /* can't write to TX register (debug-handler -> host) */ return ERROR_OK; - } - else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) - { + } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) { /* can't (explicitly) write to TXRXCTRL register */ return ERROR_OK; - } - else /* Other DBG registers have to be transfered by the debug handler */ - { - /* send CP write request (command 0x41) */ + } else {/* Other DBG registers have to be transfered by the debug handler + * send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); /* send CP register number */ @@ -2645,8 +2496,7 @@ static int xscale_read_trace(struct target *target) int i, j; unsigned int num_checkpoints = 0; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_WARNING("target must be stopped to read trace data"); return ERROR_TARGET_NOT_HALTED; } @@ -2658,16 +2508,14 @@ static int xscale_read_trace(struct target *target) xscale_receive(target, trace_buffer, 258); /* parse buffer backwards to identify address entries */ - for (i = 255; i >= 0; i--) - { + for (i = 255; i >= 0; i--) { /* also count number of checkpointed entries */ if ((trace_buffer[i] & 0xe0) == 0xc0) num_checkpoints++; is_address[i] = 0; if (((trace_buffer[i] & 0xf0) == 0x90) || - ((trace_buffer[i] & 0xf0) == 0xd0)) - { + ((trace_buffer[i] & 0xf0) == 0xd0)) { if (i > 0) is_address[--i] = 1; if (i > 0) @@ -2684,21 +2532,19 @@ static int xscale_read_trace(struct target *target) for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++) ; - if (j == 256) - { + if (j == 256) { LOG_DEBUG("no trace data collected"); return ERROR_XSCALE_NO_TRACE_DATA; } /* account for possible partial address at buffer start (wrap mode only) */ - if (is_address[0]) - { /* first entry is address; complete set of 4? */ + if (is_address[0]) { /* first entry is address; complete set of 4? */ i = 1; while (i < 4) if (!is_address[i++]) break; if (i < 4) - j += i; /* partial address; can't use it */ + j += i; /* partial address; can't use it */ } /* if first valid entry is indirect branch, can't use that either (no address) */ @@ -2706,21 +2552,20 @@ static int xscale_read_trace(struct target *target) j++; /* walk linked list to terminating entry */ - for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next) + for (trace_data_p = &xscale->trace.data; *trace_data_p; + trace_data_p = &(*trace_data_p)->next) ; *trace_data_p = malloc(sizeof(struct xscale_trace_data)); (*trace_data_p)->next = NULL; (*trace_data_p)->chkpt0 = trace_buffer[256]; (*trace_data_p)->chkpt1 = trace_buffer[257]; - (*trace_data_p)->last_instruction = - buf_get_u32(arm->pc->value, 0, 32); + (*trace_data_p)->last_instruction = buf_get_u32(arm->pc->value, 0, 32); (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j)); (*trace_data_p)->depth = 256 - j; (*trace_data_p)->num_checkpoints = num_checkpoints; - for (i = j; i < 256; i++) - { + for (i = j; i < 256; i++) { (*trace_data_p)->entries[i - j].data = trace_buffer[i]; if (is_address[i]) (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS; @@ -2732,7 +2577,7 @@ static int xscale_read_trace(struct target *target) } static int xscale_read_instruction(struct target *target, uint32_t pc, - struct arm_instruction *instruction) + struct arm_instruction *instruction) { struct xscale_common *const xscale = target_to_xscale(target); int i; @@ -2745,50 +2590,43 @@ static int xscale_read_instruction(struct target *target, uint32_t pc, return ERROR_TRACE_IMAGE_UNAVAILABLE; /* search for the section the current instruction belongs to */ - for (i = 0; i < xscale->trace.image->num_sections; i++) - { + for (i = 0; i < xscale->trace.image->num_sections; i++) { if ((xscale->trace.image->sections[i].base_address <= pc) && - (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > pc)) - { + (xscale->trace.image->sections[i].base_address + + xscale->trace.image->sections[i].size > pc)) { section = i; break; } } - if (section == -1) - { + if (section == -1) { /* current instruction couldn't be found in the image */ return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } - if (xscale->trace.core_state == ARM_STATE_ARM) - { + if (xscale->trace.core_state == ARM_STATE_ARM) { uint8_t buf[4]; - if ((retval = image_read_section(xscale->trace.image, section, - pc - xscale->trace.image->sections[section].base_address, - 4, buf, &size_read)) != ERROR_OK) - { + retval = image_read_section(xscale->trace.image, section, + pc - xscale->trace.image->sections[section].base_address, + 4, buf, &size_read); + if (retval != ERROR_OK) { LOG_ERROR("error while reading instruction"); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u32(target, buf); arm_evaluate_opcode(opcode, pc, instruction); - } - else if (xscale->trace.core_state == ARM_STATE_THUMB) - { + } else if (xscale->trace.core_state == ARM_STATE_THUMB) { uint8_t buf[2]; - if ((retval = image_read_section(xscale->trace.image, section, - pc - xscale->trace.image->sections[section].base_address, - 2, buf, &size_read)) != ERROR_OK) - { + retval = image_read_section(xscale->trace.image, section, + pc - xscale->trace.image->sections[section].base_address, + 2, buf, &size_read); + if (retval != ERROR_OK) { LOG_ERROR("error while reading instruction"); return ERROR_TRACE_INSTRUCTION_UNAVAILABLE; } opcode = target_buffer_get_u16(target, buf); thumb_evaluate_opcode(opcode, pc, instruction); - } - else - { + } else { LOG_ERROR("BUG: unknown core state encountered"); exit(-1); } @@ -2796,234 +2634,229 @@ static int xscale_read_instruction(struct target *target, uint32_t pc, return ERROR_OK; } -/* Extract address encoded into trace data. +/* Extract address encoded into trace data. * Write result to address referenced by argument 'target', or 0 if incomplete. */ static inline void xscale_branch_address(struct xscale_trace_data *trace_data, - int i, uint32_t *target) + int i, uint32_t *target) { /* if there are less than four entries prior to the indirect branch message * we can't extract the address */ if (i < 4) *target = 0; - else + else { *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) | (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24); + } } static inline void xscale_display_instruction(struct target *target, uint32_t pc, - struct arm_instruction *instruction, - struct command_context *cmd_ctx) + struct arm_instruction *instruction, + struct command_context *cmd_ctx) { - int retval = xscale_read_instruction(target, pc, instruction); - if (retval == ERROR_OK) - command_print(cmd_ctx, "%s", instruction->text); - else - command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc); + int retval = xscale_read_instruction(target, pc, instruction); + if (retval == ERROR_OK) + command_print(cmd_ctx, "%s", instruction->text); + else + command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc); } static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx) { - struct xscale_common *xscale = target_to_xscale(target); - struct xscale_trace_data *trace_data = xscale->trace.data; - int i, retval; - uint32_t breakpoint_pc; - struct arm_instruction instruction; - uint32_t current_pc = 0; /* initialized when address determined */ - - if (!xscale->trace.image) - LOG_WARNING("No trace image loaded; use 'xscale trace_image'"); - - /* loop for each trace buffer that was loaded from target */ - while (trace_data) - { - int chkpt = 0; /* incremented as checkpointed entries found */ - int j; - - /* FIXME: set this to correct mode when trace buffer is first enabled */ - xscale->trace.core_state = ARM_STATE_ARM; - - /* loop for each entry in this trace buffer */ - for (i = 0; i < trace_data->depth; i++) - { - int exception = 0; - uint32_t chkpt_reg = 0x0; - uint32_t branch_target = 0; - int count; - - /* trace entry type is upper nybble of 'message byte' */ - int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4; - - /* Target addresses of indirect branches are written into buffer - * before the message byte representing the branch. Skip past it */ - if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS) - continue; + struct xscale_common *xscale = target_to_xscale(target); + struct xscale_trace_data *trace_data = xscale->trace.data; + int i, retval; + uint32_t breakpoint_pc; + struct arm_instruction instruction; + uint32_t current_pc = 0;/* initialized when address determined */ - switch (trace_msg_type) - { - case 0: /* Exceptions */ - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - exception = (trace_data->entries[i].data & 0x70) >> 4; - - /* FIXME: vector table may be at ffff0000 */ - branch_target = (trace_data->entries[i].data & 0xf0) >> 2; - break; - - case 8: /* Direct Branch */ - break; - - case 9: /* Indirect Branch */ - xscale_branch_address(trace_data, i, &branch_target); - break; - - case 13: /* Checkpointed Indirect Branch */ - xscale_branch_address(trace_data, i, &branch_target); - if ((trace_data->num_checkpoints == 2) && (chkpt == 0)) - chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */ - else - chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */ - - chkpt++; - break; - - case 12: /* Checkpointed Direct Branch */ - if ((trace_data->num_checkpoints == 2) && (chkpt == 0)) - chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is oldest */ - else - chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and newest */ - - /* if no current_pc, checkpoint will be starting point */ - if (current_pc == 0) - branch_target = chkpt_reg; - - chkpt++; - break; - - case 15: /* Roll-over */ - break; - - default: /* Reserved */ - LOG_WARNING("trace is suspect: invalid trace message byte"); - continue; - - } - - /* If we don't have the current_pc yet, but we did get the branch target - * (either from the trace buffer on indirect branch, or from a checkpoint reg), - * then we can start displaying instructions at the next iteration, with - * branch_target as the starting point. - */ - if (current_pc == 0) - { - current_pc = branch_target; /* remains 0 unless branch_target obtained */ - continue; - } + if (!xscale->trace.image) + LOG_WARNING("No trace image loaded; use 'xscale trace_image'"); + + /* loop for each trace buffer that was loaded from target */ + while (trace_data) { + int chkpt = 0; /* incremented as checkpointed entries found */ + int j; + + /* FIXME: set this to correct mode when trace buffer is first enabled */ + xscale->trace.core_state = ARM_STATE_ARM; + + /* loop for each entry in this trace buffer */ + for (i = 0; i < trace_data->depth; i++) { + int exception = 0; + uint32_t chkpt_reg = 0x0; + uint32_t branch_target = 0; + int count; + + /* trace entry type is upper nybble of 'message byte' */ + int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4; + + /* Target addresses of indirect branches are written into buffer + * before the message byte representing the branch. Skip past it */ + if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS) + continue; + + switch (trace_msg_type) { + case 0: /* Exceptions */ + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + exception = (trace_data->entries[i].data & 0x70) >> 4; + + /* FIXME: vector table may be at ffff0000 */ + branch_target = (trace_data->entries[i].data & 0xf0) >> 2; + break; + + case 8: /* Direct Branch */ + break; + + case 9: /* Indirect Branch */ + xscale_branch_address(trace_data, i, &branch_target); + break; + + case 13: /* Checkpointed Indirect Branch */ + xscale_branch_address(trace_data, i, &branch_target); + if ((trace_data->num_checkpoints == 2) && (chkpt == 0)) + chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is + *oldest */ + else + chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and + *newest */ + + chkpt++; + break; + + case 12: /* Checkpointed Direct Branch */ + if ((trace_data->num_checkpoints == 2) && (chkpt == 0)) + chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is + *oldest */ + else + chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and + *newest */ + + /* if no current_pc, checkpoint will be starting point */ + if (current_pc == 0) + branch_target = chkpt_reg; + + chkpt++; + break; + + case 15:/* Roll-over */ + break; + + default:/* Reserved */ + LOG_WARNING("trace is suspect: invalid trace message byte"); + continue; - /* We have current_pc. Read and display the instructions from the image. - * First, display count instructions (lower nybble of message byte). */ - count = trace_data->entries[i].data & 0x0f; - for (j = 0; j < count; j++) - { - xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); - current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; - } + } - /* An additional instruction is implicitly added to count for - * rollover and some exceptions: undef, swi, prefetch abort. */ - if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) - { - xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); - current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; - } + /* If we don't have the current_pc yet, but we did get the branch target + * (either from the trace buffer on indirect branch, or from a checkpoint reg), + * then we can start displaying instructions at the next iteration, with + * branch_target as the starting point. + */ + if (current_pc == 0) { + current_pc = branch_target; /* remains 0 unless branch_target *obtained */ + continue; + } - if (trace_msg_type == 15) /* rollover */ - continue; + /* We have current_pc. Read and display the instructions from the image. + * First, display count instructions (lower nybble of message byte). */ + count = trace_data->entries[i].data & 0x0f; + for (j = 0; j < count; j++) { + xscale_display_instruction(target, current_pc, &instruction, + cmd_ctx); + current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; + } - if (exception) - { - command_print(cmd_ctx, "--- exception %i ---", exception); - continue; - } - - /* not exception or rollover; next instruction is a branch and is - * not included in the count */ - xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); - - /* for direct branches, extract branch destination from instruction */ - if ((trace_msg_type == 8) || (trace_msg_type == 12)) - { - retval = xscale_read_instruction(target, current_pc, &instruction); - if (retval == ERROR_OK) - current_pc = instruction.info.b_bl_bx_blx.target_address; - else - current_pc = 0; /* branch destination unknown */ - - /* direct branch w/ checkpoint; can also get from checkpoint reg */ - if (trace_msg_type == 12) - { - if (current_pc == 0) - current_pc = chkpt_reg; - else if (current_pc != chkpt_reg) /* sanity check */ - LOG_WARNING("trace is suspect: checkpoint register " - "inconsistent with adddress from image"); + /* An additional instruction is implicitly added to count for + * rollover and some exceptions: undef, swi, prefetch abort. */ + if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) { + xscale_display_instruction(target, current_pc, &instruction, + cmd_ctx); + current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; } - if (current_pc == 0) - command_print(cmd_ctx, "address unknown"); + if (trace_msg_type == 15) /* rollover */ + continue; - continue; - } + if (exception) { + command_print(cmd_ctx, "--- exception %i ---", exception); + continue; + } - /* indirect branch; the branch destination was read from trace buffer */ - if ((trace_msg_type == 9) || (trace_msg_type == 13)) - { - current_pc = branch_target; + /* not exception or rollover; next instruction is a branch and is + * not included in the count */ + xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); - /* sanity check (checkpoint reg is redundant) */ - if ((trace_msg_type == 13) && (chkpt_reg != branch_target)) - LOG_WARNING("trace is suspect: checkpoint register " - "inconsistent with address from trace buffer"); - } + /* for direct branches, extract branch destination from instruction */ + if ((trace_msg_type == 8) || (trace_msg_type == 12)) { + retval = xscale_read_instruction(target, current_pc, &instruction); + if (retval == ERROR_OK) + current_pc = instruction.info.b_bl_bx_blx.target_address; + else + current_pc = 0; /* branch destination unknown */ + + /* direct branch w/ checkpoint; can also get from checkpoint reg */ + if (trace_msg_type == 12) { + if (current_pc == 0) + current_pc = chkpt_reg; + else if (current_pc != chkpt_reg) /* sanity check */ + LOG_WARNING("trace is suspect: checkpoint register " + "inconsistent with adddress from image"); + } - } /* END: for (i = 0; i < trace_data->depth; i++) */ + if (current_pc == 0) + command_print(cmd_ctx, "address unknown"); - breakpoint_pc = trace_data->last_instruction; /* used below */ - trace_data = trace_data->next; + continue; + } - } /* END: while (trace_data) */ + /* indirect branch; the branch destination was read from trace buffer */ + if ((trace_msg_type == 9) || (trace_msg_type == 13)) { + current_pc = branch_target; - /* Finally... display all instructions up to the value of the pc when the - * debug break occurred (saved when trace data was collected from target). - * This is necessary because the trace only records execution branches and 16 - * consecutive instructions (rollovers), so last few typically missed. - */ - if (current_pc == 0) - return ERROR_OK; /* current_pc was never found */ + /* sanity check (checkpoint reg is redundant) */ + if ((trace_msg_type == 13) && (chkpt_reg != branch_target)) + LOG_WARNING("trace is suspect: checkpoint register " + "inconsistent with address from trace buffer"); + } + + } /* END: for (i = 0; i < trace_data->depth; i++) */ + + breakpoint_pc = trace_data->last_instruction; /* used below */ + trace_data = trace_data->next; + + } /* END: while (trace_data) */ + + /* Finally... display all instructions up to the value of the pc when the + * debug break occurred (saved when trace data was collected from target). + * This is necessary because the trace only records execution branches and 16 + * consecutive instructions (rollovers), so last few typically missed. + */ + if (current_pc == 0) + return ERROR_OK;/* current_pc was never found */ - /* how many instructions remaining? */ - int gap_count = (breakpoint_pc - current_pc) / - (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2); + /* how many instructions remaining? */ + int gap_count = (breakpoint_pc - current_pc) / + (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2); - /* should never be negative or over 16, but verify */ - if (gap_count < 0 || gap_count > 16) - { - LOG_WARNING("trace is suspect: excessive gap at end of trace"); - return ERROR_OK; /* bail; large number or negative value no good */ - } + /* should never be negative or over 16, but verify */ + if (gap_count < 0 || gap_count > 16) { + LOG_WARNING("trace is suspect: excessive gap at end of trace"); + return ERROR_OK;/* bail; large number or negative value no good */ + } - /* display remaining instructions */ - for (i = 0; i < gap_count; i++) - { - xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); - current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; - } + /* display remaining instructions */ + for (i = 0; i < gap_count; i++) { + xscale_display_instruction(target, current_pc, &instruction, cmd_ctx); + current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2; + } - return ERROR_OK; + return ERROR_OK; } static const struct reg_arch_type xscale_reg_type = { @@ -3051,8 +2884,7 @@ static void xscale_build_reg_cache(struct target *target) (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg)); (*cache_p)->num_regs = num_regs; - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { (*cache_p)->reg_list[i].name = xscale_reg_list[i]; (*cache_p)->reg_list[i].value = calloc(4, 1); (*cache_p)->reg_list[i].dirty = 0; @@ -3068,14 +2900,14 @@ static void xscale_build_reg_cache(struct target *target) } static int xscale_init_target(struct command_context *cmd_ctx, - struct target *target) + struct target *target) { xscale_build_reg_cache(target); return ERROR_OK; } static int xscale_init_arch_info(struct target *target, - struct xscale_common *xscale, struct jtag_tap *tap, const char *variant) + struct xscale_common *xscale, struct jtag_tap *tap, const char *variant) { struct arm *arm; uint32_t high_reset_branch, low_reset_branch; @@ -3091,13 +2923,13 @@ static int xscale_init_arch_info(struct target *target, int ir_length = 0; if (strcmp(variant, "pxa250") == 0 - || strcmp(variant, "pxa255") == 0 - || strcmp(variant, "pxa26x") == 0) + || strcmp(variant, "pxa255") == 0 + || strcmp(variant, "pxa26x") == 0) ir_length = 5; else if (strcmp(variant, "pxa27x") == 0 - || strcmp(variant, "ixp42x") == 0 - || strcmp(variant, "ixp45x") == 0 - || strcmp(variant, "ixp46x") == 0) + || strcmp(variant, "ixp42x") == 0 + || strcmp(variant, "ixp45x") == 0 + || strcmp(variant, "ixp46x") == 0) ir_length = 7; else if (strcmp(variant, "pxa3xx") == 0) ir_length = 11; @@ -3136,8 +2968,7 @@ static int xscale_init_arch_info(struct target *target, xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0); xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0); - for (i = 1; i <= 7; i++) - { + for (i = 1; i <= 7; i++) { xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0); xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0); } @@ -3157,7 +2988,7 @@ static int xscale_init_arch_info(struct target *target, xscale->dbr1_used = 0; LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints", - target_name(target)); + target_name(target)); xscale->arm_bkpt = ARMV5_BKPT(0x0); xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; @@ -3215,12 +3046,10 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command) uint32_t handler_address; if (CMD_ARGC < 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } - if ((target = get_target(CMD_ARGV[0])) == NULL) - { + target = get_target(CMD_ARGV[0]); + if (target == NULL) { LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } @@ -3234,12 +3063,10 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command) if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) || ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800))) - { xscale->handler_address = handler_address; - } - else - { - LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); + else { + LOG_ERROR( + "xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800"); return ERROR_FAIL; } @@ -3254,13 +3081,10 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command) uint32_t cache_clean_address; if (CMD_ARGC < 2) - { return ERROR_COMMAND_SYNTAX_ERROR; - } target = get_target(CMD_ARGV[0]); - if (target == NULL) - { + if (target == NULL) { LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } @@ -3272,13 +3096,9 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address); if (cache_clean_address & 0xffff) - { LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned"); - } else - { xscale->cache_clean_address = cache_clean_address; - } return ERROR_OK; } @@ -3297,7 +3117,7 @@ COMMAND_HANDLER(xscale_handle_cache_info_command) } static int xscale_virt2phys(struct target *target, - uint32_t virtual, uint32_t *physical) + uint32_t virtual, uint32_t *physical) { struct xscale_common *xscale = target_to_xscale(target); uint32_t cb; @@ -3320,8 +3140,7 @@ static int xscale_mmu(struct target *target, int *enabled) { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_INVALID; } @@ -3339,14 +3158,12 @@ COMMAND_HANDLER(xscale_handle_mmu_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { bool enable; COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); if (enable) @@ -3356,7 +3173,8 @@ COMMAND_HANDLER(xscale_handle_mmu_command) xscale->armv4_5_mmu.mmu_enabled = enable; } - command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); + command_print(CMD_CTX, "mmu %s", + (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); return ERROR_OK; } @@ -3370,8 +3188,7 @@ COMMAND_HANDLER(xscale_handle_idcache_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -3379,8 +3196,7 @@ COMMAND_HANDLER(xscale_handle_idcache_command) bool icache = false; if (strcmp(CMD_NAME, "icache") == 0) icache = true; - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { bool enable; COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); if (icache) { @@ -3399,8 +3215,8 @@ COMMAND_HANDLER(xscale_handle_idcache_command) } bool enabled = icache ? - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled : - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled; + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled : + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled; const char *msg = enabled ? "enabled" : "disabled"; command_print(CMD_CTX, "%s %s", CMD_NAME, msg); @@ -3418,13 +3234,13 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command) return retval; if (CMD_ARGC < 1) - { - return ERROR_COMMAND_SYNTAX_ERROR; - } - else - { + return ERROR_COMMAND_SYNTAX_ERROR; + else { COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch); - buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch); + buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, + 16, + 8, + xscale->vector_catch); xscale_write_dcsr(target, -1, -1); } @@ -3445,24 +3261,28 @@ COMMAND_HANDLER(xscale_handle_vector_table_command) if (retval != ERROR_OK) return retval; - if (CMD_ARGC == 0) /* print current settings */ - { + if (CMD_ARGC == 0) { /* print current settings */ int idx; command_print(CMD_CTX, "active user-set static vectors:"); for (idx = 1; idx < 8; idx++) if (xscale->static_low_vectors_set & (1 << idx)) - command_print(CMD_CTX, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); + command_print(CMD_CTX, + "low %d: 0x%" PRIx32, + idx, + xscale->static_low_vectors[idx]); for (idx = 1; idx < 8; idx++) if (xscale->static_high_vectors_set & (1 << idx)) - command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); + command_print(CMD_CTX, + "high %d: 0x%" PRIx32, + idx, + xscale->static_high_vectors[idx]); return ERROR_OK; } if (CMD_ARGC != 3) err = 1; - else - { + else { int idx; COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx); uint32_t vec; @@ -3471,17 +3291,13 @@ COMMAND_HANDLER(xscale_handle_vector_table_command) if (idx < 1 || idx >= 8) err = 1; - if (!err && strcmp(CMD_ARGV[0], "low") == 0) - { + if (!err && strcmp(CMD_ARGV[0], "low") == 0) { xscale->static_low_vectors_set |= (1<<idx); xscale->static_low_vectors[idx] = vec; - } - else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) - { + } else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) { xscale->static_high_vectors_set |= (1<<idx); xscale->static_high_vectors[idx] = vec; - } - else + } else err = 1; } @@ -3503,58 +3319,49 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (CMD_ARGC >= 1) - { - if (strcmp("enable", CMD_ARGV[0]) == 0) - xscale->trace.mode = XSCALE_TRACE_WRAP; /* default */ - else if (strcmp("disable", CMD_ARGV[0]) == 0) - xscale->trace.mode = XSCALE_TRACE_DISABLED; - else - return ERROR_COMMAND_SYNTAX_ERROR; + if (CMD_ARGC >= 1) { + if (strcmp("enable", CMD_ARGV[0]) == 0) + xscale->trace.mode = XSCALE_TRACE_WRAP; /* default */ + else if (strcmp("disable", CMD_ARGV[0]) == 0) + xscale->trace.mode = XSCALE_TRACE_DISABLED; + else + return ERROR_COMMAND_SYNTAX_ERROR; } - if (CMD_ARGC >= 2 && xscale->trace.mode != XSCALE_TRACE_DISABLED) - { - if (strcmp("fill", CMD_ARGV[1]) == 0) - { - int buffcount = 1; /* default */ - if (CMD_ARGC >= 3) - COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount); - if (buffcount < 1) /* invalid */ - { - command_print(CMD_CTX, "fill buffer count must be > 0"); - xscale->trace.mode = XSCALE_TRACE_DISABLED; - return ERROR_COMMAND_SYNTAX_ERROR; - } - xscale->trace.buffer_fill = buffcount; - xscale->trace.mode = XSCALE_TRACE_FILL; - } - else if (strcmp("wrap", CMD_ARGV[1]) == 0) - xscale->trace.mode = XSCALE_TRACE_WRAP; - else - { - xscale->trace.mode = XSCALE_TRACE_DISABLED; - return ERROR_COMMAND_SYNTAX_ERROR; - } - } - - if (xscale->trace.mode != XSCALE_TRACE_DISABLED) - { - char fill_string[12]; - sprintf(fill_string, "fill %" PRId32, xscale->trace.buffer_fill); - command_print(CMD_CTX, "trace buffer enabled (%s)", - (xscale->trace.mode == XSCALE_TRACE_FILL) - ? fill_string : "wrap"); + if (CMD_ARGC >= 2 && xscale->trace.mode != XSCALE_TRACE_DISABLED) { + if (strcmp("fill", CMD_ARGV[1]) == 0) { + int buffcount = 1; /* default */ + if (CMD_ARGC >= 3) + COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount); + if (buffcount < 1) { /* invalid */ + command_print(CMD_CTX, "fill buffer count must be > 0"); + xscale->trace.mode = XSCALE_TRACE_DISABLED; + return ERROR_COMMAND_SYNTAX_ERROR; + } + xscale->trace.buffer_fill = buffcount; + xscale->trace.mode = XSCALE_TRACE_FILL; + } else if (strcmp("wrap", CMD_ARGV[1]) == 0) + xscale->trace.mode = XSCALE_TRACE_WRAP; + else { + xscale->trace.mode = XSCALE_TRACE_DISABLED; + return ERROR_COMMAND_SYNTAX_ERROR; + } } - else - command_print(CMD_CTX, "trace buffer disabled"); - + + if (xscale->trace.mode != XSCALE_TRACE_DISABLED) { + char fill_string[12]; + sprintf(fill_string, "fill %" PRId32, xscale->trace.buffer_fill); + command_print(CMD_CTX, "trace buffer enabled (%s)", + (xscale->trace.mode == XSCALE_TRACE_FILL) + ? fill_string : "wrap"); + } else + command_print(CMD_CTX, "trace buffer disabled"); + dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32); if (xscale->trace.mode == XSCALE_TRACE_FILL) xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2); @@ -3571,16 +3378,13 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) int retval; if (CMD_ARGC < 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - if (xscale->trace.image) - { + if (xscale->trace.image) { image_close(xscale->trace.image); free(xscale->trace.image); command_print(CMD_CTX, "previously loaded image found and closed"); @@ -3591,18 +3395,14 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) xscale->trace.image->start_address_set = 0; /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */ - if (CMD_ARGC >= 2) - { + if (CMD_ARGC >= 2) { xscale->trace.image->base_address_set = 1; COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address); - } - else - { + } else xscale->trace.image->base_address_set = 0; - } - if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) - { + if (image_open(xscale->trace.image, CMD_ARGV[0], + (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) { free(xscale->trace.image); xscale->trace.image = NULL; return ERROR_OK; @@ -3623,32 +3423,25 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } if (CMD_ARGC < 1) - { return ERROR_COMMAND_SYNTAX_ERROR; - } trace_data = xscale->trace.data; - if (!trace_data) - { + if (!trace_data) { command_print(CMD_CTX, "no trace data collected"); return ERROR_OK; } if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) - { return ERROR_OK; - } - while (trace_data) - { + while (trace_data) { int i; fileio_write_u32(&file, trace_data->chkpt0); @@ -3657,7 +3450,8 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) fileio_write_u32(&file, trace_data->depth); for (i = 0; i < trace_data->depth; i++) - fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16)); + fileio_write_u32(&file, trace_data->entries[i].data | + ((trace_data->entries[i].type & 0xffff) << 16)); trace_data = trace_data->next; } @@ -3692,61 +3486,56 @@ COMMAND_HANDLER(xscale_handle_cp15) if (retval != ERROR_OK) return retval; - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } uint32_t reg_no = 0; struct reg *reg = NULL; - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no); /*translate from xscale cp15 register no to openocd register*/ - switch (reg_no) - { - case 0: - reg_no = XSCALE_MAINID; - break; - case 1: - reg_no = XSCALE_CTRL; - break; - case 2: - reg_no = XSCALE_TTB; - break; - case 3: - reg_no = XSCALE_DAC; - break; - case 5: - reg_no = XSCALE_FSR; - break; - case 6: - reg_no = XSCALE_FAR; - break; - case 13: - reg_no = XSCALE_PID; - break; - case 15: - reg_no = XSCALE_CPACCESS; - break; - default: - command_print(CMD_CTX, "invalid register number"); - return ERROR_COMMAND_SYNTAX_ERROR; + switch (reg_no) { + case 0: + reg_no = XSCALE_MAINID; + break; + case 1: + reg_no = XSCALE_CTRL; + break; + case 2: + reg_no = XSCALE_TTB; + break; + case 3: + reg_no = XSCALE_DAC; + break; + case 5: + reg_no = XSCALE_FSR; + break; + case 6: + reg_no = XSCALE_FAR; + break; + case 13: + reg_no = XSCALE_PID; + break; + case 15: + reg_no = XSCALE_CPACCESS; + break; + default: + command_print(CMD_CTX, "invalid register number"); + return ERROR_COMMAND_SYNTAX_ERROR; } reg = &xscale->reg_cache->reg_list[reg_no]; } - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; /* read cp15 control register */ xscale_get_reg(reg); value = buf_get_u32(reg->value, 0, 32); - command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value); - } - else if (CMD_ARGC == 2) - { + command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), + value); + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); @@ -3761,11 +3550,8 @@ COMMAND_HANDLER(xscale_handle_cp15) /* execute cpwait to ensure outstanding operations complete */ xscale_send_u32(target, 0x53); - } - else - { - return ERROR_COMMAND_SYNTAX_ERROR; - } + } else + return ERROR_COMMAND_SYNTAX_ERROR; return ERROR_OK; } @@ -3888,8 +3674,7 @@ static const struct command_registration xscale_command_handlers[] = { COMMAND_REGISTRATION_DONE }; -struct target_type xscale_target = -{ +struct target_type xscale_target = { .name = "xscale", .poll = xscale_poll, diff --git a/src/target/xscale.h b/src/target/xscale.h index 49d4c71..7213db7 100644 --- a/src/target/xscale.h +++ b/src/target/xscale.h @@ -20,6 +20,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifndef XSCALE_H #define XSCALE_H @@ -41,27 +42,23 @@ #define XSCALE_IXP4XX_PXA2XX 0x0 #define XSCALE_PXA3XX 0x4 -enum xscale_debug_reason -{ +enum xscale_debug_reason { XSCALE_DBG_REASON_GENERIC, XSCALE_DBG_REASON_RESET, XSCALE_DBG_REASON_TB_FULL, }; -enum xscale_trace_entry_type -{ +enum xscale_trace_entry_type { XSCALE_TRACE_MESSAGE = 0x0, XSCALE_TRACE_ADDRESS = 0x1, }; -struct xscale_trace_entry -{ +struct xscale_trace_entry { uint8_t data; enum xscale_trace_entry_type type; }; -struct xscale_trace_data -{ +struct xscale_trace_data { struct xscale_trace_entry *entries; int depth; uint32_t chkpt0; @@ -71,25 +68,22 @@ struct xscale_trace_data struct xscale_trace_data *next; }; -enum trace_mode -{ - XSCALE_TRACE_DISABLED, - XSCALE_TRACE_FILL, - XSCALE_TRACE_WRAP +enum trace_mode { + XSCALE_TRACE_DISABLED, + XSCALE_TRACE_FILL, + XSCALE_TRACE_WRAP }; -struct xscale_trace -{ +struct xscale_trace { struct image *image; /* source for target opcodes */ struct xscale_trace_data *data; /* linked list of collected trace data */ int buffer_fill; /* maximum number of trace runs to read */ - int fill_counter; /* running count during trace collection */ - enum trace_mode mode; + int fill_counter; /* running count during trace collection */ + enum trace_mode mode; enum arm_state core_state; /* current core state (ARM, Thumb) */ }; -struct xscale_common -{ +struct xscale_common { /* armv4/5 common stuff */ struct arm arm; @@ -147,18 +141,15 @@ struct xscale_common static inline struct xscale_common * target_to_xscale(struct target *target) { - return container_of(target->arch_info, struct xscale_common, - arm); + return container_of(target->arch_info, struct xscale_common, arm); } -struct xscale_reg -{ +struct xscale_reg { int dbg_handler_number; struct target *target; }; -enum -{ +enum { XSCALE_MAINID, /* 0 */ XSCALE_CACHETYPE, XSCALE_CTRL, |