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-rw-r--r--src/target/riscv/riscv-013.c4
-rw-r--r--src/target/riscv/riscv.c4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index b150b13..12194d6 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1056,6 +1056,10 @@ static unsigned register_size(struct target *target, unsigned number)
return riscv_xlen(target);
}
+/**
+ * Immediately write the new value to the requested register. This mechanism
+ * bypasses any caches.
+ */
static int register_write_direct(struct target *target, unsigned number,
uint64_t value)
{
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index b171469..c599ef2 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1763,6 +1763,10 @@ bool riscv_has_register(struct target *target, int hartid, int regid)
return 1;
}
+/**
+ * This function is called when the debug user wants to change the value of a
+ * register. The new value may be cached, and may not be written until the hart
+ * is running again. */
int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
{
return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);