Merge commit '9f23a1d7c1e27c556ef9787b9d3f263f5c1ecf24' into from_upstream

Conflicts:
	HACKING
	src/target/riscv/riscv-013.c

Change-Id: I43ccb143cae8daa39212d66a8824ae3ad2af6fef

16 files changed, 654 insertions, 39 deletions

diff --git a/tcl/board/calao-usb-a9g20-c01.cfg b/tcl/board/calao-usb-a9g20-c01.cfg
index 6c4bd40..d201786 100644
--- a/tcl/board/calao-usb-a9g20-c01.cfg
+++ b/tcl/board/calao-usb-a9g20-c01.cfg
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # CALAO Systems USB-A9G20-C01
+# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang
 
 adapter driver ftdi
 ftdi device_desc "USB-A9G20"
@@ -12,3 +13,160 @@ ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
 transport select jtag
 
 source [find target/at91sam9g20.cfg]
+source [find mem_helper.tcl]
+
+proc at91sam9g20_reset_start { } {
+
+        # Make sure that the jtag is running slow, since there are a number of different ways the board
+        # can be configured coming into this state that can cause communication problems with the jtag
+        # adapter.  Also since this call can be made following a "reset init" where fast memory accesses
+        # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower
+        # jtag speed without causing GDB keep alive problem.
+
+        arm7_9 fast_memory_access disable
+        adapter speed 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+        halt 0                            ;# Make sure processor is halted, or error will result in following steps.
+        wait_halt 10000
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+proc at91sam9g20_reset_init { } {
+
+        # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+        # a number of steps that must be carefully performed.  The process outline below follows the
+        # recommended procedure outlined in the AT91SAM9G20 technical manual.
+        #
+        # Several key and very important things to keep in mind:
+        # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+        mww 0xfffffd44 0x00008000      ;# WDT_MR : disable watchdog.
+
+        # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register.
+
+        mww 0xfffffc20 0x00000002
+
+        # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).
+        # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+        mww 0xfffffc28 0x20843F02
+        while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }
+
+        # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+        # Wait for MCKRDY signal from PMC_SR to assert.
+
+        mww 0xfffffc30 0x00001300
+        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+        # Now change PMC_MCKR register to select PLLA.
+        # Wait for MCKRDY signal from PMC_SR to assert.
+
+        mww 0xfffffc30 0x00001302
+        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+        # Processor and master clocks are now operating and stable at maximum frequency possible:
+        #       -> MCLK = 133.000 MHz
+        #       -> PCLK = 400.000 MHz
+
+        # Switch to fast JTAG speed
+
+        adapter speed 9500
+
+        # Enable faster DCC downloads.
+
+        arm7_9 dcc_downloads enable
+        arm7_9 fast_memory_access enable
+
+        # To be able to use external SDRAM, several peripheral configuration registers must
+        # be modified.  The first change is made to PIO_ASR to select peripheral functions
+        # for D15 through D31.  The second change is made to the PIO_PDR register to disable
+        # this for D15 through D31.
+
+        mww 0xfffff870 0xffff0000
+        mww 0xfffff804 0xffff0000
+
+        # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+        # using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+        # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+        mww 0xffffef1c 0x000000a
+
+        # The USB-A9G20 Embedded computer has built-in NandFlash.  The exact physical timing characteristics
+        # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+        # four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+        mww 0xffffec30 0x00020002
+        mww 0xffffec34 0x04040404
+        mww 0xffffec38 0x00070007
+        mww 0xffffec3c 0x00030003
+
+        # Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+        # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+        # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+        # into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+        # of 133.000 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+        #
+        #       CAS latency = 3 cycles
+        #       TXSR = 10 cycles
+        #       TRAS = 6 cycles
+        #       TRCD = 3 cycles
+        #       TRP = 3 cycles
+        #       TRC = 9 cycles
+        #       TWR = 2 cycles
+        #       9 column, 13 row, 4 banks
+        #       refresh equal to or less then 7.8 us for commercial/industrial rated devices
+        #
+        #       Thus SDRAM_CR = 0xa6339279
+
+        mww 0xffffea08 0xa6339279
+
+        # Memory Device Type: SDRAM (low-power would be 0x1)
+        mww 0xffffea24 0x00000000
+
+        # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+        # the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x00000001
+        mww 0x20000000 0
+
+        # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+        # value into the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x00000002
+        mww 0x20000000 0
+
+        # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+        # zero values eight times into the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x4
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+        mww 0x20000000 0
+
+        # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+        # the starting memory location for the SDRAM.
+
+        mww 0xffffea00 0x3
+        mww 0x20000000 0
+
+        # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
+        # memory location for the SDRAM.
+
+        mww 0xffffea00 0x0
+        mww 0x20000000 0
+
+        # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+        mww 0xffffea04 0x0000039c
+}
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
diff --git a/tcl/board/st_nucleo_8l152r8.cfg b/tcl/board/st_nucleo_8l152r8.cfg
index f06d749..7cb8bce 100644
--- a/tcl/board/st_nucleo_8l152r8.cfg
+++ b/tcl/board/st_nucleo_8l152r8.cfg
@@ -7,6 +7,6 @@ source [find interface/stlink-dap.cfg]
 
 transport select swim
 
-source [find target/stm8l152.cfg]
+source [find target/stm8l15xx8.cfg]
 
 reset_config srst_only
diff --git a/tcl/board/vd_xt8_jtag.cfg b/tcl/board/vd_xt8_jtag.cfg
new file mode 100644
index 0000000..867b9e7
--- /dev/null
+++ b/tcl/board/vd_xt8_jtag.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Xtensa xt8 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME xt8
+set CPUTAPID 0x120034e5
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg
+#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000
+#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+source  [find target/xtensa-core-xt8.cfg]
diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg
index 7071e5e..4c84792 100644
--- a/tcl/cpld/jtagspi.cfg
+++ b/tcl/cpld/jtagspi.cfg
@@ -23,11 +23,21 @@ if { [info exists FLASHNAME] } {
 target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
 flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
 
-proc jtagspi_init {chain_id proxy_bit} {
+# initialize jtagspi flash
+# chain_id: identifier of pld (you can get a list with 'pld devices')
+# proxy_bit: file with bitstream connecting JTAG and SPI interface in the PLD.
+# release_from_pwr_down_cmd: optional, command sent to spi flash before probing.
+#                            ex: 0xAB to release from power-dowm.
+#                            Just omit it to not send a command.
+
+proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} {
 	# load proxy bitstream $proxy_bit and probe spi flash
 	global _FLASHNAME
 	pld load $chain_id $proxy_bit
 	reset halt
+	if {$release_from_pwr_down_cmd != -1} {
+		jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd
+	}
 	flash probe $_FLASHNAME
 }
 
diff --git a/tcl/target/qn908x.cfg b/tcl/target/qn908x.cfg
new file mode 100644
index 0000000..ac3e06b
--- /dev/null
+++ b/tcl/target/qn908x.cfg
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# NXP QN908x Cortex-M4F with 128 KiB SRAM
+
+source [find target/swj-dp.tcl]
+
+set CHIPNAME qn908x
+set CHIPSERIES qn9080
+if { ![info exists WORKAREASIZE] } {
+  set WORKAREASIZE 0x20000
+}
+
+# SWD IDCODE (Cortex M4).
+set CPUTAPID 0x2ba01477
+
+swj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID
+dap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu
+
+set TARGETNAME $CHIPNAME.cpu
+target create $TARGETNAME cortex_m -dap $CHIPNAME.dap
+
+# SRAM is mapped at 0x04000000.
+$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE
+
+# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum]
+# The base must be set as 0x01000000, and the size parameter is unused.
+set FLASHNAME $CHIPNAME.flash
+flash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum
+
+# We write directly to flash memory over this adapter interface. For debugging
+# this could in theory be faster (the Core clock on reset is normally at 32MHz),
+# but for flashing 1MHz is more reliable.
+adapter speed 1000
+
+# Delay on reset line.
+adapter srst delay 200
+
+cortex_m reset_config sysresetreq
diff --git a/tcl/target/stm32c0x.cfg b/tcl/target/stm32c0x.cfg
new file mode 100644
index 0000000..d015120
--- /dev/null
+++ b/tcl/target/stm32c0x.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32c0x family
+#
+# stm32c0 devices support SWD transports only.
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32c0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 6kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1800
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # SWD IDCODE (single drop, arm)
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# Enable DBGMCU clock
+	# RCC_APB1ENR |= DBGMCUEN
+	mmw 0x4002103C 0x08000000 0
+
+	# Enable debug during low power modes (uses more power)
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
diff --git a/tcl/target/stm8l151x2.cfg b/tcl/target/stm8l151x2.cfg
new file mode 100644
index 0000000..db88c71
--- /dev/null
+++ b/tcl/target/stm8l151x2.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x2
+# Supported Devices:
+# STM8L151C2
+# STM8L151F2
+# STM8L151G2
+# STM8L151K2
+
+# 1kB RAM
+# Start 0x0000
+# End   0x03ff
+set WORKAREASIZE 1024
+
+# 4kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0x8fff
+
+# 256B EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x10ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x487f
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/tcl/target/stm8l151x3.cfg b/tcl/target/stm8l151x3.cfg
new file mode 100644
index 0000000..fe904b4
--- /dev/null
+++ b/tcl/target/stm8l151x3.cfg
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x3
+# Supported Devices:
+# STM8L151C3
+# STM8L151F3
+# STM8L151G3
+# STM8L151K3
+
+# 1kB RAM
+# Start 0x0000
+# End   0x03ff
+set WORKAREASIZE 1024
+
+# 8kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0x9fff
+
+# 256B EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x10ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x487f
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/tcl/target/stm8l152.cfg b/tcl/target/stm8l152.cfg
index b716ce1..033b826 100644
--- a/tcl/target/stm8l152.cfg
+++ b/tcl/target/stm8l152.cfg
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-#config script for STM8L152
+echo 'DEPRECATED: choose between stm8l15xx4.cfg, stm8l15xx6.cfg and stm8l15xx8.cfg instead of stm8l152.cfg'
+echo '            using stm8l152.cfg for backwards compatability'
 
 set EEPROMSTART 0x1000
 set EEPROMEND 0x13ff
diff --git a/tcl/target/stm8l15xx4.cfg b/tcl/target/stm8l15xx4.cfg
new file mode 100644
index 0000000..4438193
--- /dev/null
+++ b/tcl/target/stm8l15xx4.cfg
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x4/STM8L152x4
+# Supported Devices:
+# STM8L151C4
+# STM8L151G4
+# STM8L151K4
+# STM8L152C4
+# STM8L152K4
+
+# 2kB RAM
+# Start 0x0000
+# End   0x07ff
+set WORKAREASIZE 2048
+
+# 16kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0xbfff
+
+# 1kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x13ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/tcl/target/stm8l15xx6.cfg b/tcl/target/stm8l15xx6.cfg
new file mode 100644
index 0000000..5243295
--- /dev/null
+++ b/tcl/target/stm8l15xx6.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x6/STM8L152x6
+# Supported Devices:
+# STM8L151C6
+# STM8L151G6
+# STM8L151K6
+# STM8L151R6
+# STM8L152C6
+# STM8L152K6
+# STM8L152R6
+
+# 2kB RAM
+# Start 0x0000
+# End   0x07ff
+set WORKAREASIZE 2048
+
+# 32kB Flash
+set FLASHSTART  0x8000
+set FLASHEND    0xffff
+
+# 1kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x13ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/tcl/target/stm8l15xx8.cfg b/tcl/target/stm8l15xx8.cfg
new file mode 100644
index 0000000..e354827
--- /dev/null
+++ b/tcl/target/stm8l15xx8.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Config script for STM8L151x8/STM8L152x8
+# Supported Devices:
+# STM8L151C8
+# STM8L151M8
+# STM8L151R8
+# STM8L152C8
+# STM8L152K8
+# STM8L152M8
+# STM8L152R8
+
+# 4kB RAM
+# Start 0x0000
+# End   0x0fff
+set WORKAREASIZE 4096
+
+# 64kB Flash
+set FLASHSTART  0x08000
+set FLASHEND    0x17fff
+
+# 2kB EEPROM
+set EEPROMSTART 0x1000
+set EEPROMEND   0x17ff
+
+set OPTIONSTART 0x4800
+set OPTIONEND   0x48ff
+
+proc stm8_reset_rop {} {
+   mwb 0x4800 0xaa
+   mwb 0x4800 0xaa
+   reset halt
+}
+
+source [find target/stm8l.cfg]
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index 213fb09..18e0d82 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -22,7 +22,7 @@ source [find target/icepick.cfg]
 if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID $DAP_TAPID
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version
 jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # ICEpick-C (JTAG route controller)
@@ -35,10 +35,7 @@ set _JRC_TAPID2 0x0B7B302F
 set _JRC_TAPID3 0x0B95502F
 set _JRC_TAPID4 0x0B97102F
 set _JRC_TAPID5 0x0D8A002F
-set _JRC_TAPID6 0x2B8A002F
-set _JRC_TAPID7 0x2D8A002F
-set _JRC_TAPID8 0x3B8A002F
-set _JRC_TAPID9 0x3D8A002F
+set _JRC_TAPID6 0x0B8A002F
 
 
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
@@ -48,9 +45,6 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID4 \
 	-expected-id $_JRC_TAPID5 \
 	-expected-id $_JRC_TAPID6 \
-	-expected-id $_JRC_TAPID7 \
-	-expected-id $_JRC_TAPID8 \
-	-expected-id $_JRC_TAPID9 \
 	-ignore-version
 jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
@@ -60,7 +54,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 # Cortex-R4 target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
+	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000
 
 # TMS570 uses quirky BE-32 mode
 $_CHIPNAME.dap ti_be_32_quirks 1
diff --git a/tcl/target/ti_tms570lc43xx.cfg b/tcl/target/ti_tms570lc43xx.cfg
new file mode 100644
index 0000000..ffda989
--- /dev/null
+++ b/tcl/target/ti_tms570lc43xx.cfg
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+set DAP_TAPID 0x0B95A02F
+set JRC_TAPID 0x0B95A02F
+
+source [find target/ti_tms570.cfg]
diff --git a/tcl/target/vd_xtensa_jtag.cfg b/tcl/target/vd_xtensa_jtag.cfg
deleted file mode 100644
index 88f5bcc..0000000
--- a/tcl/target/vd_xtensa_jtag.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# Cadence virtual debug interface
-# for Palladium emulation systems
-#
-
-# TODO: Enable backdoor memory access
-# set _MEMSTART 0x00000000
-# set _MEMSIZE 0x100000
-
-# BFM hierarchical path and input clk period
-vdebug bfm_path dut_top.JTAG 10ns
-# DMA Memories to access backdoor (up to 4)
-# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
-
-# Create Xtensa target first
-source [find target/xtensa.cfg]
-
-# Configure Xtensa core parameters next
-# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
-
-# register target
-proc vdebug_examine_end {} {
-#    vdebug register_target
-}
-
-# Default hooks
-$_TARGETNAME configure -event examine-end { vdebug_examine_end }
diff --git a/tcl/target/xtensa-core-xt8.cfg b/tcl/target/xtensa-core-xt8.cfg
new file mode 100644
index 0000000..e544d78
--- /dev/null
+++ b/tcl/target/xtensa-core-xt8.cfg
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa xt8 target
+
+#  Core definition and ABI
+xtensa xtdef	LX
+xtensa xtopt	arnum           	32
+xtensa xtopt	windowed        	1
+
+
+#  Exception/Interrupt Options
+xtensa xtopt	exceptions      	1
+xtensa xtopt	hipriints       	1
+xtensa xtopt	intlevels       	3
+xtensa xtopt	excmlevel       	1
+
+
+#  Cache Options
+xtensa xtmem	icache          	16	1024	1
+xtensa xtmem	dcache          	16	1024	1	1
+
+
+#  Memory Options
+xtensa xtmem	iram            	0x40000000	1048576
+xtensa xtmem	dram            	0x3ff00000	262144
+xtensa xtmem	srom            	0x50000000	131072
+xtensa xtmem	sram            	0x60000000	4194304
+
+
+#  Memory Protection/Translation Options
+
+
+#  Debug Options
+xtensa xtopt	debuglevel      	3
+xtensa xtopt	ibreaknum       	2
+xtensa xtopt	dbreaknum       	2
+
+
+#  Core Registers
+xtensa xtregs	127
+xtensa xtreg	a0              	0x0000
+xtensa xtreg	a1              	0x0001
+xtensa xtreg	a2              	0x0002
+xtensa xtreg	a3              	0x0003
+xtensa xtreg	a4              	0x0004
+xtensa xtreg	a5              	0x0005
+xtensa xtreg	a6              	0x0006
+xtensa xtreg	a7              	0x0007
+xtensa xtreg	a8              	0x0008
+xtensa xtreg	a9              	0x0009
+xtensa xtreg	a10             	0x000a
+xtensa xtreg	a11             	0x000b
+xtensa xtreg	a12             	0x000c
+xtensa xtreg	a13             	0x000d
+xtensa xtreg	a14             	0x000e
+xtensa xtreg	a15             	0x000f
+xtensa xtreg	pc              	0x0020
+xtensa xtreg	ar0             	0x0100
+xtensa xtreg	ar1             	0x0101
+xtensa xtreg	ar2             	0x0102
+xtensa xtreg	ar3             	0x0103
+xtensa xtreg	ar4             	0x0104
+xtensa xtreg	ar5             	0x0105
+xtensa xtreg	ar6             	0x0106
+xtensa xtreg	ar7             	0x0107
+xtensa xtreg	ar8             	0x0108
+xtensa xtreg	ar9             	0x0109
+xtensa xtreg	ar10            	0x010a
+xtensa xtreg	ar11            	0x010b
+xtensa xtreg	ar12            	0x010c
+xtensa xtreg	ar13            	0x010d
+xtensa xtreg	ar14            	0x010e
+xtensa xtreg	ar15            	0x010f
+xtensa xtreg	ar16            	0x0110
+xtensa xtreg	ar17            	0x0111
+xtensa xtreg	ar18            	0x0112
+xtensa xtreg	ar19            	0x0113
+xtensa xtreg	ar20            	0x0114
+xtensa xtreg	ar21            	0x0115
+xtensa xtreg	ar22            	0x0116
+xtensa xtreg	ar23            	0x0117
+xtensa xtreg	ar24            	0x0118
+xtensa xtreg	ar25            	0x0119
+xtensa xtreg	ar26            	0x011a
+xtensa xtreg	ar27            	0x011b
+xtensa xtreg	ar28            	0x011c
+xtensa xtreg	ar29            	0x011d
+xtensa xtreg	ar30            	0x011e
+xtensa xtreg	ar31            	0x011f
+xtensa xtreg	lbeg            	0x0200
+xtensa xtreg	lend            	0x0201
+xtensa xtreg	lcount          	0x0202
+xtensa xtreg	sar             	0x0203
+xtensa xtreg	windowbase      	0x0248
+xtensa xtreg	windowstart     	0x0249
+xtensa xtreg	configid0       	0x02b0
+xtensa xtreg	configid1       	0x02d0
+xtensa xtreg	ps              	0x02e6
+xtensa xtreg	expstate        	0x03e6
+xtensa xtreg	mmid            	0x0259
+xtensa xtreg	ibreakenable    	0x0260
+xtensa xtreg	ddr             	0x0268
+xtensa xtreg	ibreaka0        	0x0280
+xtensa xtreg	ibreaka1        	0x0281
+xtensa xtreg	dbreaka0        	0x0290
+xtensa xtreg	dbreaka1        	0x0291
+xtensa xtreg	dbreakc0        	0x02a0
+xtensa xtreg	dbreakc1        	0x02a1
+xtensa xtreg	epc1            	0x02b1
+xtensa xtreg	epc2            	0x02b2
+xtensa xtreg	epc3            	0x02b3
+xtensa xtreg	depc            	0x02c0
+xtensa xtreg	eps2            	0x02c2
+xtensa xtreg	eps3            	0x02c3
+xtensa xtreg	excsave1        	0x02d1
+xtensa xtreg	excsave2        	0x02d2
+xtensa xtreg	excsave3        	0x02d3
+xtensa xtreg	interrupt       	0x02e2
+xtensa xtreg	intset          	0x02e2
+xtensa xtreg	intclear        	0x02e3
+xtensa xtreg	intenable       	0x02e4
+xtensa xtreg	exccause        	0x02e8
+xtensa xtreg	debugcause      	0x02e9
+xtensa xtreg	ccount          	0x02ea
+xtensa xtreg	icount          	0x02ec
+xtensa xtreg	icountlevel     	0x02ed
+xtensa xtreg	excvaddr        	0x02ee
+xtensa xtreg	ccompare0       	0x02f0
+xtensa xtreg	ccompare1       	0x02f1
+xtensa xtreg	pwrctl          	0x200f
+xtensa xtreg	pwrstat         	0x2010
+xtensa xtreg	eristat         	0x2011
+xtensa xtreg	cs_itctrl       	0x2012
+xtensa xtreg	cs_claimset     	0x2013
+xtensa xtreg	cs_claimclr     	0x2014
+xtensa xtreg	cs_lockaccess   	0x2015
+xtensa xtreg	cs_lockstatus   	0x2016
+xtensa xtreg	cs_authstatus   	0x2017
+xtensa xtreg	fault_info      	0x2026
+xtensa xtreg	trax_id         	0x2027
+xtensa xtreg	trax_control    	0x2028
+xtensa xtreg	trax_status     	0x2029
+xtensa xtreg	trax_data       	0x202a
+xtensa xtreg	trax_address    	0x202b
+xtensa xtreg	trax_pctrigger  	0x202c
+xtensa xtreg	trax_pcmatch    	0x202d
+xtensa xtreg	trax_delay      	0x202e
+xtensa xtreg	trax_memstart   	0x202f
+xtensa xtreg	trax_memend     	0x2030
+xtensa xtreg	pmg             	0x203e
+xtensa xtreg	pmpc            	0x203f
+xtensa xtreg	pm0             	0x2040
+xtensa xtreg	pm1             	0x2041
+xtensa xtreg	pmctrl0         	0x2042
+xtensa xtreg	pmctrl1         	0x2043
+xtensa xtreg	pmstat0         	0x2044
+xtensa xtreg	pmstat1         	0x2045
+xtensa xtreg	ocdid           	0x2046
+xtensa xtreg	ocd_dcrclr      	0x2047
+xtensa xtreg	ocd_dcrset      	0x2048
+xtensa xtreg	ocd_dsr         	0x2049
+xtensa xtreg	psintlevel      	0x2003
+xtensa xtreg	psum            	0x2004
+xtensa xtreg	pswoe           	0x2005
+xtensa xtreg	psexcm          	0x2006
+xtensa xtreg	pscallinc       	0x2007
+xtensa xtreg	psowb           	0x2008