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| author | micbis <michele.bisogno.ct@renesas.com> | 2022-05-12 15:17:49 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-05-21 09:01:22 +0000 |
| commit | e5f515f990cc345fd3089a5520f39d5a128329bd (patch) | |
| tree | 1d653283b1d70b8aa0a17deeebadc8b964f95b98 /tcl | |
| parent | 19e992e8827a13a9507b64b3a96895e6ed3d714a (diff) | |
| download | riscv-openocd-e5f515f990cc345fd3089a5520f39d5a128329bd.zip riscv-openocd-e5f515f990cc345fd3089a5520f39d5a128329bd.tar.gz riscv-openocd-e5f515f990cc345fd3089a5520f39d5a128329bd.tar.bz2 | |
tcl/target/renesas_rz_five: Added RZ/Five
Added support for the new Renesas RISC-V
device: RZ/Five
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Change-Id: Id8ba29b83528c0bfe4f9b4ed21b0151a6e853bd7
Reviewed-on: https://review.openocd.org/c/openocd/+/6974
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/renesas_rz_five.cfg | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tcl/target/renesas_rz_five.cfg b/tcl/target/renesas_rz_five.cfg new file mode 100644 index 0000000..5ab94ab --- /dev/null +++ b/tcl/target/renesas_rz_five.cfg @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Renesas RZ/Five SoC +# +# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz) + +transport select jtag + +reset_config trst_and_srst srst_gates_jtag +adapter speed 4000 +adapter srst delay 500 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME r9A07g043u +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME |