Merge commit 'bcaac692d0fce45189279a4c80cbd6852e4bbf4e' into from_upstream

Conflicts:
	src/target/breakpoints.c

Change-Id: I815ac06fbe74398fad307112e95fde5c49bbc590

2 files changed, 71 insertions, 6 deletions

diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index 2539be0..0c82c57 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -5,6 +5,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -116,3 +117,51 @@ proc nrf52_recover {} {
 }
 
 add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+	targets $_targetname
+
+	# Read FICR.INFO.PART
+	set PART [mrw 0x10000100]
+
+	switch $PART {
+		0x52840 -
+		0x52833 -
+		0x52832 {
+			if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+				if { [$_chipname.tpiu cget -port-width] != 4 } {
+					echo "Error. Device only supports 4-bit sync traces."
+					return
+				}
+
+				# Set TRACECONFIG.TRACEMUX to enable synchronous trace
+				mmw 0x4000055C 0x00020000 0x00010000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00020000 0x00010000
+				}
+			} else {
+				# Set TRACECONFIG.TRACEMUX to enable SWO
+				mmw 0x4000055C 0x00010000 0x00020000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00010000 0x00020000
+				}
+			}
+		}
+		0x52820 -
+		0x52811 -
+		0x52810 -
+		0x52805 {
+			echo "Error: Device does not support TPIU"
+			return
+		}
+		default {
+			echo "Error: Unknown device"
+			return
+		}
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 01e11c6..1cd85ee 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -248,6 +248,13 @@ switch $_soc {
 	}
 }
 
+proc _get_rtos_type_for_cpu { target_name } {
+	if { [info exists ::RTOS($target_name)] } {
+		return $::RTOS($target_name)
+	}
+	return none
+}
+
 set _CHIPNAME $_soc
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
@@ -260,7 +267,10 @@ set _CTINAME $_CHIPNAME.cti
 
 # sysctrl is always present
 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
 $_TARGETNAME.sysctrl configure -event reset-assert { }
 
 proc sysctrl_up {} {
@@ -303,8 +313,9 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 	cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
 		-baseaddr [lindex $ARMV8_CTIBASE $_core]
 
-	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
+	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
+		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
 
 	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
 
@@ -340,7 +351,7 @@ if { $_v8_smp_debug == 0 } {
 		_armv8_smp_up
 	}
 	# Declare SMP
-	target smp $:::_v8_smp_targets
+	target smp {*}$_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
@@ -350,7 +361,8 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
 	$_TARGETNAME.$_r5_name configure -event gdb-attach {
 		_cpu_no_smp_up
@@ -368,7 +380,8 @@ proc r5_up { args } {
 
 if { $_gp_mcu_cores != 0 } {
 	cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
-	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
 	$_TARGETNAME.gp_mcu configure -event reset-assert { }
 
 	proc gp_mcu_up {} {
@@ -404,4 +417,7 @@ if { 0 == [string compare [adapter name] dmem ] } {
 	} else {
 		puts "ERROR: ${SOC} data is missing to support dmem access!"
 	}
+} else {
+	# AXI AP access port for SoC address map
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
 }