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| author | Clément Burin des Roziers <clement.burin-des-roziers@hikob.com> | 2011-09-16 15:55:54 +0200 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2011-10-03 18:42:39 +0200 |
| commit | da8ce5f2e193b8637202d56c69b22a158a12e32a (patch) | |
| tree | 3e22065eb62a8879656c8e332aa7842ef5db3c82 /tcl | |
| parent | a17adf0601f66617f2203c6d4db168a8e8c55055 (diff) | |
| download | riscv-openocd-da8ce5f2e193b8637202d56c69b22a158a12e32a.zip riscv-openocd-da8ce5f2e193b8637202d56c69b22a158a12e32a.tar.gz riscv-openocd-da8ce5f2e193b8637202d56c69b22a158a12e32a.tar.bz2 | |
STM32L: Added flash driver and target
Added the flash driver for the STM32L family, which highly differ from the STM32F family.
Added the TCL target file for JTAG access.
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/stm32l.cfg | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg new file mode 100644 index 0000000..5c3d368 --- /dev/null +++ b/tcl/target/stm32l.cfg @@ -0,0 +1,81 @@ +# script for stm32l + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32l +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 14kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x3800 +} + +# JTAG speed should be <= F_CPU/6. +# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz +adapter_khz 100 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0038 + # Section 24.6.3 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0038 + # Section 24.6.2 + set _BSTAPID 0x06416041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq + +proc stm32l_enable_HSI {} { + # Enable HSI as clock source + echo "STM32L: Enabling HSI" + + # Set HSION in RCC_CR + mww 0x40023800 0x00000101 + + # Set HSI as SYSCLK + mww 0x40023808 0x00000001 + + # Increase JTAG speed + adapter_khz 2000 +} + +$_TARGETNAME configure -event reset-init { + stm32l_enable_HSI +} + |