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| author | Christopher Head <chead@zaber.com> | 2018-09-14 15:27:34 -0700 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2018-09-27 16:12:44 +0100 |
| commit | bdef93520a4721e1ed4ac4675476772fab064896 (patch) | |
| tree | b61e6fa45e2b48b3d9090a805a7f48c1abdcf8aa /tcl | |
| parent | 723fc07ddc925d101e8d2de1fa1d83e7843e246f (diff) | |
| download | riscv-openocd-bdef93520a4721e1ed4ac4675476772fab064896.zip riscv-openocd-bdef93520a4721e1ed4ac4675476772fab064896.tar.gz riscv-openocd-bdef93520a4721e1ed4ac4675476772fab064896.tar.bz2 | |
target/stm32: make APCSW cacheable
Change-Id: I7c5c9720ded329848647f17db95f845e46c01c19
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4674
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl')
| -rwxr-xr-x | tcl/target/stm32f7x.cfg | 8 | ||||
| -rw-r--r-- | tcl/target/stm32h7x.cfg | 8 |
2 files changed, 16 insertions, 0 deletions
diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg index 562de30..e06a345 100755 --- a/tcl/target/stm32f7x.cfg +++ b/tcl/target/stm32f7x.cfg @@ -145,3 +145,11 @@ $_TARGETNAME configure -event reset-start { # Reduce speed since CPU speed will slow down to 16MHz with the reset adapter_khz 2000 } + +# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal +# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 +# makes the data access cacheable. This allows reading and writing data in the +# CPU cache from the debugger, which is far more useful than going straight to +# RAM when operating on typical variables, and is generally no worse when +# operating on special memory locations. +$_CHIPNAME.dap apcsw 0x08000000 0x08000000 diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 10477a5..e2ea8a8 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -92,3 +92,11 @@ $_TARGETNAME configure -event reset-init { # Clock after reset is HSI at 64 MHz, no need of PLL adapter_khz 4000 } + +# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal +# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 +# makes the data access cacheable. This allows reading and writing data in the +# CPU cache from the debugger, which is far more useful than going straight to +# RAM when operating on typical variables, and is generally no worse when +# operating on special memory locations. +$_CHIPNAME.dap apcsw 0x08000000 0x08000000 |