Merge up to ac63cd00d792331914db0b6edd3f427c30eec3fa from upstream

- src/jtag/drivers/ftdi.c:

```
++<<<<<<< HEAD
 +      int i;
 +      static const uint8_t zero;
++=======
+       uint8_t zero = 0;
++>>>>>>> ocd_upstream
```

Decided to choose the latter.

- src/target/riscv/riscv-013.c:

```
++<<<<<<< HEAD
 +      int abs_chain_position;
 +      /* The base address to access this DM on DMI */
 +      uint32_t base;
++=======
+       unsigned int abs_chain_position;
+
++>>>>>>> ocd_upstream
```

Decided to choose the latter (abs_chain_position is unsigned now)

- src/target/riscv/batch.c:

```
++<<<<<<< HEAD
++=======
+ void dump_field(int idle, const struct scan_field *field)
+ {
  ...
+ }
++>>>>>>> ocd_upstream
```

dump_field function is not needed anymore

Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>

28 files changed, 170 insertions, 34 deletions

diff --git a/tcl/board/actux3.cfg b/tcl/board/actux3.cfg
index edb529c..7c2ce06 100644
--- a/tcl/board/actux3.cfg
+++ b/tcl/board/actux3.cfg
@@ -50,7 +50,7 @@ reset init
 
 # setup to debug u-boot in flash
 proc uboot_debug {} {
-    gdb_breakpoint_override hard
+    gdb breakpoint_override hard
     xscale vector_catch 0xFF
 
     xscale vector_table low  1 0xe59ff018
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 4740471..22a38a7 100644
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -43,7 +43,7 @@ proc read_register {register} {
 
 proc at91sam9g20_reset_start { } {
 
-	# Make sure that the the jtag is running slow, since there are a number of different ways the board
+	# Make sure that the jtag is running slow, since there are a number of different ways the board
 	# can be configured coming into this state that can cause communication problems with the jtag
 	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
 	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
@@ -202,7 +202,7 @@ proc at91sam9g20_reset_init { } {
 	mww 0xffffea00 0x3
 	mww 0x20000000 0
 
-	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
+	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting
 	# memory location for the SDRAM.
 
 	mww 0xffffea00 0x0
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 85d9a35..5642cb1 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -128,7 +128,7 @@ reset_config trst_and_srst
 # GDB Setup
 #-------------------------------------------------------------------------
 
-    gdb_breakpoint_override hard
+    gdb breakpoint_override hard
 
 #------------------------------------------------
 # ARM SPECIFIC
diff --git a/tcl/board/mini6410.cfg b/tcl/board/mini6410.cfg
index 18f9e8d..276e718 100644
--- a/tcl/board/mini6410.cfg
+++ b/tcl/board/mini6410.cfg
@@ -95,7 +95,7 @@ adapter srst delay 100
 jtag_ntrst_delay 100
 reset_config trst_and_srst
 
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
 
 targets
 nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
diff --git a/tcl/board/netgear-wg102.cfg b/tcl/board/netgear-wg102.cfg
index 15f9c11..0a7dad5 100644
--- a/tcl/board/netgear-wg102.cfg
+++ b/tcl/board/netgear-wg102.cfg
@@ -27,7 +27,7 @@ $_TARGETNAME configure -event reset-init {
 	#                 0x00003800 - 0x07 << FLASHCTL_WST2_S
 	# FLASHCTL_AC_8M  0x00060000 - Size of flash
 	# FLASHCTL_E      0x00080000 - Flash bank enable (added)
-	# FLASHCTL_WP     0x04000000 - write protect. If used, CFI mode wont work!!
+	# FLASHCTL_WP     0x04000000 - write protect. If used, CFI mode won't work!!
 	# FLASHCTL_MWx16  0x10000000 - 16bit mode. Do not use it!!
 	# FLASHCTL_MWx8   0x00000000 - 8bit mode.
 	mww 0xb8400000 0x000d3ce1
diff --git a/tcl/board/or1k_generic.cfg b/tcl/board/or1k_generic.cfg
index 915a0de..b6cf3a0 100644
--- a/tcl/board/or1k_generic.cfg
+++ b/tcl/board/or1k_generic.cfg
@@ -22,7 +22,7 @@ poll_period 1
 adapter speed 3000
 
 # Enable the target description feature
-gdb_target_description enable
+gdb target_description enable
 
 # Add a new register in the cpu register list. This register will be
 # included in the generated target descriptor file.
diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg
new file mode 100644
index 0000000..99fc0b0
--- /dev/null
+++ b/tcl/board/ti_am62a7_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM62A7
+# Link: https://www.ti.com/product/AM62A7
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM62A7 platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM62A7 and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am62a7
+}
+
+source [find target/ti_k3.cfg]
diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg
new file mode 100644
index 0000000..fa549f3
--- /dev/null
+++ b/tcl/board/ti_am62p_swd_native.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments am62p
+# Link: https://www.ti.com/product/AM62P
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every AM62P platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside AM62P and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC am62p
+}
+
+source [find target/ti_k3.cfg]
diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg
new file mode 100644
index 0000000..bbe0d50
--- /dev/null
+++ b/tcl/board/ti_j722s_swd_native.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J722S/AM67/TDA4VEN
+# Link: https://www.ti.com/product/AM67
+# Link: https://www.ti.com/product/TDA4VEN-Q1
+#
+# This configuration file is used as a self hosted debug configuration that
+# works on every J722S platform based on firewall configuration permitted
+# in the system.
+#
+# In this system openOCD runs on one of the CPUs inside J722S and provides
+# network ports that can then be used to debug the microcontrollers on the
+# SoC - either self hosted IDE OR remotely.
+
+# We are using dmem, which uses dapdirect_swd transport
+adapter driver dmem
+
+if { ![info exists SOC] } {
+	set SOC j722s
+}
+
+source [find target/ti_k3.cfg]
diff --git a/tcl/interface/nulink.cfg b/tcl/interface/nulink.cfg
index 2a4bc0b..48dc20e 100644
--- a/tcl/interface/nulink.cfg
+++ b/tcl/interface/nulink.cfg
@@ -5,9 +5,9 @@
 #
 
 adapter driver hla
-hla_layout nulink
-hla_device_desc "Nu-Link"
-hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201
+hla layout nulink
+hla device_desc "Nu-Link"
+hla vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201
 
 # Only swd is supported
 transport select hla_swd
diff --git a/tcl/interface/raspberrypi5-gpiod.cfg b/tcl/interface/raspberrypi5-gpiod.cfg
index f3fdde0..9624ad5 100644
--- a/tcl/interface/raspberrypi5-gpiod.cfg
+++ b/tcl/interface/raspberrypi5-gpiod.cfg
@@ -19,8 +19,7 @@ proc read_file { name } {
 }
 
 set pcie_aspm [read_file /sys/module/pcie_aspm/parameters/policy]
-# escaping [ ] characters in string match pattern does not work in Jim-Tcl
-if {![string match "*<performance>*" [string map { "\[" < "\]" > } $pcie_aspm]]} {
+if {![string match {*\[performance\]*} $pcie_aspm]} {
 	echo "Warn : Switch PCIe power saving off or the first couple of pulses gets clocked as fast as 20 MHz"
 	echo "Warn : Issue 'echo performance | sudo tee /sys/module/pcie_aspm/parameters/policy'"
 }
diff --git a/tcl/interface/stlink.cfg b/tcl/interface/stlink.cfg
index 8578bf2..9b7f1f9 100644
--- a/tcl/interface/stlink.cfg
+++ b/tcl/interface/stlink.cfg
@@ -6,9 +6,9 @@
 #
 
 adapter driver hla
-hla_layout stlink
-hla_device_desc "ST-LINK"
-hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
+hla layout stlink
+hla device_desc "ST-LINK"
+hla vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
 
 # Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2
 # devices seem to have serial numbers with unreadable characters.  ST-LINK/V2
diff --git a/tcl/interface/ti-icdi.cfg b/tcl/interface/ti-icdi.cfg
index db4e1e0..c13d27e 100644
--- a/tcl/interface/ti-icdi.cfg
+++ b/tcl/interface/ti-icdi.cfg
@@ -10,8 +10,8 @@
 #
 
 adapter driver hla
-hla_layout ti-icdi
-hla_vid_pid 0x1cbe 0x00fd
+hla layout ti-icdi
+hla vid_pid 0x1cbe 0x00fd
 
 # Optionally specify the serial number of TI-ICDI devices, for when using
 # multiple devices. Serial numbers can be obtained using lsusb -v
diff --git a/tcl/interface/vdebug.cfg b/tcl/interface/vdebug.cfg
index 7350bb9..9097c33 100644
--- a/tcl/interface/vdebug.cfg
+++ b/tcl/interface/vdebug.cfg
@@ -22,9 +22,9 @@ vdebug server $_VDEBUGHOST:$_VDEBUGPORT
 
 # example config listen on all interfaces, disable tcl/telnet server
 bindto 0.0.0.0
-#gdb_port 3333
+#gdb port 3333
 #telnet_port disabled
-tcl_port disabled
+tcl port disabled
 
 # transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw
 vdebug batching 1
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
index 437bd95..6c3435e 100644
--- a/tcl/target/allwinner_v3s.cfg
+++ b/tcl/target/allwinner_v3s.cfg
@@ -28,7 +28,7 @@
 # UART2_TX	PB0			Per default disabled
 # UART2_RX	PB1	 		Per default disabled
 #
-# JTAG is enabled by default after power on on listed JTAG_* pins. So far the
+# JTAG is enabled by default after power-on on listed JTAG_* pins. So far the
 # boot sequence is:
 # Time		Action
 # 0000ms	Power ON
diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg
index 0b0bd9e..fd68fcd 100644
--- a/tcl/target/ampere_emag.cfg
+++ b/tcl/target/ampere_emag.cfg
@@ -8,7 +8,7 @@
 
 #
 # Configure defaults for target
-# Can be overriden in board configuration file
+# Can be overridden in board configuration file
 #
 
 if { [info exists CHIPNAME] } {
diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg
new file mode 100644
index 0000000..6d4a048
--- /dev/null
+++ b/tcl/target/bl702.cfg
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL702, BL704 and BL706 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=8
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TMS - GPIO0
+# TDI - GPIO1
+# TCK - GPIO2
+# TDO - GPIO9
+#
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME bl702
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+
+$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 4000
+
+$_TARGETNAME configure -event reset-assert-pre {
+	halt
+
+	# Switch clock to internal RC32M
+	# In HBN_GLB, set ROOT_CLK_SEL = 0
+	mmw 0x4000f030 0x0 0x00000003
+	# Wait for clock switch
+	sleep 10
+
+	# GLB_REG_BCLK_DIS_FALSE
+	mww 0x40000ffc 0x0
+
+	# HCLK is RC32M, so BCLK/HCLK doesn't need divider
+	# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+	mmw 0x40000000 0x0 0x00FFFF00
+	# Wait for clock to stabilize
+	sleep 10
+
+	# Do reset
+	# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
+	mmw 0x40000018 0x0 0x00000007
+	# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
+	mmw 0x40000018 0x6 0x0
+}
diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg
index a8b0823..d29c636 100644
--- a/tcl/target/esi32xx.cfg
+++ b/tcl/target/esi32xx.cfg
@@ -35,4 +35,4 @@ reset_config none
 # The default linker scripts provided by the eSi-RISC toolchain do not
 # specify attributes on memory regions, which results in incorrect
 # application of software breakpoints by GDB.
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
index af2f6ad..5ea9bc8 100644
--- a/tcl/target/esp_common.cfg
+++ b/tcl/target/esp_common.cfg
@@ -200,7 +200,7 @@ proc configure_esp_xtensa_default_settings { } {
 		$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
 	}
 
-	gdb_breakpoint_override hard
+	gdb breakpoint_override hard
 
 	if { [info exists _FLASH_VOLTAGE] } {
 		$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 5509532..e5d5706 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -6,7 +6,7 @@
 #
 
 # Utilities for TI ICEpick-C/D used in most TI SoCs
-# Details about the ICEPick are available in the the TRM for each SoC
+# Details about the ICEPick are available in the TRM for each SoC
 # and http://processors.wiki.ti.com/index.php/ICEPICK
 
 # create "constants"
diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index a448550..4bc7fe1 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
 $_CHIPNAME.m31 configure -event reset-assert { }
 
 # Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg
index bbc824b..85ba96c 100644
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/omap4460.cfg
@@ -128,4 +128,4 @@ $_CHIPNAME.m30 configure -event reset-assert { }
 $_CHIPNAME.m31 configure -event reset-assert { }
 
 # Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index 2d670b9..78c456d 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -64,5 +64,5 @@ arm7_9 dcc_downloads enable
 etm config $_TARGETNAME 16 normal full etb
 etb config $_TARGETNAME $_CHIPNAME.etb
 
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
 arm7_9 dbgrq enable
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index d69515c..52b04f5 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -113,7 +113,7 @@ proc psoc6_deassert_post { target } {
 }
 
 if { $_ENABLE_CM0 } {
-	target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
+	target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1
 	${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
 
 	flash bank main_flash_cm0		psoc6 0x10000000 0 0 0 ${TARGET}.cm0
@@ -128,7 +128,7 @@ if { $_ENABLE_CM0 } {
 }
 
 if { $_ENABLE_CM4 } {
-	target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
+	target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2
 	${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
 
 	flash bank main_flash_cm4		psoc6 0x10000000 0 0 0 ${TARGET}.cm4
diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg
index de76b4e..5e78c69 100644
--- a/tcl/target/rp2040.cfg
+++ b/tcl/target/rp2040.cfg
@@ -96,7 +96,7 @@ if { $_USE_CORE == 1 } {
 	set _FLASH_TARGET $_TARGETNAME_0
 }
 # Backup the work area. The flash probe runs an algorithm on the target CPU.
-# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+# The flash is probed during gdb connect if gdb memory_map is enabled (by default).
 $_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index ebea821..2ae0f75 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -209,6 +209,16 @@ switch $_soc {
 		# Sysctrl power-ap unlock offsets
 		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
 
+		# Setup DMEM access descriptions
+		# DAPBUS (Debugger) description
+		set _dmem_base_address 0x740002000
+		set _dmem_ap_address_offset 0x100
+		set _dmem_max_aps 10
+		# Emulated AP description
+		set _dmem_emu_base_address 0x760000000
+		set _dmem_emu_base_address_map_to 0x1d500000
+		set _dmem_emu_ap_list 1
+
 		# Overrides for am62p
 		if { "$_soc" == "am62p" } {
 			set _K3_DAP_TAPID 0x0bb9d02f
diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index 417fdd1..b87d261 100644
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -142,9 +142,9 @@ proc enable_apetap {} {
 	}
 	}
 
-tcl_port 5555
+tcl port 5555
 telnet_port 4444
-gdb_port 3333
+gdb port 3333
 
 if { [info exists CHIPNAME] } {
 global _CHIPNAME
@@ -319,7 +319,7 @@ global _MAXSPEED
 adapter speed $_MAXSPEED
 
 
-gdb_breakpoint_override hard
+gdb breakpoint_override hard
 set mem inaccessible-by-default-off
 
 jtag_ntrst_delay 100
diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg
index 561131d..c277673 100644
--- a/tcl/target/xtensa.cfg
+++ b/tcl/target/xtensa.cfg
@@ -67,4 +67,4 @@ if { $_XTENSA_NUM_CORES == 1 } {
 	$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
 }
 
-gdb_report_register_access_error enable
+gdb report_register_access_error enable