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authorliangzhen <zhen.liang@spacemit.com>2024-09-02 20:21:48 +0800
committerAntonio Borneo <borneo.antonio@gmail.com>2024-09-15 09:18:35 +0000
commit84d196673e1d24898c588423870ea0f0ab39d9be (patch)
tree505fc239af8c8a5b522795bc8a28783e40b6f2cd /tcl
parent0261cd995888e83f6099f0d94a5e9a96a47bc609 (diff)
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tcl/target: Add SpacemiT Key Stone K1 config
Add basic connection details with Key Stone K1 Change-Id: I3e51d4194cfd3b7fe8ae395e0aca0fa4799dfb73 Signed-off-by: liangzhen <zhen.liang@spacemit.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8361 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
Diffstat (limited to 'tcl')
-rw-r--r--tcl/target/spacemit-k1.cfg74
1 files changed, 74 insertions, 0 deletions
diff --git a/tcl/target/spacemit-k1.cfg b/tcl/target/spacemit-k1.cfg
new file mode 100644
index 0000000..ef5d783
--- /dev/null
+++ b/tcl/target/spacemit-k1.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SpacemiT Key Stone K1 target
+#
+# https://www.spacemit.com/key-stone-k1
+#
+
+transport select jtag
+
+adapter speed 2000
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME k1
+}
+
+if { [info exists CORES] } {
+ set _cores $CORES
+} else {
+ set _cores 1
+}
+
+if { [info exists SECJTAG] } {
+ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21
+} else {
+ jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
+ jtag configure pre.unknown -event tap-enable ""
+
+ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10000E21 -disable
+ jtag configure $_CHIPNAME.cpu -event tap-enable ""
+
+ jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
+
+ jtag configure post.unknown -event setup {
+ global _CHIPNAME
+
+ irscan post.unknown 0x98
+ drscan post.unknown 16 0xa
+
+ jtag tapenable pre.unknown
+ jtag tapenable $_CHIPNAME.cpu
+ }
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+set DBGBASE {0x0 0x400}
+set _smp_command "target smp"
+
+for { set _core 0 } { $_core < $_cores } { incr _core } {
+ target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME \
+ -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]]
+
+ if { [expr {$_core % 4}] == 0 } {
+ $_TARGETNAME.$_core configure -rtos hwthread
+ }
+
+ set _smp_command "$_smp_command $_TARGETNAME.$_core"
+}
+
+eval $_smp_command
+
+set _SPEED 8000
+
+$_TARGETNAME.0 configure -event examine-start {
+ adapter speed $_SPEED
+ puts [ adapter speed ]
+}
+
+foreach t [target names] {
+ # $t riscv set_mem_access sysbus progbuf
+ $t riscv set_mem_access progbuf
+}