Merge commit '4b1ea8511a7da9d7201df40302e3341c6e97ffdd' into from_upstream

Change-Id: I59366e08a4ac7e443e426b5fd6727c649f1ac9d5

18 files changed, 357 insertions, 16 deletions

diff --git a/tcl/board/bemicro_cycloneiii.cfg b/tcl/board/bemicro_cycloneiii.cfg
index 95dd394..bd1459a 100644
--- a/tcl/board/bemicro_cycloneiii.cfg
+++ b/tcl/board/bemicro_cycloneiii.cfg
@@ -16,5 +16,9 @@ source [find fpga/altera-cycloneiii.cfg]
 
 #quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
 
-#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load 0 cycloneiii_blinker.rbf"
+#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load cycloneiii.pld cycloneiii_blinker.rbf"
 # "ipdbg -start -tap cycloneiii.tap -hub 0x00e -tool 0 -port 5555"
+
+
+set JTAGSPI_CHAIN_ID cycloneiii.pld
+source [find cpld/jtagspi.cfg]
diff --git a/tcl/board/certuspro_evaluation.cfg b/tcl/board/certuspro_evaluation.cfg
index 5ff2a1e..ba2f17c 100644
--- a/tcl/board/certuspro_evaluation.cfg
+++ b/tcl/board/certuspro_evaluation.cfg
@@ -12,3 +12,11 @@ transport select jtag
 adapter speed 10000
 
 source [find fpga/lattice_certuspro.cfg]
+
+#openocd -f board/certuspro_evaluation.cfg -c "init" -c "pld load certuspro.pld shared_folder/certuspro_blinker_impl_1.bit"
+
+set JTAGSPI_CHAIN_ID certuspro.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init certuspro.pld "" -1
+#jtagspi_program shared_folder/certuspro_blinker_impl1.bit 0
diff --git a/tcl/board/digilent_cmod_s7.cfg b/tcl/board/digilent_cmod_s7.cfg
new file mode 100644
index 0000000..c52ee95
--- /dev/null
+++ b/tcl/board/digilent_cmod_s7.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# digilent CMOD S7
+# https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0x6010
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find cpld/xilinx-xc7.cfg]
+
+# "ipdbg -start -tap xc7.tap -hub 0x02 -tool 0 -port 5555"
+#openocd -f board/digilent_cmod_s7.cfg -c "init" -c "pld load xc7.pld shared_folder/cmod_s7_fast.bit"
+
+set JTAGSPI_CHAIN_ID xc7.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init xc7.pld "shared_folder/bscan_spi_xc7s25.bit" 0xab
+#jtagspi_program shared_folder/cmod_s7_fast.bit 0
diff --git a/tcl/board/ecp5_evaluation.cfg b/tcl/board/ecp5_evaluation.cfg
index 427037b..dd663f7 100644
--- a/tcl/board/ecp5_evaluation.cfg
+++ b/tcl/board/ecp5_evaluation.cfg
@@ -15,5 +15,11 @@ adapter speed 6000
 
 source [find fpga/lattice_ecp5.cfg]
 
-#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load 0 shared_folder/ecp5_blinker_impl1.bit"
+#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load ecp5.pld shared_folder/ecp5_blinker_impl1.bit"
 #ipdbg -start -tap ecp5.tap -hub 0x32 -port 5555 -tool 0
+
+set JTAGSPI_CHAIN_ID ecp5.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init ecp5.pld "" -1
+#jtagspi_program shared_folder/ecp5_blinker_impl1_slow.bit 0
diff --git a/tcl/board/gatemate_eval.cfg b/tcl/board/gatemate_eval.cfg
index cc078a0..c4d3f3d 100644
--- a/tcl/board/gatemate_eval.cfg
+++ b/tcl/board/gatemate_eval.cfg
@@ -14,3 +14,9 @@ transport select jtag
 adapter speed 6000
 
 source [find fpga/gatemate.cfg]
+
+set JTAGSPI_CHAIN_ID gatemate.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init gatemate.pld "" -1
+#jtagspi_program workspace/blink/blink_slow.cfg.bit 0
diff --git a/tcl/board/ti_am62pevm.cfg b/tcl/board/ti_am62pevm.cfg
new file mode 100644
index 0000000..2322b3d
--- /dev/null
+++ b/tcl/board/ti_am62pevm.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments SK-AM62P: https://www.ti.com/lit/zip/sprr487
+#
+
+# AM62P SK/EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC am62p
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/tcl/board/ti_j784s4evm.cfg b/tcl/board/ti_j784s4evm.cfg
new file mode 100644
index 0000000..d23dc8c
--- /dev/null
+++ b/tcl/board/ti_j784s4evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J784S4 EVM: https://www.ti.com/tool/J784S4XEVM
+# Texas Instruments SK-AM69: https://www.ti.com/tool/SK-AM69
+#
+
+# J784S4/AM69 SK/EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+	set SOC j784s4
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
diff --git a/tcl/board/trion_t20_bga256.cfg b/tcl/board/trion_t20_bga256.cfg
index 045d63d..dc76d39 100644
--- a/tcl/board/trion_t20_bga256.cfg
+++ b/tcl/board/trion_t20_bga256.cfg
@@ -19,6 +19,11 @@ adapter speed 6000
 
 source [find fpga/efinix_trion.cfg]
 
-#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load 0 outflow/trion_blinker.bit"
+#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load trion.pld outflow/trion_blinker.bit"
 #ipdbg -start -tap trion.tap -hub 0x8 -port 5555 -tool 0
 
+set JTAGSPI_CHAIN_ID trion.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init trion.pld "trion_jtagspi/outflow/trion_jtagspi.bit" 0xAB
+#jtagspi_program trion_blinker/outflow/trion_blinker.bin 0
diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg
index 4c84792..a7f02b9 100644
--- a/tcl/cpld/jtagspi.cfg
+++ b/tcl/cpld/jtagspi.cfg
@@ -4,6 +4,8 @@ set _USER1 0x02
 
 if { [info exists JTAGSPI_IR] } {
 	set _JTAGSPI_IR $JTAGSPI_IR
+} elseif {[info exists JTAGSPI_CHAIN_ID]} {
+	set _JTAGSPI_CHAIN_ID $JTAGSPI_CHAIN_ID
 } else {
 	set _JTAGSPI_IR $_USER1
 }
@@ -21,7 +23,11 @@ if { [info exists FLASHNAME] } {
 }
 
 target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
-flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
+if { [info exists _JTAGSPI_IR] } {
+	flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
+} else {
+    flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
+}
 
 # initialize jtagspi flash
 # chain_id: identifier of pld (you can get a list with 'pld devices')
@@ -33,7 +39,9 @@ flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
 proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} {
 	# load proxy bitstream $proxy_bit and probe spi flash
 	global _FLASHNAME
-	pld load $chain_id $proxy_bit
+	if { $proxy_bit ne "" } {
+		pld load $chain_id $proxy_bit
+	}
 	reset halt
 	if {$release_from_pwr_down_cmd != -1} {
 		jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd
diff --git a/tcl/interface/ftdi/digilent-hs2.cfg b/tcl/interface/ftdi/digilent-hs2.cfg
index e9fe94e..89c9e4b 100644
--- a/tcl/interface/ftdi/digilent-hs2.cfg
+++ b/tcl/interface/ftdi/digilent-hs2.cfg
@@ -2,11 +2,17 @@
 
 # this supports JTAG-HS2 (and apparently Nexys4 as well)
 
+# ADBUS5 controls TMS tri-state buffer enable
+# ACBUS6=SEL_TMS controls mux to TMS output buffer: 0=TMS 1=TDI
+# ACBUS5=SEL_TDO controls mux to TDO input: 0=TDO 1=TMS
+
 adapter driver ftdi
 ftdi device_desc "Digilent Adept USB Device"
 ftdi vid_pid 0x0403 0x6014
 
 ftdi channel 0
 ftdi layout_init 0x00e8 0x60eb
+ftdi layout_signal SWD_EN -data 0x6000
+ftdi layout_signal SWDIO_OE -data 0x20
 
 reset_config none
diff --git a/tcl/target/cavium_cn61xx.cfg b/tcl/target/cavium_cn61xx.cfg
new file mode 100644
index 0000000..60b56a5
--- /dev/null
+++ b/tcl/target/cavium_cn61xx.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Cavium Octeon II CN61xx (PrID 0x000D9301)
+
+jtag newtap cpu tap0 -irlen 5
+jtag newtap cpu tap1 -irlen 5
+
+target create cpu.core0 mips_mips64 -chain-position cpu.tap0 -endian big -rtos hwthread -coreid 0
+target create cpu.core1 mips_mips64 -chain-position cpu.tap1 -endian big -rtos hwthread -coreid 1
+target smp cpu.core0 cpu.core1
+
+cpu.core0 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+cpu.core1 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+
+targets cpu.core0
diff --git a/tcl/target/netl_xlp304.cfg b/tcl/target/netl_xlp304.cfg
new file mode 100644
index 0000000..27c30a0
--- /dev/null
+++ b/tcl/target/netl_xlp304.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP304 processor by NetLogic Microsystems
+#
+
+set XLP_NT 4
+source [find target/netl_xlp3xx.cfg]
diff --git a/tcl/target/netl_xlp308.cfg b/tcl/target/netl_xlp308.cfg
new file mode 100644
index 0000000..c3ba11e
--- /dev/null
+++ b/tcl/target/netl_xlp308.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP308 processor by NetLogic Microsystems
+#
+
+set XLP_NT 8
+source [find target/netl_xlp3xx.cfg]
diff --git a/tcl/target/netl_xlp316.cfg b/tcl/target/netl_xlp316.cfg
new file mode 100644
index 0000000..961b67f
--- /dev/null
+++ b/tcl/target/netl_xlp316.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP316 processor by NetLogic Microsystems
+#
+
+set XLP_NT 16
+source [find target/netl_xlp3xx.cfg]
diff --git a/tcl/target/netl_xlp3xx.cfg b/tcl/target/netl_xlp3xx.cfg
new file mode 100644
index 0000000..2366503
--- /dev/null
+++ b/tcl/target/netl_xlp3xx.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP 300-series processors by NetLogic Microsystems
+#
+# See http://www.broadcom.com/products/Processors/Enterprise/XLP300-Series
+#
+# Use xlp304.cfg, xlp308.cfg, xlp316.cfg for particular processor model.
+#
+
+transport select jtag
+
+global XLP_NT
+
+for {set i $XLP_NT} {$i > 0} {incr i -1} {
+	jtag newtap xlp cpu_$i -irlen 5 -disable
+	if {$i != 1} {
+		jtag configure xlp.cpu_$i -event tap-enable {}
+	}
+}
+jtag newtap xlp jrc -irlen 16 -expected-id 0x00011449
+
+jtag configure xlp.cpu_1 -event tap-enable {
+	global XLP_NT
+	irscan xlp.jrc 0xe0
+	drscan xlp.jrc 1 1
+	for {set i $XLP_NT} {$i > 1} {incr i -1} {
+		jtag tapenable xlp.cpu_$i
+	}
+}
+
+proc chipreset {} {
+	irscan xlp.jrc 0xab
+	drscan xlp.jrc 1 1
+	drscan xlp.jrc 1 0
+}
+
+jtag configure xlp.jrc -event setup "jtag tapenable xlp.cpu_1"
+
+target create xlp.cpu_1 mips_mips64 -endian big -chain-position xlp.cpu_1
diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg
index 1a21e1f..84bb0b7 100644
--- a/tcl/target/npcx.cfg
+++ b/tcl/target/npcx.cfg
@@ -9,7 +9,7 @@ source [find target/swj-dp.tcl]
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
 } else {
-	set _CHIPNAME NPCX_M4
+	set _CHIPNAME npcx
 }
 
 # SWD DAP ID of Nuvoton NPCX Cortex-M4.
@@ -27,6 +27,12 @@ if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE 0x8000
 }
 
+if { [info exists FIUNAME]} {
+   set _FIUNAME $FIUNAME
+} else {
+   set _FIUNAME npcx.fiu
+}
+
 # Debug Adapter Target Settings
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
@@ -48,4 +54,4 @@ cortex_m reset_config sysresetreq
 
 # flash configuration
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME $_FIUNAME
diff --git a/tcl/target/stm32wbax.cfg b/tcl/target/stm32wbax.cfg
new file mode 100644
index 0000000..1299407
--- /dev/null
+++ b/tcl/target/stm32wbax.cfg
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbax family
+
+#
+# stm32wba devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME stm32wbax
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    if { [using_jtag] } {
+        set _CPUTAPID 0x6ba00477
+    } else {
+        # SWD IDCODE (single drop, arm)
+        set _CPUTAPID 0x6ba02477
+    }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+    jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+    jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # CPU comes out of reset with HSION | HSIRDY.
+    # Use HSI 16 MHz clock, compliant even with VOS == 2.
+    # 1 WS compliant with VOS == 2 and 16 MHz.
+    mmw 0x40022000 0x00000001 0x0000000E	;# FLASH_ACR: Latency = 1
+    mmw 0x56020C00 0x00000100 0x00000000	;# RCC_CR |= HSION
+    mmw 0x56020C1C 0x00000000 0x00000002	;# RCC_CFGR1: SW=HSI16
+    # Boost JTAG frequency
+    adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+    # Reset clock is HSI (16 MHz)
+    adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+    # Enable debug during low power modes (uses more power)
+    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+    mmw 0xE0042004 0x00000006 0
+
+    # Stop watchdog counters during halt
+    # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
+    mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+    targets $_targetname
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index f0881cd..01e11c6 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -10,12 +10,16 @@
 #  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
 # * J721S2: https://www.ti.com/lit/pdf/spruj28
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
+# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
+#  Has 8 ARMV8 Cores and 8 R5 Cores
 # * AM642: https://www.ti.com/lit/pdf/spruim2
 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
 #  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
 # * AM62a7: https://www.ti.com/lit/pdf/spruj16a
 #  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM62P: https://www.ti.com/lit/pdf/spruj83
+#  Has 4 ARMV8 Cores and 2 R5 Cores
 #
 
 source [find target/swj-dp.tcl]
@@ -63,7 +67,6 @@ set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 # Set configuration overrides for each SOC
 switch $_soc {
 	am654 {
-		set _CHIPNAME am654
 		set _K3_DAP_TAPID 0x0bb5a02f
 
 		# AM654 has 2 clusters of 2 A53 cores each.
@@ -78,7 +81,6 @@ switch $_soc {
 		set _sysctrl_ap_unlock_offsets {0xf0 0x50}
 	}
 	am642 {
-		set _CHIPNAME am642
 		set _K3_DAP_TAPID 0x0bb3802f
 
 		# AM642 has 1 clusters of 2 A53 cores each.
@@ -97,7 +99,6 @@ switch $_soc {
 		set _gp_mcu_cores 1
 	}
 	am625 {
-		set _CHIPNAME am625
 		set _K3_DAP_TAPID 0x0bb7e02f
 
 		# AM625 has 1 clusters of 4 A53 cores.
@@ -131,17 +132,17 @@ switch $_soc {
 		set _dmem_emu_base_address_map_to 0x1d500000
 		set _dmem_emu_ap_list 1
 	}
+	am62p -
 	am62a7 {
-		set _CHIPNAME am62a7
 		set _K3_DAP_TAPID 0x0bb8d02f
 
-		# AM62a7 has 1 clusters of 4 A53 cores.
+		# AM62a7/AM62P has 1 cluster of 4 A53 cores.
 		set _armv8_cpu_name a53
 		set _armv8_cores 4
 		set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
 		set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
 
-		# AM62a7 has 2 cluster of 1 R5s core.
+		# AM62a7/AM62P has 2 cluster of 1 R5 core.
 		set _r5_cores 2
 		set R5_NAMES {main0_r5.0 mcu0_r5.0}
 		set R5_DBGBASE {0x9d410000 0x9d810000}
@@ -151,9 +152,14 @@ switch $_soc {
 		set CM3_CTIBASE {0x20001000}
 		# Sysctrl power-ap unlock offsets
 		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+		# Overrides for am62p
+		if { "$_soc" == "am62p" } {
+			set _K3_DAP_TAPID 0x0bb9d02f
+			set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
+		}
 	}
 	j721e {
-		set _CHIPNAME j721e
 		set _K3_DAP_TAPID 0x0bb6402f
 		# J721E has 1 cluster of 2 A72 cores.
 		set _armv8_cpu_name a72
@@ -173,7 +179,6 @@ switch $_soc {
 		set _dmem_emu_ap_list 1
 	}
 	j7200 {
-		set _CHIPNAME j7200
 		set _K3_DAP_TAPID 0x0bb6d02f
 
 		# J7200 has 1 cluster of 2 A72 cores.
@@ -189,7 +194,6 @@ switch $_soc {
 		set CM3_CTIBASE {0x20001000}
 	}
 	j721s2 {
-		set _CHIPNAME j721s2
 		set _K3_DAP_TAPID 0x0bb7502f
 
 		# J721s2 has 1 cluster of 2 A72 cores.
@@ -208,11 +212,44 @@ switch $_soc {
 		set _gp_mcu_cores 1
 		set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
 	}
+	j784s4 {
+		set _K3_DAP_TAPID 0x0bb8002f
+
+		# j784s4 has 2 cluster of 4 A72 cores each.
+		set _armv8_cpu_name a72
+		set _armv8_cores 8
+		set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
+                           0x90810000 0x90910000 0x90a10000 0x90b10000}
+		set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
+                           0x90820000 0x90920000 0x90a20000 0x90b20000}
+
+		# J721s2 has 4 clusters of 2 R5 cores each.
+		set _r5_cores 8
+		set R5_DBGBASE {0x9d010000 0x9d012000
+                        0x9d410000 0x9d412000
+                        0x9d510000 0x9d512000
+                        0x9d610000 0x9d612000}
+		set R5_CTIBASE {0x9d018000 0x9d019000
+                        0x9d418000 0x9d419000
+                        0x9d518000 0x9d519000
+                        0x9d618000 0x9d619000}
+		set R5_NAMES {mcu_r5.0 mcu_r5.1
+                      main0_r5.0 main0_r5.1
+                      main1_r5.0 main1_r5.1
+                      main2_r5.0 main2_r5.1}
+
+		# sysctrl CTI base
+		set CM3_CTIBASE {0x20001000}
+		# Sysctrl power-ap unlock offsets
+		set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+	}
 	default {
 		echo "'$_soc' is invalid!"
 	}
 }
 
+set _CHIPNAME $_soc
+
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu