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| author | Tomas Vanek <vanekt@fbl.cz> | 2021-11-17 17:33:29 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2022-04-24 08:27:06 +0000 |
| commit | 1c07229f8ca72e0f244e2289cefa28b65e21e774 (patch) | |
| tree | a4b91e126835dc677c4175f1b028ddc6787006a3 /tcl | |
| parent | f2b4897773a1c9db185dfb61d474055559fd507a (diff) | |
| download | riscv-openocd-1c07229f8ca72e0f244e2289cefa28b65e21e774.zip riscv-openocd-1c07229f8ca72e0f244e2289cefa28b65e21e774.tar.gz riscv-openocd-1c07229f8ca72e0f244e2289cefa28b65e21e774.tar.bz2 | |
tcl/target/gd32vf103: add flash bank
The flash is compatible with stm32f1x, reuse the driver.
Extend the size of work area to RAM size of the smallest device.
Stop watchdogs before flash programming.
Change-Id: I67a7654a6e196f9d4b2409edaa7990c53334437e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6711
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/gd32vf103.cfg | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg index 0f4dcf3..cfc6478 100644 --- a/tcl/target/gd32vf103.cfg +++ b/tcl/target/gd32vf103.cfg @@ -4,6 +4,8 @@ # https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/ # +source [find mem_helper.tcl] + transport select jtag if { [info exists CHIPNAME] } { @@ -12,10 +14,11 @@ if { [info exists CHIPNAME] } { set _CHIPNAME gd32vf103 } +# The smallest RAM size 6kB (GD32VF103C4/T4/R4) if { [info exists WORKAREASIZE] } { set _WORKAREASIZE $WORKAREASIZE } else { - set _WORKAREASIZE 0x800 + set _WORKAREASIZE 0x1800 } jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d @@ -24,3 +27,14 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + +# DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU +# does not allow the debugger to access memory. +# Stop watchdogs at least before flash programming. +$_TARGETNAME configure -event reset-init { + # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP + mmw 0xE0042004 0x00000300 0 +} |